JP3089192B2 - IC test equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an integrated circuit (IC).
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC test apparatus for inspecting electrical characteristics of an IC, and more particularly, to an IC test apparatus capable of inspecting at a double speed of the maximum operation speed in the apparatus.

[0002]

2. Description of the Related Art In order to ship an IC whose performance and quality are guaranteed as a final product, it is necessary to extract all or a part of the IC product in each process of a manufacturing department and an inspection department and to inspect its electrical characteristics. There is. An IC test device is a device for inspecting such electrical characteristics. The IC test apparatus gives predetermined test pattern data to the IC under test, reads the output data of the IC under test, and determines whether there is any problem in the basic operation and function of the IC under test. The failure information is analyzed from the data and the electrical characteristics are inspected.

[0003] DC tests (D
C measurement test) and a function test (FC measurement test). For DC test, D
By applying a predetermined voltage or current from the C measuring means, it is checked whether there is any defect in the basic operation of the IC to be measured. On the other hand, in the function test, predetermined test pattern data is given to the input terminal of the IC under test from the pattern generation means, and the output data of the IC under test is read, and there is no problem in the basic operation and function of the IC under test. It is to check whether or not.

FIG. 2 is a block diagram showing a schematic configuration of a conventional IC test apparatus. The IC test apparatus is roughly divided into a tester section 50 and an IC mounting apparatus 70. The tester unit 50 includes a control unit 51, a DC measurement unit 52, a timing generation unit 5
3. It comprises a pattern generating means 54, a pin control means 55, a pin electronics 56, a fail memory 57 and an input / output switching means 58. In the actual tester section 50,
There are various other components, but only necessary parts are shown in this specification.

The tester unit 50 and the IC mounting device 70 are connected by signal lines including a plurality (m) of coaxial cables or the like corresponding to the total number of input / output terminals (m) of the IC mounting device 70. The connection relationship between the terminal and the coaxial cable is associated with each other by a relay matrix (not shown), and transmission of various signals is performed between a predetermined terminal and the coaxial cable. Note that there are physically as many signal lines as the number m of all input / output terminals of the IC mounting device 70.

The IC mounting device 70 includes a plurality of ICs to be measured.
71 is configured to be mounted on a socket. The input / output terminal of the IC 71 to be measured and the input / output terminal of the IC mounting device 70 are connected in one-to-one correspondence. For example, if the IC 71 to be measured having 28 input / output terminals is 1
In the case of the IC mounting device 70 capable of mounting zero ICs, a total of 28
It has zero input / output terminals. The control means 51 controls, operates and manages the entire IC test apparatus, and has a microprocessor configuration. Therefore,
Although not shown, an RO for storing the system program
It has a RAM for storing M and various data.

The control means 51 includes a bus (data bus, data bus) for the DC measurement means 52, the timing generation means 53, the pattern generation means 54, the pin control means 55, and the fail memory 57.
(Address bus, control bus) 65. The control means 51 outputs the DC test data to the DC measurement means 52, the function test start signal to the timing generation means 53, the test pattern generation data and the like to the pattern generation means 54, and the expected value data and the like to the It outputs to the control means 55, respectively. In addition, the control means 51
Outputs various data to each component via a bus. Further, the control means 51 includes a fail memory 57.
Then, the test results (fail data and DC data) are read out from the DC measuring means 52, and various data processings and the like are performed, and the test data is analyzed to judge the quality of the IC.

The DC measuring means 52 receives the DC test data from the control means 51 and performs a DC test on the IC 71 to be measured of the IC mounting device 70 based on the data. DC
The measuring means 52 starts a DC test by inputting a measurement start signal from the control means 51, and writes data indicating the test result into an internal register. When the writing of the test result data is completed, the DC measuring means 52 outputs an end signal to the control means 51. The data indicating the test result written in the internal register of the DC measuring means 52 is read by the control means 51 via the bus 65 and analyzed there. Thus, the DC test is performed. DC measurement means 5
2 are reference voltages VIH, VIL, VO for the driver 63 and the comparator 64 of the pin electronics 56.
H and VOL are output.

The timing generation means 53 outputs a predetermined clock to the pin control means 55,
It controls the operation speed and the like of the formatter 60, the I / O formatter 61, and the comparator logic circuit 62. Therefore, the test signal P2 output from the formatter 60 to the pin electronics 56 and the I / O formatter 61
The output timing of the switching signal P6 output to the input / output switching means 58 is also controlled according to the high-speed clock from the timing generation means 53. The pattern generator 54 receives the pattern data from the controller 51 and outputs pattern data based on the pattern data to the data selector 59 of the pin controller 55.

The pin control means 55 includes a data selector 59,
It comprises a formatter 60, an I / O formatter 61 and a comparator logic circuit 62. The data selector 59 is composed of a memory storing various test signal creation data (address data / write data) P1, switching signal creation data P5 and expected value data P4, and stores the pattern data from the pattern generation means 54. Input as an address, and test signal creation data P corresponding to the address.
1 and the switching signal creation data P5 are output to the formatter 60 and the I / O formatter 61, and the expected value data P4 is output to the comparator logic circuit 62.

The formatter 60 has a multi-stage configuration of flip-flop circuits and logic circuits. The formatter 60 processes test signal creation data (address data / write data) P1 from the data selector 59 to create a predetermined applied waveform. And uses it as a test signal P2 in the timing generation means 53.
The signal is output to the driver 63 of the pin electronics 56 in synchronization with the timing signal (the rate signal RATE or the edge signal EDGE). Like the formatter 60, the I / O formatter 61 has a multi-stage configuration of flip-flop circuits and logic circuits.
The switching signal generation data P5 is processed to generate a predetermined application waveform, and the waveform is output to the input / output switching unit 58 as a switching signal P6 in synchronization with the timing signal from the timing generation unit 53.

The comparator logic circuit 62 includes read data P3 from the comparator 64 of the pin electronics 56 and expected value data P4 from the data selector 59.
And outputs the result of the determination to the fail memory 57 as fail data FD. The pin electronics 56 includes a plurality of drivers 63 and comparators 64.
Consists of One driver 63 and one comparator 64 are provided for each input / output terminal of the IC mounting device 70, and one of them is connected via the input / output switching means 58. The input / output switching means 58 is provided with a switching signal P5 from the I / O formatter 61.
The connection state between one of the driver 63 and the comparator 64 and the input / output terminal of the IC mounting device 70 is switched in accordance with. That is, the IC mounting device 7
When the number of input / output terminals of 0 is m, the number of drivers 63, comparators 64, and input / output switching means 58 is m. However, when measuring a memory IC, etc.,
Since a comparator is not required for an address terminal, a chip select terminal, or the like, the number of comparators and input / output switching means may be small.

The driver 63 is connected to input / output terminals of the IC mounting device 70, that is, signal input terminals such as an address terminal, a data input terminal, a chip select terminal, and a write enable terminal of the IC 71 to be measured via the input / output switching means 58. ,
The test signal P from the formatter 60 of the pin control means 55
A signal of high level “1” or low level “0” corresponding to 2 is applied, and a desired test pattern is written to the IC under test 71. The comparator 64 inputs a signal output from the data output terminal of the IC 71 to be measured via the input / output switching means 58, compares it with the reference voltages VOH, VOL at the timing of the strobe signal from the control means 51, and The comparison result is output to the comparator logic circuit 62 as read data P3 of high level “1” or low level “0”.

The fail memory 57 stores the fail data FD output from the comparator logic circuit 62, and is constituted by a RAM which has the same storage capacity as the IC 71 to be measured and which can be read and written as needed. The fail memory 57 has a data input / output terminal fixedly corresponding to the data output terminal of the IC mounting device 70. For example, if the total number of input / output terminals of the IC mounting device 70 is 280, and 160 of them are data output terminals, the fail memory 57 stores data of the same number or more than this number of data output terminals. It is composed of a memory having an input terminal. The fail data FD stored in the fail memory 57 is read out by the control means 51, transferred to a data processing memory (not shown), and analyzed. The function test is performed in this manner.

[0015]

SUMMARY OF THE INVENTION As described above, the conventional I
The C test apparatus is configured so that inspection can be performed at twice the maximum operation speed. FIG. 3 shows a part of the configuration of an IC test apparatus capable of double speed inspection, that is, a pin control unit 55.
3 is a diagram showing a connection relationship among a formatter 60, an I / O formatter 61 and a comparator logic circuit 62, a driver 63 and a comparator 64 in a pin electronics 56, and an input / output switching means 58. FIG.

In the figure, for simplicity, a case will be described in which the number of ICs 71 to be measured that can be simultaneously inspected at a normal operation speed is eight. At the time of inspection at a normal operation speed, the formatter FM1 processes the test signal creation data (address data / write data) P1A from the data selector 59 to create a predetermined applied waveform, and converts it into a test signal P2A.
And outputs in synchronization with a timing signal (rate signal RATE or edge signal EDGE) from the timing generation means 53. The formatter MF2 processes the test signal creation data (address data / write data) P1B from the data selector 59 to create a predetermined applied waveform, and uses it as a test signal P2B as a timing signal (rate) from the timing generator 53. The signal is output in synchronization with the signal RATE or the edge signal EDGE. In the inspection of the double speed operation, the test signals P2A and P2B separately processed by the formatters FM1 and FM2 are ORed and output as the double speed test signal DP2. The I / O formatters I / OFM1 and I / OFM2 operate similarly.

Therefore, at the time of inspection at a normal operation speed, the formatter FM1 has four drivers D1 and D4.
, D5, and D7, and outputs a test signal P2A. The formatter FM2 outputs the other four drivers D2, D4, and D7.
6 and D8, the test signal P2B is output via the driver-side selector DSL1. Similarly, the I / O formatter I / OFM1 has four input / output switching means CH1, CH
3, a switching signal P6A is output to CH5 and CH7,
The I / O formatter I / OFM2 outputs a switching signal P6B to the other four input / output switching means CH2, CH4, CH6, and CH8 via the driver-side selector DSL2. As a result, the drivers D1 to D8 output the test signal P
A signal of high level “1” or low level “0” corresponding to 2A and P2B is applied to each pin of the eight ICs 71 to be measured, and desired test patterns are simultaneously written to the eight ICs 71 to be measured.

The comparators C1 to C8 are connected to the input / output switching means CH from the data output terminals of the eight ICs 71 to be measured.
1 to CH8, and compares them with the reference voltages VOH and VOL at the timing of the strobe signal from the control means 51, and compares the comparison result with a high level "1" or a low level "0". Read data P31 to P3
8 as comparator-side selectors CSL1 to CSL8
To the corresponding comparator logic circuits CL1 to CL8. The comparator logic circuits CL1 to CL8 include a comparator-side selector CSL1.
To read data P31 to P3 input through.
8 and the expected value data P41 to P41 from the data selector 59.
P48 is compared and determined, and the determination result is output to the fail memory 57 as fail data FD. When eight ICs 71 to be measured are inspected simultaneously, the expected value data P41 to P48 are the same. In this manner, the conventional IC test apparatus can simultaneously perform a series of function tests on eight ICs to be measured.

On the other hand, during the inspection by the double speed operation,
The formatters FM1 and FM2 have four drivers D1,
The double-speed test signal DP2 is output to D3, D5, and D7, and the double-speed test signal D2 is output to the other four drivers D2, D4, D6, and D8 via the driver-side selector DSL1.
P2 is output. Similarly, I / O formatter I / OF
M1 and I / OFM2 are four input / output switching means CH1,
A double speed switching signal DP6 is output to CH3, CH5, and CH7, and the other four input / output switching means CH2, CH4, and C7 are output.
A double speed switching signal DP6 is output to H6 and CH8 via the driver-side selector DSL2. Double speed test signal DP
2 are drivers D1 to D1 at different timings in one cycle.
D8, the double-speed signal of high level "1" or low level "0" according to the double-speed test signal DP2 is applied to each pin of the eight ICs 71 to be measured. The test is performed at twice the operation speed, that is, at a double speed operation.

However, the comparator logic circuit CL
Since only one comparator 1 to CL8 exists for each of the comparators C1 to C8, about half of all the comparators are in the non-operating state at the time of the inspection by the double speed operation. This is because, when the comparison result of the comparator C1 is taken into the comparator logic circuits CL1 and CL2 via the comparator-side selectors CSL1 and CSL2, there is no comparator logic circuit that takes in the comparison result of the comparator C2. The same can be said for the comparators C3 to C8. Therefore, the comparator C
The comparators C2, C4, C6, and C8 are in a non-operating state while 1, C3, C5, and C7 are operating at double speed.
Conversely, while the comparators C2, C4, C6 and C8 are operating at double speed, the comparators C1, C3, C5 and C7
Becomes inactive. In other words, the conventional IC test apparatus has a drawback in that at the time of inspection by the double speed operation, it is possible to simultaneously inspect only about half of the number of ICs to be measured that can be simultaneously inspected by the normal operation. Inspection had to be performed with a reduced number of measurements.

The present invention has been made in view of the above-mentioned points, and is capable of performing the same inspection without reducing the number of measurable items in the normal operation and the double speed operation.
It is intended to provide a C test apparatus.

[0022]

SUMMARY OF THE INVENTION An IC testing apparatus according to the present invention is an IC testing apparatus for simultaneously inspecting electrical characteristics of a plurality of ICs to be measured.
In the C test apparatus, the specified address of the IC to be measured is
Test signal generating means for generating a test signal such as write data to be written to the specified address and expected value data to be read from the specified address; and a signal based on the specified address and the write data. A plurality of driver means for applying to each terminal of the plurality of ICs to be measured and writing a predetermined test pattern based on the applied data to each of the plurality of ICs to be measured; and a plurality of driver means for each of the plurality of ICs to be measured based on the designated address. Reading a test pattern written in the plurality of ICs to be measured by comparing a signal output from a terminal with a predetermined reference voltage;
A plurality of comparing means for outputting the read data as read data; a dividing means for dividing the read data output from the plurality of comparing means into at least two series; and at least two for one of the comparing means A plurality of determining means for determining whether or not the two sets of read data divided by the dividing means match the expected value data, and outputting a result of the determination; and Inspection means for simultaneously inspecting the electrical characteristics of the plurality of ICs to be measured based on the determination result from the means. Since at least two judging means are provided for one of the comparing means, there is no comparator which becomes inactive even at the time of inspection by the double speed operation.
The number of ICs to be measured that can be measured in the normal operation and the double-speed operation can be the same.

[0023]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a part of the configuration of an IC test apparatus according to the present invention, and corresponds to the prior art in FIG. In the figure, for the sake of simplicity, a case will be described in which the number of ICs 71 to be measured that can be simultaneously tested at a normal operation speed is eight. In FIG. 1, the same components as those in FIG. 3 are denoted by the same reference numerals, and the description thereof will be omitted.

The IC test apparatus according to the present invention differs from the conventional IC test apparatus shown in FIG. 3 in that two comparator logic circuits are provided for each comparator via a selector. That is, the comparator-side selector C is provided for the two comparators C1 and C2.
Four comparator logic circuits CL1A, CL1 are provided via SL1A, CSL1B, CSL2A, CSL2B.
B, CL2A and CL2B are provided. Similarly, 2
Comparator-side selectors CSL3A, CSL3B, CSL4A, CSL for the comparators C3 and C4
4B, four comparator logic circuits CL3
A, CL3B, CL4A, CL4B are provided.
Although this embodiment shows a case where the inspection can be performed at an operation speed up to 4 times the operation speed, if only the inspection is performed at an operation speed of twice the operation speed, the selector is omitted and one inspection is performed. It is sufficient that two comparator logic circuits CL1A and CL1B are provided for the comparator C1, and two comparator logic circuits CL2A and CL2B are provided for one comparator C2.

Comparator logic circuits CL1A, CL
1B, CL2A, CL2B are read data P31 or P32 input via comparator-side selectors CSL1A, CSL1B, CSL2A, CSL2B, and expected value data P41A, P41B,
P42A and P42B are compared and determined, and the determination result is output to the fail memory 57 as fail data FD. Comparator logic circuits CL3A, CL3B, C
L4A and CL4B are comparator-side selectors CSL3
A, read data P33 or P34 input via CSL3B, CSL4A, CSL4B, and expected value data P43A, P43B, P44 from data selector 59.
A and P44B are compared and determined, and the determination result is output to the fail memory 57 as fail data FD. Note that the configurations of the comparators C5 to C8 and the comparator-side selectors and comparator logic circuits respectively provided corresponding to the comparators C1 to C8 are described below.
The illustration is omitted because it is the same as the case of FIG.

Next, eight ICs to be measured at normal operating speed
A case in which the inspection is performed on 71 will be described. At the time of inspection at a normal operation speed, the formatter FM1
Outputs the test signal P2A directly to the four drivers D1, D3, D5 and D7, and the formatter FM2 outputs
The test signal P2B is output to the drivers D2, D4, D6, and D8 via the driver-side selector DSL1. Similarly, the I / O formatter I / OFM1 outputs a switching signal P6A directly to the four input / output switching means CH1, CH3, CH5, CH7, and outputs the I / O formatter I / O.
/ OFM2 is the other four input / output switching means CH2, CH
Driver selector DS for CH4, CH6 and CH8
The switching signal P6B is output via L2. As a result, the drivers D1 to D8 apply a high-level "1" or low-level "0" signal corresponding to the test signals P2A and P2B to each pin of the eight ICs 71 to be measured, and generate eight desired test patterns. Can be written simultaneously to the ICs 71 to be measured.

The comparators C1 to C8 are connected to the input / output switching means CH from the data output terminals of the eight ICs 71 to be measured.
1 to CH8, and compares them with the reference voltages VOH and VOL at the timing of the strobe signal from the control means 51, and compares the comparison result with a high level "1" or a low level "0". Read data P31 to P3
8 as comparator-side selectors CSL1A to CSL
8B, the corresponding comparator logic circuits CL1A to CL8B are output.

For example, the comparator-side selector CSL1
A selects the comparator C1 and the comparator-side selector CS
L2A is the comparator C2, the comparator-side selector CSL3A is the comparator C3, the comparator-side selector CSL4A is the comparator C4, the comparator-side selector CSL5A is the comparator C5, the comparator-side selector CSL6A is the comparator C6, and the comparator-side selector CSL7A is the comparator C7. , The comparator-side selector CSL8A is the comparator C8
, Respectively. The remaining comparators CSL1B to CSL8B are optional to select which comparator.

At this time, the comparator logic circuit CL
1A, CL2A, CL3A, CL4A, CL5A, CL
6A, CL7A, CL8A are the comparator-side selectors CSL1A, CSL2A, CSL3A, CSL4A, C
Read data P31 to P38 input via SL5A, CSL6A, CSL7A, CSL8A and expected value data P41A, P42A, P4 from data selector 59
3A, P44A, P45A, P46A, P47A, P4
8A, and compares the result of the determination with the failure data F
D is output to the fail memory 57. Since eight ICs 71 to be measured are inspected simultaneously, the expected value data P41A, P42A, P43A, P44A, P45
A, P46A, P47A, and P48A are the same data. In this way, the IC test apparatus according to the present invention performs a series of function tests on eight ICs to be measured simultaneously at a normal operation speed.

Next, the inspection by the double speed operation will be described. During the double-speed operation inspection, the formatters FM1 and FM1
2 outputs a double-speed test signal DP2 to the four drivers D1, D3, D5, and D7, and outputs the other four drivers D2.
Driver side selector DSL1 for D4, D6 and D8
Output the double speed test signal DP2 via the. Similarly, I /
The O formatters I / OFM1 and I / OFM2 output the double speed switching signal DP6 to the four input / output switching means CH1, CH3, CH5, CH7, and the other four input / output switching means CH2, CH4, CH6, A double speed switching signal DP6 is output to CH8 via the driver-side selector DSL2. At this time, the double speed test signal DP2 is applied to the drivers D1 to D8 at different timings within one cycle.
Therefore, the high level “1” corresponding to the double speed test signal DP2
Or 8 ICs to be measured with a low-speed "0" double speed signal
The desired test pattern is applied to each pin of the test IC 71 at twice the normal operation speed.
Are simultaneously written and read at twice the speed.

At this time, the comparator logic circuit
Since two comparators are provided for each of the comparators C1 to C8, all the comparators can operate even at the time of the inspection by the double speed operation. This is because the comparison result of the comparator C1 is compared with the comparator-side selectors CSL1A and CSL1.
2A, comparator logic circuits CL1A and CL1C
The comparison result of the comparator C2 is taken into the comparator logic circuits CL1B and CL2B via the comparator-side selectors CSL1B and CSL2B. Similarly, the comparison results of the comparators C3 to C8 are also taken into the respective comparator logic circuits via the respective comparator-side selectors. Therefore, according to this embodiment, all the comparators C1 to C are in the operating state even in the double-speed operation, and the measured I
The same number of ICs 71 to be measured as in the normal operation mode can be inspected without reducing the number of C71 by half.

In the above-described embodiment, the case of operating at double speed has been described. However, when operating at triple speed and quadruple speed, the comparator-side selector CSL1 is appropriately selected.
This can be dealt with by changing the selection state of A to CSL 8B. However, it is needless to say that the maximum measurement number is reduced by operating at such triple speed and quadruple speed. However, in this case, three or more comparator logics may be provided for one comparator.

[0033]

According to the present invention, the same inspection can be performed without reducing the number of measurable items in the normal operation and the double speed operation.

[Brief description of the drawings]

FIG. 1 is a diagram showing a part of the configuration of an IC test apparatus according to the present invention.

FIG. 2 is a block diagram showing an entire configuration of a conventional IC test apparatus.

FIG. 3 is a diagram showing a part of the configuration of a conventional IC test apparatus capable of performing a double speed inspection.

[Explanation of symbols]

50 tester section, 51 control means, 52 DC measurement means, 53 timing generation means, 54 pattern generation means, 55 pin control means, 56 pin electronics, 57 fail memory, 58 input / output switching means , 5
9 Data selector, 60, FM1, FM2 ... Formatter, 61, I / OFM1, I / OFM2 ... I / O formatter, 62, CL1A to CL4B ... Comparator logic circuit, 63, D1 to D8 ... Driver, 64, C1
To C4: comparator, 65: bus, 70: IC mounting device, 71: IC to be measured, DSL1, DSL2: driver side selector, CSL1 to CSL4, CSL1A to CSL
4B ... Comparator-side selector

Claims (2)

(57) [Claims] 1. An IC test apparatus for simultaneously inspecting electrical characteristics of a plurality of ICs to be measured, wherein the specified addresses of the ICs to be measured, write data to be written to the specified addresses, and read data from the specified addresses. Test signal generating means for generating a test signal such as expected value data for a solder; applying a signal based on the specified address and the write data to each terminal of the plurality of ICs to be measured; A plurality of driver means for writing the plurality of ICs to each of the plurality of ICs to be measured, and comparing the signals output from the respective terminals of the plurality of ICs to be measured with a predetermined reference voltage based on the designated address. A plurality of comparing means for reading a test pattern written in the IC under test and outputting the read test data as read data; A dividing means for dividing the read data output from the comparing means into at least two sequences, and at least two dividing means provided for one of the comparing means, wherein the two series divided by the dividing means are provided. A plurality of determining means for determining whether the read data matches the expected value data and outputting the determination result; and the plurality of ICs to be measured based on the determination results from the plurality of determining means. And an inspection means for simultaneously inspecting electrical characteristics of the IC. 2. The method according to claim 1, wherein the dividing means divides the read data output from the plurality of comparing means into four series, respectively, wherein four are provided for two of the comparing means. Selecting means for selectively outputting the four series of read data divided by the dividing means; and determining whether or not the read data selected by the selecting means matches the expected value data. 2. The IC test apparatus according to claim 1, wherein the determination is made and a result of the determination is output.