JP3080296B2 - IC test equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an integrated circuit (IC).
More particularly, the present invention relates to an IC test apparatus having improved pattern generation means for generating pattern data serving as a reference of a test signal applied to an IC to be measured.

[0002]

2. Description of the Related Art In order to ship an IC whose performance and quality are guaranteed as a final product, it is necessary to extract all or a part of the IC product in each process of a manufacturing department and an inspection department and to inspect its electrical characteristics. There is. An IC test device is a device for inspecting such electrical characteristics. The IC test apparatus gives predetermined test pattern data to the IC to be measured, reads data output from the IC to be measured in response thereto, and outputs whether there is no problem in the basic operation and function of the IC to be measured. The analysis is performed based on the data, and the inspection regarding the electrical characteristics is performed.

[0003] DC tests (D
C measurement test) and a function test (FC measurement test). For DC test, D
By applying a predetermined voltage or current from the C measuring means, it is checked whether there is any defect in the basic operation of the IC to be measured. On the other hand, in the function test, predetermined test pattern data is given to the input terminal of the IC under test from the pattern generation means, and the output data of the IC under test is read, and there is no problem in the basic operation and function of the IC under test. It is to check whether or not.

FIG. 3 is a block diagram showing a schematic configuration of a conventional IC test apparatus. The IC test apparatus is roughly divided into a tester section 50 and an IC mounting apparatus 70. The tester unit 50 includes a control unit 51, a DC measurement unit 52, a timing generation unit 5
3. It comprises a pattern generating means 54, a pin control means 55, a pin electronics 56, a fail memory 57 and an input / output switching means 58. In the actual tester section 50,
There are various other components, but only necessary parts are shown in this specification.

The tester unit 50 and the IC mounting device 70 are connected by signal lines including a plurality (m) of coaxial cables or the like corresponding to the total number of input / output terminals (m) of the IC mounting device 70. The connection relationship between the terminal and the coaxial cable is associated with each other by a relay matrix (not shown), so that transmission of various signals is performed between a predetermined terminal and the coaxial cable. Note that there are physically as many signal lines as the number m of all input / output terminals of the IC mounting device 70.

The IC mounting device 70 includes a plurality of ICs to be measured.
71 is configured to be mounted on a socket. The input / output terminal of the IC 71 to be measured and the input / output terminal of the IC mounting device 70 are connected in one-to-one correspondence. For example, if the IC 71 to be measured having 28 input / output terminals is 1
In the case of the IC mounting device 70 capable of mounting zero ICs, a total of 28
It has zero input / output terminals. At present, some of those on the market have 1024 input / output terminals.

The control means 51 controls the entire IC test apparatus,
It performs operations and management, and has a microprocessor configuration. Therefore, although not shown, it has a ROM for storing a system program, a RAM for storing various data, and the like. Further, the control means 51 includes a DC
The measuring means 52, the timing generating means 53, the pattern generating means 54, the pin control means 55, and the fail memory 57 are connected via buses (data bus, address bus, control bus) 65 and respective internal registers. The control means 51 converts the DC test data into the DC measurement data 52
A signal for starting a function test is sent to the timing generator 53, data for generating a test pattern is sent to the pattern generator 54, and expected value data and the like are sent to the pin controller 55.
Respectively. In addition, the control means 51 outputs various data to respective components via a bus. In particular, the control means 51 has internal registers (hereinafter referred to as "pin registers") corresponding to pins for storing data relating to each input / output terminal, the number of which corresponds to the number of input / output terminals, and writes data therein. Thus, data relating to the input / output terminals is transferred to each component. Further, the control unit 51 reads out the test results (fail data and DC data) from the fail memory 57 and the DC measuring unit 52, performs various data processing and the like, analyzes the test data, and determines the quality of the IC.

The DC measuring means 52 receives the DC test data from the control means 51 and performs a DC test on the IC 71 to be measured of the IC mounting device 70 based on the data. DC
The measuring means 52 starts a DC test by inputting a measurement start signal from the control means 51, and writes data indicating the test result into an internal register. When the writing of the test result data is completed, the DC measuring means 52 outputs an end signal to the control means 51. The data indicating the test result written in the internal register of the DC measuring means 52 is read by the control means 51 via the bus 65 and analyzed there. Thus, the DC test is performed. DC measurement means 5
2 are reference voltages VIH, VIL, VO for the driver 63 and the comparator 64 of the pin electronics 56.
H and VOL are output.

The timing generation means 53 outputs a predetermined clock to the pin control means 55,
It controls the operation speed and the like of the formatter 60, the I / O formatter 61, and the comparator logic circuit 62. Therefore, the test signal P2 output from the formatter 60 to the pin electronics 56 and the I / O formatter 61
The output timing of the switching signal P6 output to the input / output switching unit 58 is also controlled according to the high-speed operation clock CLK from the timing generation unit 53. The pattern generation unit 54 receives the pattern data from the control unit 51 and outputs the pattern data based on the pattern data to the pin control unit 55.
Is output to the data selector 59.

The pin control means 55 includes a data selector 59,
It comprises a formatter 60, an I / O formatter 61 and a comparator logic circuit 62. The data selector 59 is composed of a memory storing various test signal creation data (address data / write data) P1, switching signal creation data P5 and expected value data P4, and stores the pattern data from the pattern generation means 54. Input as an address, and test signal creation data P corresponding to the address.
1 and the switching signal creation data P5 are output to the formatter 60 and the I / O formatter 61, and the expected value data P4 is output to the comparator logic circuit 62.

The formatter 60 has a multi-stage configuration of flip-flop circuits and logic circuits. The formatter 60 processes test signal creation data (address data / write data) P1 from the data selector 59 to create a predetermined applied waveform. And uses it as a test signal P2 in the timing generation means 53.
The signal is output to the driver 63 of the pin electronics 56 in synchronization with the timing signal (the rate signal RATE or the edge signal EDGE). Like the formatter 60, the I / O formatter 61 has a multi-stage configuration of flip-flop circuits and logic circuits.
The switching signal generation data P5 is processed to generate a predetermined application waveform, and the waveform is output to the input / output switching unit 58 as a switching signal P6 in synchronization with the timing signal from the timing generation unit 53.

The comparator logic circuit 62 includes read data P3 from the comparator 64 of the pin electronics 56 and expected value data P4 from the data selector 59.
And outputs the result of the determination to the fail memory 57 as fail data FD. The pin electronics 56 includes a plurality of drivers 63 and comparators 64.
Consists of One driver 63 and one comparator 64 are provided for each input / output terminal of the IC mounting device 70, and one of them is connected via the input / output switching means 58. The input / output switching means 58 is provided with a switching signal P5 from the I / O formatter 61.
The connection state between one of the driver 63 and the comparator 64 and the input / output terminal of the IC mounting device 70 is switched in accordance with. That is, the IC mounting device 7
When the number of input / output terminals of 0 is m, the number of drivers 63, comparators 64, and input / output switching means 58 is m. However, when measuring a memory IC, etc.,
Since a comparator is not required for an address terminal, a chip select terminal, or the like, the number of comparators and input / output switching means may be small.

The driver 63 is connected to input / output terminals of the IC mounting device 70, that is, signal input terminals such as an address terminal, a data input terminal, a chip select terminal, and a write enable terminal of the IC 71 to be measured via the input / output switching means 58. ,
The test signal P from the formatter 60 of the pin control means 55
A signal of high level “1” or low level “0” corresponding to 2 is applied, and a desired test pattern is written to the IC under test 71. The comparator 64 inputs a signal output from the data output terminal of the IC 71 to be measured via the input / output switching means 58, compares it with the reference voltages VOH, VOL at the timing of the strobe signal from the control means 51, and The comparison result is output to the comparator logic circuit 62 as read data P3 of high level “1” or low level “0”.

The fail memory 57 stores the fail data FD output from the comparator logic circuit 62, and is constituted by a RAM which has the same storage capacity as the IC 71 to be measured and which can be read and written as needed. The fail memory 57 has a data input / output terminal fixedly corresponding to the data output terminal of the IC mounting device 70. For example, if the total number of input / output terminals of the IC mounting device 70 is 280, and 160 of them are data output terminals, the fail memory 57 stores data of the same number or more than this number of data output terminals. It is composed of a memory having an input terminal. The fail data FD stored in the fail memory 57 is read out by the control means 51, transferred to a data processing memory (not shown), and analyzed. The function test is performed in this manner.

FIG. 4 is a block diagram showing a schematic configuration of the pattern generating means 54 of FIG. Pattern generating means 54
Is composed of a sequence unit 1 and a calculation unit 2. The sequence unit 1 controls the sequence of the test pattern by instructions such as a loop branch condition, a subroutine jump, a flag sense, an advance, and a hold stored in the sequence instruction memory 12, and an address of the instruction memory 21 of the arithmetic unit 2. Is output. The operation unit 2 outputs pattern data in accordance with an operation instruction stored in the instruction memory 21. Both the sequence unit 1 and the arithmetic unit 2 operate according to the high-speed operation clock CLK from the timing generation unit 53.

The sequence section 1 has a program counter 1
1. It comprises a sequence instruction memory 12 and a decoder 13. The program counter 12 counts the operation clock CLK. The sequence instruction memory 12 stores sequence instructions such as a loop branch condition, a subroutine jump, a flag sense, an advance, and a hold. The count value of the program counter 11 is input as an address, and the sequence instruction stored at the address is stored. Output to the decoder 13. The decoder 13 decodes this sequence command, outputs it to the program counter 11, and controls the counting operation of the program counter 11.

The operation unit 2 includes an instruction memory 2
1, a flip-flop circuit 22 and an arithmetic logic unit (ALU) 23. Instruction memory 2
Numeral 1 stores an operation instruction (addition instruction, subtraction instruction, etc.) of the arithmetic logic unit 23, inputs a count value from the program counter 11 of the sequence unit 1 as an address, and executes the operation instruction stored at that address. Flip-flop circuit (F / F) in synchronization with operation clock CLK
22. The flip-flop circuit 22 temporarily stores the operation instruction output from the instruction memory 21 and supplies the operation instruction to the operation logic unit 23. The arithmetic logic unit 23 performs arithmetic processing according to an arithmetic instruction from the flip-flop circuit 22. As a result, the arithmetic logic unit 23 outputs the pattern data PD that changes sequentially according to the arithmetic instruction.

[0018]

Since the sequence section 1 and the arithmetic section 2 of the conventional pattern generating means 54 operate according to the operating clock CLK from the timing generating means 53, the operating clock CLK can be shifted at a high speed. The more the operation speed, the higher the operation speed of the pattern generating means 54.

However, the operation of the sequence section 1 is to access the sequence instruction memory 12 in accordance with the address output from the program counter 11 and to control the count operation of the program counter 11 again in accordance with the accessed sequence instruction. , The operation speed of the sequence unit 1 is limited by the access speed of the sequence instruction memory 12. Therefore, there is a problem that the entire pattern generating means 54 cannot be operated at a speed higher than the operating speed limit of the sequence unit due to the limitation by the access speed of the memory.

The present invention has been made in view of the above points, and provides an IC test apparatus provided with a pattern generating means capable of generating pattern data at a speed higher than the operating speed limit of the sequence section at a high speed. The purpose is to do.

[0021]

According to the present invention, there is provided an IC test apparatus comprising: a frequency dividing means for dividing an operation clock; and operating based on the frequency divided clock divided by the frequency dividing means. Is read by a program counter, a sequence instruction is read from a sequence instruction memory using the count value as an address, and a feedback type sequence means for controlling the program counter by the read sequence instruction is used. A bit generating means for outputting the bit data of the instruction memory, operating based on the operation clock, synthesizing a count value from the program counter and bit data from the bit generating means, and using the synthesized data as an address as an instruction memory Read the operation instruction from the Controls arithmetic logic unit in response to the operation instruction, and has a pattern generating means comprising an arithmetic unit for outputting a predetermined pattern data.

As described above, since the sequence means operates in a feedback manner, it is limited by the access speed of the sequence instruction memory. On the other hand, since the operation means only reads the instruction memory by the address output from the program counter and operates the operation logic unit by the read operation instruction, by adopting an interleave method or the like as the instruction memory read method, It is possible to increase the reading speed without being limited by the access speed of the instruction memory, thereby increasing the operating speed of the entire arithmetic unit.

Therefore, in the present invention, frequency dividing means for dividing the operating clock is provided, the sequence means is operated based on the divided clock, and the calculating means is operated directly based on the operating clock. At this time,
Since the program counter of the sequence means counts the frequency-divided clock, the count value cannot be used as it is as the address of the instruction memory of the arithmetic means. Therefore, in the present invention, a bit generation means for counting an operation clock and outputting predetermined bit data is provided, and by combining the bit data from the bit generation means with the count value of the program counter, the count value of the program counter is obtained. Was synchronized with the operation clock. Thereby, the sequence means operates with the divided clock, and the arithmetic means can operate with the operation clock higher than the operation speed of the sequence means without being restricted by the access speed of the instruction memory. Pattern data can be generated at high speed.

[0024]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. FIG.
FIG. 5 is a diagram illustrating a detailed configuration of a pattern generation unit according to an embodiment of the C test apparatus, and corresponds to FIG. 4. In FIG. 1, the same components as those in FIG. 4 are denoted by the same reference numerals. The pattern generating means according to the present invention is different from the conventional one in that a 発 生 frequency divider 3 for dividing the operation clock CLKH by half, and a least significant bit of an address output from the program counter 11 are provided. The difference is that a least significant bit generator 4 for generating a desired bit is newly provided.

In FIG. 1, the operation clock CLKH is about twice as fast as the operation clock CLK of FIG. For example, assuming that the frequency of the operation clock CLK at which the sequence unit 1 can operate is 60 MHz (16 nS).
The operating clock CLKH of FIG. 1 is twice the frequency of 120 MHz.
z (8 nS). Accordingly, although the sequence unit 1 can operate under the operation clock CLK, the sequence unit 1 operates under the operation clock CL.
It cannot operate under KH. Therefore, in the present invention, a 分 frequency divider 3 for dividing the frequency of the operation clock CLKH by 設 け is provided in the preceding stage of the sequence unit 1, and the frequency division operation divided by the frequency divider 3 is performed. The clock CLKD is supplied to the sequence unit 1. Therefore, even if the operation clock CLKH becomes about twice as fast, the sequence unit 1 operates in the same manner as in the prior art.
It will work under LK. Further, in the present invention,
A least significant bit generator 4 for outputting a bit signal A0 in synchronization with the operation clock CLKH is provided.
Is the address AD output from the program counter 11.
P is synthesized to be the least significant bit of P
AD of the interleave memories 21a and 21b
Output as Q. That is, the least significant bit generator 4 is a 1-bit counter that counts the operation clock CLKH, and the bit signal A0 of “0” or “1”
Are output alternately.

The sequence section 1 has a program counter 1
1. It comprises a sequence instruction memory 12 and a decoder 13. The program counter 11 counts the frequency-divided operation clock CLKD frequency-divided by the 、 frequency divider 3 and outputs the count value to the sequence instruction memory 12 and the arithmetic unit 2 as an address ADP. The sequence instruction memory 12 stores sequence instructions such as a loop branch condition, a subroutine jump, a flag sense, an advance, and a hold. The count value of the program counter 11 is input as an address ADP, and the sequence stored in the address ADP is stored. An instruction is output to the decoder 13. The decoder 13 decodes this sequence instruction,
This is output to the program counter 11 and the counting operation of the program counter 11 is controlled.

The operation unit 2 includes instruction memories 21a and 21b read out by an interleave method,
It comprises flip-flop circuits 22a and 22b, a multiplexer 24 and an arithmetic logic unit (ALU) 23. The instruction memories 21a and 21b store operation instructions (addition instruction, subtraction instruction, etc.) of the arithmetic logic unit 23, and store the address ADP from the program counter 11 of the sequence unit 1 and the bit signal A0 from the least significant bit generator 4. Are input in parallel, and the operation instruction stored in the address ADQ is output to the flip-flop circuits (F / F) 22a and 22b. The flip-flop circuits 22a and 22b temporarily store operation instructions output from the instruction memories 21a and 21b.

The multiplexer 24 operates with an operation clock CLK.
The operation command stored in the flip-flop circuit 22a or 22b is alternately switched and supplied to the operation logic unit 23 in synchronization with H. The arithmetic logic unit 23 receives an arithmetic instruction from the flip-flop circuit 22a or 22b alternately switched by the multiplexer 24,
The arithmetic processing corresponding thereto is performed. As a result, the arithmetic logic unit 23 can output the pattern data PD that changes sequentially according to the arithmetic command at a speed corresponding to the operation clock CLKH.

Next, the operation of the pattern generating means of FIG. 1 will be described with reference to the timing chart of FIG. The timing generation means 53 outputs the operation clock CLKH as shown in FIG.
１ ／ frequency divider 3, least significant bit generator 4 and arithmetic unit 3
Output to The first clock CLK1 and the second clock CLK are generated according to the generation timing of the operation clock CLKH.
2, third clock CLK3, fourth clock CLK4,.
・

The 1/2 frequency divider 3 generates the operation clock CLK
H is halved, and the divided operating clock C
The LKD is output to the sequence unit 1. That is, the divided operation clock CLKD is the second clock CLK2, the fourth clock CLK4, and the sixth clock C of the operation clock CLKH.
LK6,... Are generated. The sequence unit 1 operates with the frequency division operation clock CLKD, and the program counter 11 counts (addresses AD) synchronized with the frequency division operation clock CLKD.
P) is output.

At this time, the least significant bit generator 4 outputs a bit signal A0 of "0" or "1" synchronized with the operation clock CLKH. Therefore, the program counter 1 is stored in the instruction memories 21a and 21b of the arithmetic unit 2.
The address ADP from 1 and the bit signal A0 are combined to read the address ADQ in an interleaved manner.

That is, the instruction memory 21
The address ADQa is input to the address terminal a at a timing synchronized with the first clock CLK1, the third clock CLK3, the fifth clock CLK5,. On the other hand, the address terminal of the instruction memory 21b is
Address A at a timing synchronized with clock CLK2, fourth clock CLK4, sixth clock CLK6,.
DQb is input.

The instruction memories 21a and 21b to which the addresses ADQa and ADQb have been input output the operation instructions MPa and MPb stored at the addresses at different timings after the lapse of the access time, so that the flip-flop circuits 22a and 22b The operation instructions MPa and MPb are fetched at respective timings and temporarily stored. Flip-flop circuits 22a and 2
The operation commands MPa and MPb stored in 2b are alternately switched by the multiplexer 24 and output to the operation logic unit 23 at different timings. Here, the arithmetic logic unit 23 inputs the incremental mode (ALU = 1) as the arithmetic instructions MPa and MPb. Therefore, the arithmetic logic unit 23 operates the operation clock CL
The pattern data PD (data to be incremented) is output at high speed in synchronization with KH.

In the above-described embodiment, a case has been described in which the operating clock is divided by one half, but the operating clock may be divided by one fourth or one eighth. In this case, the least significant bit generator is a 2-bit counter, 4
A bit counter may be used. Further, the interleave method has been described as an example of a read method of the instruction memory, but it goes without saying that other methods may be used as long as the memory can be read at high speed.

[0035]

According to the IC testing apparatus of the present invention, there is an effect that pattern data can be generated at a speed higher than the operating speed limit of the sequence section.

[Brief description of the drawings]

FIG. 1 is a diagram showing a detailed configuration of a pattern generation unit as an embodiment of an IC test apparatus according to the present invention.

FIG. 2 is a timing chart for explaining the operation of FIG. 1;

FIG. 3 is a block diagram showing an overall configuration of an IC test apparatus.

FIG. 4 is a diagram showing a schematic configuration of a pattern generating unit of FIG. 3;

[Explanation of symbols]

1 ... Sequence section, 2 ... Operation section, 3 ... 1/2 frequency divider, 4
... Least significant bit generator, 11 ... Program counter, 1
2 ... sequence instruction memory, 13 ... decoder, 21a,
21b, 21 ... instruction memory, 22a, 2
2b, 22 ... flip-flop circuit (F / F), 23 ...
Arithmetic logic unit (ALU), 24 ... Mux (MUX)

Claims (3)

(57) [Claims] A frequency dividing means for dividing an operating clock; operating based on a frequency divided clock divided by the frequency dividing means; counting the frequency divided clock by a program counter; A sequencer of a feedback system that reads a sequence instruction from a sequence instruction memory and controls the program counter by the read sequence instruction; a bit generator that counts the operation clock and outputs predetermined bit data; Operating based on an operation clock, synthesizing a count value from the program counter and bit data from the bit generation means, reading an operation instruction from the instruction memory using the synthesized data as an address, and reading the read operation instruction Logic operation unit And an operation means for outputting predetermined pattern data.
Testing equipment. 2. The frequency dividing means divides the operating clock by half, and the bit generating means comprises a 1-bit counter for counting the operating clock. 2. The IC test apparatus according to claim 1, wherein the value is combined with the count value of the program counter as a bit. 3. The IC test apparatus according to claim 1, wherein said operation means reads out operation instructions from said instruction memory in an interleaved manner.