JP3459036B2 - Data transfer device for IC test equipment - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC (integrated circuit).
The present invention relates to an IC test apparatus for inspecting electrical characteristics of the IC test apparatus, and more particularly to a data transfer apparatus of the IC test apparatus in which a transfer section for adjusting transfer times of a plurality of test pattern data is improved.

[0002]

2. Description of the Related Art In order to ship an IC device whose performance and quality are guaranteed as a final product, all or a part of the IC device is extracted in each process of a manufacturing department and an inspection department, and its electrical characteristics are inspected. There is a need.

The IC test device is a device for inspecting such electrical characteristics. The IC tester gives predetermined test pattern data to the IC to be measured, and the IC to be measured by this
Of the output data of the IC to be measured and whether the basic operation and function of the IC to be measured have no problem is analyzed from the output data of the IC to be measured to inspect the electrical characteristics.

The test in the IC test equipment is a direct current test (D
It is roughly divided into a C measurement test) and a function test (FC measurement test). For the DC test, use the D
By applying a predetermined voltage or current from the C measuring means, it is inspected whether the basic operation of the IC to be measured is defective. On the other hand, in the function test, given pattern data for test from the pattern generating means to the input terminal of the IC to be measured, the output data of the IC to be measured is read, and there is no problem in the basic operation and function of the IC to be measured. It is something to inspect. That is, in the function test, the input timing of each input signal of the IC to be measured such as address, data, write enable signal, chip select signal, input conditions such as amplitude, etc. are changed, and the output timing and output amplitude are tested. It is something to do.

FIG. 3 is a block diagram showing a schematic configuration of a conventional IC test apparatus. The IC test device is roughly divided into a tester unit 50 and an IC mounting device 70. Tester part 5
0 is a control means 51, a DC measurement means 52, a timing generation means 53, a pattern generation means 54, a pin control means 55,
It is composed of a pin electronics 56, a fail memory 57 and an input / output switching means 58. Although the tester unit 50 has various other components, only the necessary parts are shown in the present specification.

The tester section 50 and the IC mounting device 70 are connected by a signal line composed of a plurality (m) of coaxial cables corresponding to the total number of input / output terminals (m) of the IC mounting device 70. The connection relationship between the terminals and the coaxial cable is associated with each other by a relay matrix (not shown), and various signals are transmitted between the predetermined terminals and the coaxial cable. The number of signal lines is physically the same as the total number m of input / output terminals of the IC mounting apparatus 70. The IC attachment device 70 is configured so that a plurality of ICs to be measured 71 can be mounted in a socket. The input / output terminals of the IC to be measured 71 and the input / output terminals of the IC attachment device 70 are connected in one-to-one correspondence with each other. For example, in the case of the IC attachment device 70 capable of mounting 10 ICs under test 71 having 28 input / output terminals, the total number of input / output terminals is 280.

The control means 51 controls the entire IC test apparatus,
It is used for operation and management, and has a microprocessor configuration. Therefore, although not shown, the control means 51 has a ROM for storing a system program, a RAM for storing various data, and the like. The control means 51
DC measuring means 52, timing generating means 53, pattern generating means 54, pin control means 55 and fail memory 5
7 via a tester bus (data bus, address bus, control bus) 69. The control means 51 expects the DC test data to be the DC measurement means 52, the function test start timing data to be the timing generation means 53, and the program and various data necessary for the test pattern generation to be the pattern generation means 54. The value data and the like are output to the pin control means 55. In addition to this, the control means 51 outputs various data to the respective constituent parts via the tester bus 69. Also, the control means 51
Is an internal register in the DC measuring means 52, a fail memory 57 and a pass / fail (PA in the pin control means 55).
Data indicating the test result (DC data or pass / fail data PFD) is read from the SS / FAIL register 63P and analyzed to determine whether the IC 71 under test is good or bad.

The DC measuring means 52 receives the DC test data from the control means 51 and performs a DC test on the IC 71 to be measured of the IC mounting apparatus 70 based on the DC test data. DC
The measuring means 52 starts the DC test by inputting the measurement start signal from the control means 51, and writes the data showing the test result in the internal register. When the DC measurement means 52 finishes writing the test result data, it outputs an end signal to the control means 51. The data written in the internal register is read by the control means 51 via the tester bus 69 and analyzed there. In this way, the DC test is performed. Further, the DC measuring means 52 supplies the reference voltages VIH, VIL, VOH, and VOL to the driver 64 of the pin electronics 56 and the analog comparator 65.

The timing generating means 53 is a control means 51.
The timing data from the memory is stored in the internal memory, and the high-speed operation clock CLK is output to the pattern generation means 54, the pin control means 55 and the fail memory 57 based on the timing data PH and the timing signal PH for writing and reading data.
Is output to the pin control means 55 and the fail memory 57.
Therefore, the operation speeds of the pattern generation means 54 and the pin control means 55 are determined by this high speed operation clock CLK, and the timing of data writing and reading to / from the IC 71 to be measured is determined by this timing signal PH. The timing signal PH also determines the write timing of the pass / fail data PFD to the fail memory 57.

Therefore, the test signal P2 and I / O output from the formatter 60 to the pin electronics 56.
The output timing of the switching signal P6 output from the formatter 61 to the input / output switching means 58 is also the timing generating means 5.
High-speed operation clock CLK and timing signal P from 3
It is controlled according to H. Also, the timing generating means 53
Receives a timing switching control signal CH from the pattern generating means 54, and switches the operation cycle, phase, etc. as appropriate based on the input.

The pattern generating means 54 inputs the data (microprogram or pattern data) for pattern generation from the control means 51 and outputs the pattern data PD based on the data to the data selector 59 of the pin control means 55. That is, the pattern generating means 54 uses a program method that outputs regular test pattern data by various arithmetic processing according to the microprogram method, and an internal memory (referred to as a pattern memory) that has the same data as the data written in the IC to be measured. Is written in advance and is read at the same address as the IC to be measured, so that irregular (random) pattern data (expected value data)
It operates by the memory stored method that outputs. In the program method, the IC to be measured is RAM (Random Acces)
Corresponding to the test of volatile memory such as s Memory),
Memory stored method is ROM (Read Only M)
It corresponds to the test of a non-volatile memory such as memory. Even in the case of the memory stored method, the address supplied to the IC to be measured is generated by the program method.

The pin control means 55 is a data selector 59,
Formatter 60, I / O formatter 61, comparator logic circuit 62 and pass / fail (PASS /
FAIL) register 63P. The data selector 59 is composed of a memory that stores various test signal creation data (address data / write data) P1, switching signal creation data P5, and expected value data P4. The pattern data from the pattern generation means 54 is stored in the data selector 59. The test signal creation data P1 and the switching signal creation data P5 corresponding to the address are input to the formatter 60 and the I / O formatter 61, and the expected value data P4 is output to the comparator logic circuit 62. The formatter 60 is composed of flip-flop circuits and logic circuits in multiple stages, and has test signal generation data (address data / write data) P1 from the data selector 59.
Is processed to create a predetermined applied waveform, which is used as the test signal P
2 as pin electronics 56 at the timing synchronized with the timing signal PH from the timing generation means 53.
Output to the driver 64. Like the formatter 60, the I / O formatter 61 also has a multi-stage structure of flip-flop circuits and logic circuits.
The switching signal creation data P5 from 9 is processed to create a predetermined applied waveform, which is output to the input / output switching means 58 as a switching signal P6 at a timing synchronized with the timing signal PH from the timing generating means 53.

The comparator logic circuit 62 compares and judges the digital read data P3 from the analog comparator 65 of the pin electronics 56 and the expected value data P4 from the data selector 59, and the pass / fail data PFD indicating the judgment result. Is output to the pass / fail register 63P and the fail memory 57. The pass / fail register 63P is set to fail (FA) by the comparator logic circuit 62 in the function test.
IL) is a register for storing whether or not it is determined, and is configured by the number of bits corresponding to the number of ICs under test 71 that can be mounted on the IC attachment device 70. That is, when up to 32 ICs to be measured 71 can be mounted on the IC attachment device 70, the pass / fail register 63P has a 32-bit configuration. When the corresponding bit of the pass / fail register 63P is the high level "1" pass (PASS), the IC 71 under test is determined to be a good product,
In the case of a low level “0” fail, the IC 71 to be measured has some defect and is determined to be a defective product. Therefore, it is necessary to use the fail memory 57 when analyzing the defective portion in detail.

The pin electronics 56 is composed of a plurality of drivers 64 and an analog comparator 65. The driver 64 and the analog comparator 65 are ICs
One is provided for each input / output terminal of the mounting device 70, and either one of them is connected via the input / output switching means 58. Input / output switching means 5
Reference numeral 8 switches the connection state between one of the driver 64 and the analog comparator 65 and the input / output terminal of the IC mounting device 70 in response to the switching signal P6 from the I / O formatter 61. That is, when the number of input / output terminals of the IC mounting device 70 is m, the driver 64,
Each of the analog comparator 65 and the input / output switching means 58 is composed of m pieces. However, when measuring a memory IC or the like, an analog comparator is not required for an address terminal, a chip select terminal, or the like, so the number of analog comparators and input / output switching means may be small.

The driver 64 is connected to the input / output terminals of the IC attachment device 70, that is, the signal input terminals such as the address terminal, the data input terminal, the chip select terminal and the write enable terminal of the IC to be measured 71 through the input / output switching means 58. ,
Test signal P from the formatter 60 of the pin control means 55
A high level “H” or low level “L” signal corresponding to 2 is applied to write a desired test pattern in the IC 71 to be measured. The analog comparator 65 is the IC 7 to be measured.
The signal output from the first data output terminal via the input / output switching unit 58 is input, and the signal is input to the timing generating unit 53.
From the reference voltage VOH, VOL at the timing of the strobe signal (not shown) from the comparator logic circuit 62 as the digital read data P3 of the high level "PASS" or the low level "FAIL".
Output to. Normally, the analog comparator 65 is composed of two comparators for the reference voltage VOH and the reference voltage VOL, but they are omitted in the figure.

The fail memory 57 is a pass / fail data PF output from the comparator logic circuit 62.
D is stored in the address position corresponding to the address signal AD from the pattern generating means at the input timing of the timing signal PH from the timing generating means 53.
The fail memory 57 has a storage capacity similar to that of the IC to be measured 71 and can be read from and written to at any time.
When the IC 71 to be measured is determined to be defective, it is used for detailed analysis of the defective portion or the like. Therefore, the fail memory 57 is not used in the normal simple pass / fail judgment. Further, the fail memory 57 has a data input / output terminal that fixedly corresponds to the data output terminal of the IC attachment device 70. For example, when the total number of input / output terminals of the IC attachment device 70 is 280 and 160 of them are data output terminals, the fail memory 57 has the same or more data as the number of data output terminals. It is composed of a memory having an input terminal. The pass / fail data PFD stored in the fail memory 57 is read out by the control means 51 and transferred to a data processing memory (not shown).
Parsed.

[0017]

In the conventional IC test apparatus, a plurality of test pattern data generated by the pattern generating means are synchronized and are supplied to each device as test pattern data. . However, recently, as the speed of the IC to be measured has increased, the speed of the test pattern data has increased, and the timing adjustment of each test pattern data has to be performed on the order of about 100 MHz.

FIG. 4 is a diagram showing the configuration of a data transfer device for adjusting the time of test pattern data in a conventional IC test device. In the figure, the data transfer device is composed of a plurality of flip-flop circuits (F / F) F0 to Fn connected in series and a selector circuit (SEL) that selectively outputs the outputs of the flip-flop circuits F0 to Fn. Has been done.

The input clock CLK is input to the clock terminals C0 to Cn of the flip-flop circuits F0 to Fn. Input terminal D of each flip-flop circuit F1 to Fn
1 to Dn are the flip-flop circuits F0 to Fn- of the previous stage.
1 output signals FQ0 to FQn-1 are captured. Output signals FQ0 to FQn- delayed by one clock from the output terminals Q0 to Qn of the flip-flop circuits F0 to Fn.
1 is output to the flip-flop circuits F1 to Fn of the next stage and is output to each of the selection input terminals S0 to Sn of the selector circuit 2.

The selector circuit 2 is provided with a stage number selection signal SS for determining which of the output terminals Q0 to Qn of the flip-flop circuits F0 to Fn is to be used as the final output data OuDt. It has been entered.

FIG. 5 is a timing chart showing the state of data output from each of the flip-flop circuits F0 to F2 when the flip-flop circuit has three stages. As is apparent from the figure, when outputting a signal delayed by one clock, the output signal FQ0 of the flip-flop circuit F0
It suffices to output the stage number selection signal SS0 for selecting. When it is desired to output a signal delayed by two clocks or a signal delayed by three clocks, the stage number selection signals SS1, SS2 for selecting the output signals FQ1, FQ2 of the respective flip-flop circuits may be output.

However, if the flip-flop circuits are connected in series and the flip-flop circuits are operated by the high-speed input clock CLK, all the flip-flop circuits operate by the high-speed input clock CLK. Become. That is, in the case of delaying by one clock, although the first flip-flop circuit only needs to be operated, the conventional transfer unit is configured to also operate the other flip-flop circuits on the subsequent stage side. There is. Therefore, wasteful current consumption flows, which causes heat generation, which is a problem.

The present invention has been made in view of the above points, and it is an object of the present invention to provide a data transfer device of an IC test device capable of suppressing current consumption by a high-speed clock and heat generation accompanying it as much as possible.

[0024]

According to another aspect of the present invention, there is provided a data transfer device for an IC test apparatus, comprising a plurality of storage circuit groups for receiving and outputting input data according to a write clock, and the write clock according to the input clock. Write control means for sequentially supplying to the memory circuit group, selector means for outputting each output of the memory circuit group in the same order as the order according to a selection signal, and masking only a predetermined number from the beginning of the input clock. And a read control means for outputting the selection signal to the selector means in accordance with the masked input clock.

Each memory circuit is composed of, for example, a flip-flop circuit, input data is input to its input terminal, the input data is fetched in accordance with a write clock, and the data is output from an output terminal. The write control means is for generating a write clock to be supplied to each flip-flop circuit. The write control means sequentially supplies the write clock to each flip-flop circuit based on the input clock. Therefore, each flip-flop circuit operates so as to sequentially take in and output the input data in accordance with the write clock. The output of each flip-flop circuit is
It is selectively output via the selector means. The selector means outputs the output of each flip-flop circuit as output data in the order according to the selection signal from the read control means, that is, in the same order as the write control means supplies the write clock to the flip-flop circuit. Since the read control means masks a predetermined number of portions from the beginning of the input clock input to the write control means,
Since the operation is delayed by the predetermined number, the output of each flip-flop circuit output from the selector means is delayed by the clock timing corresponding to the predetermined number, and the input data and the output data are output according to the input clock timing. You can adjust the timing of. Moreover, since each flip-flop circuit operates at a lower speed than the high-speed input clock, power consumption and heat generation can be suppressed to a low level. The memory circuit is not limited to a so-called flip-flop circuit, and in short, may be a circuit that takes in input data and outputs it according to a write clock.

The data transfer apparatus according to a second aspect of the invention delays the input data by a timing corresponding to the number of masked clocks and outputs the delayed data as output data. That is, the delay timing can be adjusted by selecting various numbers of clocks to be masked.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 1 is a diagram showing a schematic configuration of a test pattern data transfer unit of an IC test apparatus according to the present invention. This transfer unit includes a predetermined number of flip-flop circuits (F / F) F0 to Fn and a selector circuit (SEL).
2, a write control unit 3, and a read control unit 4.

Each flip-flop circuit F0 to Fn independently takes in the input data InDt to the input terminals D0 to Dn. Each of the flip-flop circuits F0 to Fn has a write clock signal CL output from the write control unit 3.
K0 to CLKn are taken into the clock terminals C0 to Cn, respectively. Each of the flip-flop circuits F0 to Fn outputs the output signals FQ0 to FQn delayed by the number of clocks corresponding to the number of stages of the flip-flop circuits forming the transfer section from the output terminals Q0 to Qn to each selection input terminal S0 of the selector circuit 2.
To Sn.

The selector circuit 2 determines which of the output terminals Q0 to Qn of the flip-flop circuits F0 to Fn outputs the output signals FQ0 to FQn as the output data OuDt, and the selection signals SS0 to SS from the read control unit 4.
It is determined and output according to n.

The write controller 3 uses the input clock CLK.
A counter that cyclically counts up or down,
Write clock signal CLK0 according to the count value
To CLKn are sequentially output. The count value of the counter is the same as the number of stages of the flip-flop circuit. That is, the input clock CLK input to the write control unit 3 is counted, and when the count value is "0", the write clock signal CLK0 is supplied to the flip-flop circuit F0, and when it is "1", the write clock signal CLK1 is supplied. The clock terminals C0 to C of the flip flop circuits F0 to Fn are sequentially input to the flip flop circuit F1 and the write clock signal CLK2 to the flip flop circuit F2 in the case of "2", and so on.
Write clock signals CLK0 to CLKn are output to n.

The read control unit 4 receives the input clock CLK.
From the beginning, and a counter that cyclically counts up or down the input clock CLK that has passed through this register.
That is, the read control unit 4 operates to count the input clock CLK at a timing delayed by a predetermined number. This masked predetermined number corresponds to the delay time of the transfer unit.

Next, the operation of the transfer section of the IC test apparatus shown in FIG. 1 will be described with reference to FIG. 2 shows each flip-flop circuit F when the flip-flop circuit of FIG. 1 has three stages.
6 is a timing chart showing the operations of 0 to F2, the selector circuit 2, the write control unit 3, and the read control unit 4. FIG. In this timing chart, the transfer unit operates so as to delay the input data InDt by 2 clocks and output it.

That is, the write control circuit 3 which receives the input clock CLK receives the write clock C as shown in FIG.
LK0 to CLK2 are used as flip-flop circuits F0 to F2
Output to. The input data ID1 to ID9 are synchronized with the input clock CLK and the flip-flop circuits F0 to F0 are used.
2 is supplied. The flip-flop circuit F0 is synchronized with the write clock CLK0 and receives the input data ID1, ID
4, ID7, ... Are fetched and the output signal FQ0 is output to the selector circuit 2. The flip-flop circuit F1 receives the input data ID in synchronization with the write clock CLK1.
2, ID5, ID8, ... are taken in and output signal FQ
1 is output to the selector circuit 2. The flip-flop circuit F2 takes in the input data ID3, ID6, ID9, ... In synchronization with the write clock CLK2 and outputs the output signal FQ2 to the selector circuit 2.

At this time, since the read control unit 4 masks the first and second input clocks CLK, it operates based on a clock like the masking clock CLKM in FIG. Therefore, the read control unit 4 has three
The count operation is performed based on the th input clock CLK, and the count value is output to the selection terminal of the selector circuit 2 as the selection signals SS0 to SS2. The selector circuit 2 which receives the selection signal SS0 selectively outputs the output signal FQ0 of the flip-flop circuit F0. The selector circuit 2 which receives the selection signal SS1 selectively outputs the output signal FQ1 of the flip-flop circuit F1. The selector circuit 2 which receives the selection signal SS2 selectively outputs the output signal FQ2 of the flip-flop circuit F2. As a result, the selector circuit 2 outputs the output data OuDt obtained by delaying the input data InDt by 2 clocks.

As described above, according to the embodiment of the present invention,
Even if the frequency of the input clock is increased, the clock frequency supplied to the flip-flop circuit can be reduced to a fraction of the clock frequency, and current consumption and heat generation can be suppressed as much as possible.

[0036]

According to the present invention, there is an effect that current consumption by a high-speed clock and heat generation accompanying it can be suppressed as much as possible.

[Brief description of drawings]

FIG. 1 is a diagram showing a detailed configuration of a test pattern data transfer unit of an IC test apparatus of the present invention.

FIG. 2 is an operation timing chart of the data transfer unit when the flip-flop circuit of FIG. 1 has three stages.

FIG. 3 is a block diagram showing a schematic configuration of a conventional IC test apparatus.

FIG. 4 is a diagram showing a configuration of a data transfer unit that adjusts time of test pattern data in a conventional IC test apparatus.

5 is an operation timing chart of the data transfer unit when the flip-flop circuit of FIG. 4 has three stages.

[Explanation of symbols]

F0, F1 to Fn ... Flip-flop circuit, 2 ... Selector circuit, 3 ... Write control unit, 4 ... Read control unit, 5
0 ... Tester section, 51 ... Control means, 52 ... DC measuring means,
53 ... Timing generating means, 54 ... Pattern generating means,
55 ... Pin control means, 56 ... Pin electronics, 5
7 ... Fail memory, 58 ... Input / output switching means, 59 ... Data selector, 60 ... Formatter, 61 ... I / O formatter, 62 ... Comparator logic circuit, 63P ...
Pass / fail register, 64 ... Driver, 65 ... Analog comparator, 69 ... Tester bus, 70 ... IC mounting device, 71 ... IC to be measured

Claims (2)

(57) [Claims] 1. A plurality of storage circuit groups for receiving and outputting input data according to a write clock, write control means for sequentially supplying the write clocks to the storage circuit group according to the input clock, and the storage circuit. Selector means for outputting each output of the group in the same order as the above according to a selection signal, and masking only a predetermined number from the beginning of the input clock, and the selection signal according to the input clock after the masking. A data transfer device for an IC test device, comprising: a read control means for outputting to a selector means. 2. The data transfer apparatus for an IC test apparatus according to claim 1, wherein the input data is delayed by a timing corresponding to the number of masked clocks and output as the output data.