JPH11316260A - Semiconductor testing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor testing apparatus whose costs can be minimized a method wherein a driver enable leading (dre-i) pulse generator which generates an output enable (-OE) signal and a driver enable trailing (dre-t) pulse generator are used in common for all drivers. SOLUTION: In a plurality of test signal waveform shapers 35i, timing pulses are generated by output data from a cycle generator 10 by a set clock generator 21i and a reset clock generator 22i. Consequently, the timing of a test pattern signal from a waveform control circuit 26 is set so as to be given to an RSFF 31i, and the waveform of a test signal is given to a plurality of drivers 33i. In an -OE signal shaper 36, timing pulses of -OF signals of the drivers 33i are generated by output data from the cycle generator 10 by a dre-i pulse generator 23 and a re-t pulse generator 24, and they are given to an RSFF 32. The waveform of an -OF signal is generated, and it is given to -OE signal terminals of all the drivers 33i via a variable delay circuit VD.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a high density CMOS.
・ Construction using LSI, high timing accuracy,
The present invention relates to a semiconductor test apparatus having a very low-cost pin signal generator.

[0002]

2. Description of the Related Art First, an outline of a conventional semiconductor test apparatus will be described. FIG. 3 shows a basic configuration diagram of the semiconductor test apparatus. The test processor 1 controls the entire apparatus according to a test program, and supplies a control signal to each unit via a tester bus. Pattern generator 2 is a DUT
An application pattern to be applied to the device under test 9 and an expected value pattern to be applied to the pattern comparator 7 are generated. The timing generator 3 generates a timing pulse signal to obtain a test timing of the entire apparatus, and supplies the timing pulse signal to the waveform shaper 4, the comparator 6, the pattern comparator 7, and the like to determine a test timing. The waveform shaper 4 shapes the applied pattern from the pattern generator 2 into a real waveform test signal waveform, and supplies a test signal to the DUT 9 via the driver 5.

FIG. 3 shows a test example of a memory IC.
When writing test data to the DUT 9, the RW terminal of the DUT 9 is set to the write state, the driver 5 is set to output enable (/ OE), the switch is turned on, and the comparator 6 is turned on.
Switch is off. When the writing of the test data to the storage element in the test range is completed, the switch of the driver 5 is turned off, and the RW terminal of the DUT 9 is set to the read state,
The comparator 6 is input-enabled (/ IE) to turn on the switch, and the response signal is read. DUT
The response signal from 9 is compared with the reference voltage by the comparator 6, and the resulting logic signal is given to the pattern comparator 7.
The pattern comparator 7 logically compares the logical pattern of the test result from the comparator 6 with the expected value pattern from the pattern generator 2 to detect a match / mismatch, and determines the quality of the DUT 9. In the case of a failure which does not match the expected value, information is given to the fail memory 8 and stored together with information such as a failure address from the pattern generator 2, and failure analysis is performed later.

In order to generate signals for performing these operations, a table is prepared and data is stored in the pattern generator 2, the timing generator 3, and the waveform shaper 4. The data given to these tables is created by the programmer considering test patterns based on the performance data of the DUT 9 to create a test program, and is supplied from the test processor 1 to each unit.

The timing generator 3 has a RATE setting table and a clock setting table. The RATE setting table stores pattern period data (Test Period), and the clock setting table stores driver waveform timing data. ing. A plurality of groups, for example, a TS1 group, a TS2 group, a TSn group, and the like are prepared and read by combining these data, and a timing pulse of a set signal or a reset signal is generated. In the timing generator 3, the pattern cycle to be set is based on a reference clock (Reference Clock).
The fractional data of the reference clock may be added to the fractional data from the previous pattern cycle and the set fractional data, and the integral multiple data of the addition result may be delayed by a digital counter. , The fraction data is converted to one of the reference clocks using an analog variable delay circuit.
, 1/4, 1/8, 1/16,..., Etc., are accurately delayed to generate a timing pulse signal.

The table of the pattern generator 2 has a DUT
Test pattern data for each of the nine pins 1 to n is prepared. In the table of the waveform shaper 4, data relating to waveform settings such as a waveform mode is prepared.
Using the test pattern data from the pattern generator 2 and the set / reset timing pulse signals from the timing generator 3 to generate a test signal at a predetermined timing,
It is supplied to the driver 5.

[0007] By the way, the development of semiconductor ICs has been remarkable, and they have become more and more highly integrated. In recent LSIs (large-scale integrated circuits), there have appeared LSIs in which a combinational circuit and a storage element are composed of complicated sequential circuits. In order to test these complicated LSIs, semiconductor test devices have been developed. Conventional Shared Resource Tester
ter) to Per-pin Resour
An advanced tester called ce Tester) has also appeared. Also called a shared tester or a perpin tester. Here, the shared tester refers to a tester in which a plurality of resources such as a timing generator and a reference voltage are shared by all tester pins, and the per-pin tester is a DU.
This is a tester having a function in which test parameters applied to T9 can be set independently for each pin of DUT9. Parpin
The tester is more suitable for advanced LSI testing because it can generate more complex test patterns and more flexible conditions such as timing than a shared tester that uses test parameters in common for each pin of the DUT 9. ing.

Therefore, in the per-pin tester, the timing generator 3 and the waveform shaper 4 shown in FIG. 3 are collectively assigned to each pin of the DUT 9. Then, a pin signal generation portion in which the timing generator 3 and the waveform shaper 4 corresponding to each pin are combined, and a combination of the pattern comparator 7 and the calibration unit are assigned to each pin.

The present invention relates to a low-cost pin signal generation section with high precision timing. FIG. 4 shows a configuration diagram of a pin signal generation portion of a conventional shared tester, and FIG. 5 shows a configuration diagram of a pin signal generation portion of a per-pin tester. Both are composed of CMOS LSI. First, FIG. 4 will be described. The cycle generator 10 generates and holds the logic data of the test cycle based on the test program and the high-precision clock signal, and supplies them to the delay generator 11. The delay generation unit 11 includes a plurality of A clock generators, a B clock generator, a C clock generator, and a plurality of driver enable readings (driver enable l) for generating an output enable (/ OE) signal of the driver 33.
eading: pulse generator and driver enable trailing (hereinafter referred to as “dre-l”)
ailing: a pulse generator (hereinafter referred to as “dre-t”), which generates respective clocks based on the high-precision clock signal and the logic data from the period generator 10 and sends the clock to the clock distributor 12 Transmit. The clock distribution unit 12 receives a large number of clock signals from the delay generation unit 11 by the buffer ICs and distributes the clock signals to the plurality of pin signal generation units 13i.

The pin signal generator 13 includes a clock distributor 1
2, a selector for selecting one clock from each of a plurality of A clock groups, B clock groups, and C clock groups; a driver enable selector for selecting a driver enable clock from a driver enable clock group; There is a waveform control circuit 26 that receives the applied pattern and the waveform mode data from the waveform mode register 25 and outputs a test pattern signal. The test pattern signal from the waveform control circuit 26 is clocked by an AND circuit.
An AND operation is performed with the clock from the selector, and a timing pulse for determining the leading edge and the trailing edge of the test signal is output. The timing pulse is passed through a variable delay circuit (VD) for skew adjustment to the RS flip-flop 31 or R
The signal is sent to the set terminal or the reset terminal of the S flip-flop 32 to generate a timed test signal waveform.

The output waveform from the RS flip-flop 31 is supplied to the driver 33, and is supplied to the DUT 9 as a test signal having a voltage suitable for the DUT 9. An output signal from the RS flip-flop 32 is sent to an output enable (/ OE) terminal of the driver 33,
Turns the output on and off. The signals Ps, Pr, Pds, and Pdr output from the waveform control circuit 26 are signals for fixing the initial values of the RS flip-flops 31 and 32.

FIG. 5 shows a pin signal generating portion of the per-pin tester. In the figure, reference numerals 20 and 20i denote pulse wave generators (Pulse Wave Generators; hereinafter, “PWGs”).
I say). The PWG 20 is prepared for each pin of the DUT 9. And each PWG2
At 0, a set clock generator 21, a reset clock generator 22, a dre-l pulse generator 23, and a dre-t pulse generator 24 are provided. Therefore, only the logical data is received from the cycle generator 10 and each generates a clock signal. That is, each is a clock pulse generator and generates four timing edges (TE). Since this clock pulse is used, a variable delay circuit for skew adjustment is unnecessary.

As described above, the pin signal generation unit 13
The WG 20 is also formed of a CMOS LSI. C
In MOS / LSI, the delay time of a timing pulse fluctuates due to fluctuations in operating frequency, temperature, and voltage, and timing accuracy deteriorates. Timing accuracy is related to the time of passage of a timing pulse in a semiconductor device and the product of temperature variation and voltage variation. In terms of accuracy, the PWG 20 of the per-pin tester is good, and the pin signal generator 13 of the shared tester is not good. This is because, in a perpin tester, the passage time of a semiconductor element through which a highly accurate clock pulse passes is short. Conversely, in terms of cost, the per-pin TG including the period generator 10 of the per-pin tester is almost twice as expensive as the shared TG. Table 1 shows these comparison tables.

[0014]

[Table 1]

As shown in Table 1, only one location of the clock pulse generator causes the timing accuracy to be deteriorated at the per-pin TG. On the other hand, in the shared TG, at least, a high-precision clock generator in the cycle generator, a clock pulse generator in the delay generator, a clock distributor, a clock selector, a variable delay circuit,
And there are five places.

[0016]

By the way, PWG20
And the integration density of the CMOS / LSI constituting the pin signal generation unit 13 has been increasingly improved. For example, a CMOS having a line width of 0.35 μm
-When designing using an LSI, it has become possible to configure a PWG 20 for eight pins in one LSI. That is,
A configuration for generating about 32 TEs (timing edges) can be realized by one LSI.

The present invention is configured to generate, for example, 32 timing edges TE using a CMOS / LSI having a fine line width, the timing accuracy is equivalent to that of a conventional perpin tester, and the cost is reduced by a conventional shared tester. It is an object of the present invention to provide a new semiconductor test device which is equal to or less than the above.

In a semiconductor test apparatus for measuring a general-purpose memory IC, since there is generally one type of IO port, only one type of DRE serving as a control signal for the IO port may be used. Therefore, the output enable signal generation unit is not provided for each driver pin, and all the driver
It is an object of the present invention to provide a cost advantage by sharing the pins.

[0019]

In order to achieve the above object, the present invention employs a configuration of a per pin tester for generating a test signal, and a pair of set clock generators for each pin of the DUT. A reset clock generator, an RS flip-flop and a driver are allocated to maintain timing accuracy as high as that of a conventional perpin tester.

On the other hand, a pair of output enable (/ OE) signals to be applied to the / OE terminal of the driver are generated.
The number of dre-l pulse generators and dre-t pulse generators is minimized, for example, only one pair, and shared by all drivers in the same LSI. Generally, a general-purpose memory has one I / O port group, and a semiconductor memory test apparatus for measuring the DUT is particularly effective because the / OE signal is exactly the same. The RS flip-flop may be shared, but if a dedicated driver is used for each driver and the timing is adjusted by a variable delay circuit, a / OE signal with improved phase accuracy for each channel can be generated.

Therefore, if one CMOS LSI is configured to generate 32 timing edges (TE),
In the conventional configuration, 4TE is used for one pin of the DUT, so that eight pins can be incorporated. With the configuration of the present invention, 2T
By using E for generating the / OE signal, a test signal for 15 pins can be generated at 30 TE. In other words, the timing accuracy is equivalent to that of the conventional perpin tester, and the cost can be reduced to about 1 / 2.5.

Next, the configuration of the present invention will be described. The first invention has the following configuration. A pulse waveform generator of a semiconductor test device, which receives logic data from a cycle generator,
The timing of the test pattern signal from the waveform control circuit is obtained by the timing pulse of the pair of set clock generator and reset clock generator that generate the timing pulse of the test pattern signal, and is given to the RS flip-flop. A plurality of test signal waveform shapers for generating waveforms of test signals and supplying the waveforms to a dedicated driver, and timing pulses of output enable (/ OE) signals of the plurality of drivers in response to logic data from a cycle generator; A timing pulse of a pair of driver enable reading pulse generator and driver enable trailing pulse generator for generating a clock signal is supplied to an RS flip-flop to generate a waveform of an output enable signal. Apply to / OE terminal of all drivers through variable delay circuit And one / OE signal waveform shaper that is a semiconductor testing apparatus having a pulse waveform generator having.

A second aspect of the present invention is to obtain the phase accuracy of each channel by allowing the / OE signal of the first aspect of the invention to be finely adjusted in each channel. That is, /
The OE signal waveform shaper has an output enable (/
An OE) signal is provided with an RS flip-flop for each driver to provide a driver enable reading pulse signal and a driver enable trailing signal.
The delay time of the pulse signal can be adjusted by each variable delay circuit.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described based on embodiments with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of another embodiment. 4 and 5 are denoted by the same reference numerals. First, FIG. 1 will be described.

The PWG 40i shown in FIG. 1 has a pair of set clock generators 21 and reset clock generators 22 for generating timing pulses of a test pattern signal, and a timing control signal from the waveform control circuit 26 for each timing pulse. A plurality of n test signal waveform shapers 35 each including AND circuits 27 and 28 for taking the timing of the test pattern signal and an RS flip-flop 31 driven by the timed test pattern signal are arranged. And
Test signals output from the plurality of test signal waveform shapers 35 are given to a dedicated driver 33, and the output signal of the driver 33 is sent to the DUT. That is, a plurality of test signal waveform shapers of a conventional perpin tester are arranged.

On the other hand, there is only one pair of the driver enable leading pulse generator 23 and the driver enable trailing pulse generator 24 for generating the timing pulse of the output enable signal.
In addition, there is one / OE waveform shaper 36 composed of the RS flip-flop 32. This one / OE waveform shaper 3
6, the / OE terminals of all the drivers 33i in the LSI are controlled by the / OE signal output from the LSI. Other configurations and operations are the same as those of the conventional perpin tester.

FIG. 2 shows an arrangement in which RS flip-flops 32 for generating a / OE signal are exclusively used for respective drivers 33i. Others are almost the same as FIG.
Table 2 shows a comparison table between the one constructed by the present invention, the one constructed by the conventional perpin tester system, and the one constructed by the shared tester. Although the structure of the present invention is slightly more complicated than the conventional per-pin tester system, the accuracy is almost the same and the cost per DUT pin is the lowest.

[0028]

[Table 2]

[0029]

As described in detail above, the pulse waveform generator 40i in the high-density CMOS LSI constructed according to the present invention has the following effects as shown in the comparison table shown in Table 2. . In the conventional configuration using the per-pin TG method, only one LSI could be used to form the test signal waveform shaper 35 for eight pins.
Can be configured. Therefore, the cost per pin of the DUT is very low, about 1 / 2.5 that of the conventional per-pin TG method, and about 80% of the shared TG, which is the lowest.

The structure is slightly more complicated than the conventional perpin TG method, but simpler than the shared TG method. The timing accuracy of the set / reset timing pulse for the test signal is similar to that of the conventional perpin TG system, but the timing of dre-l and dre-r for the / OE signal is
The pulse gets worse. Still 2 / of shared TG method
5 or less, and high accuracy can be maintained.

As described above, although the pulse waveform generator of the present invention has high accuracy, its cost is lower than that of the shared TG system, and its structure is simpler than that of the shared TG system. The effect is great.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a configuration diagram of another embodiment of the present invention.

FIG. 3 is a basic configuration diagram of a semiconductor test apparatus.

FIG. 4 is a configuration diagram of a pin signal generation portion of a conventional shared tester.

FIG. 5 is a configuration diagram of a pin signal generation portion of a conventional per-pin tester.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Test processor 2 Pattern generator 3 Timing generator 4 Waveform shaper 5 Driver 6 Comparator 7 Pattern comparator 8 Fail memory 9 DUT (device under test) 10 Period generator 11 Delay generator 12 Clock distributor 13 , 13i pin signal generator 14 A clock selector (A Clok Selector) 15 B clock selector (B Clok Selector) 16 C clock selector (C Clok Selector) 17 dre selector 20, 20i Pulse waveform generator (Pulse Wave) Gener
ator) 21, 21i Set clock generator 22, 22i Reset clock generator 23 Driver enable reading (dre-l)
Pulse generator 24 Driver enable trailing (dre-t)
Pulse generator 25 Waveform mode register 26 Waveform control circuit 27, 27i, 28, 28i, 29, 30 AND circuit 31, 31i, 32, RS flip-flop 33, 33i Driver 35, 35i Test signal waveform shaper 36 / OE signal Waveform shaper 40, 40i Pulse Wave Generator
ator) VD variable delay circuit

Claims (2)

[Claims] A pair of set clock generators (21) for receiving a logical data from a period generator (10) and generating a timing pulse of a test pattern signal in a pulse waveform generator of a semiconductor test apparatus. The timing of the test pattern signal from the waveform control circuit (26) is determined by the timing pulses of the reset clock generator (22) and the reset clock generator (22), and the timing is applied to the RS flip-flop (31) to generate the test signal waveform. Upon receiving logic data from the plurality of test signal waveform shapers (35i) and the cycle generator (10) to be supplied to the corresponding drivers (33), the output enable (/ O) of the plurality of drivers (33i) is received.
E) A pair of driver enable reading pulse generators for generating timing pulses of the signal (23)
And a driver enable trailing pulse generator (24) for applying respective timing pulses to an RS flip-flop (32) to generate a waveform of an output enable (/ OE) signal and to generate respective variable delay circuits. A semiconductor test comprising: a single / OE signal waveform shaper (36) to be applied to the / OE terminals of all drivers (33i) via (VD); and a pulse waveform generator (40i) having apparatus. 2. The / OE signal waveform shaper (36) has an RS flip-flop (32i) for each driver (33i) for providing an output enable (/ OE) signal, and includes a driver enable reading pulse. The output signal of each of the signal and the driver enable trailing pulse signal is adjusted in delay time by a variable delay circuit (VD) to adjust the RS flip-flop (32i).
2. The semiconductor test apparatus according to claim 1, wherein the semiconductor test apparatus is driven.