JP2510973B2 - Semiconductor test equipment - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor test apparatus, and more particularly to a semiconductor test apparatus capable of testing a multi-pin VLSI with high precision timing.

[Background of the Invention]

As a conventional semiconductor tester for multi-pin VLSI, "19
83 International Test Conference (19
1983) (1983 International Test Conference) by Steve Bisset, “The Development of Attestor Perpin”
"Buyer SII Test System Architecture" (The Development of A Tester-per Pin VLSI T
est System Architecure), Mitchell Catalano, Richard Feldman (Ri)
chard Feldman), Robert Kurchanski (Rober
t Krutiansky), Richard Swan
"Individual Dual Signal Path Calibration For Maximum Timing Accuracy Accuracy In A High Pin Count Bryer S Test System" (Individual Signal Pa
th Calibration For Maximum Timing Accuracy in A Hi
gh Pincount VLSI Test System) is known.

The semiconductor test device described in the above document has a test accuracy,
In particular, it is intended to improve the timing accuracy and has the following configuration. That is, in order to improve the timing accuracy, the accuracy of both the output timing of the test waveform applied to the pin of the device under test and the determination timing for comparing the normality / abnormality of the response signal are improved for each pin. There is a need. Therefore, the semiconductor test apparatus described in the above document is provided with a timing generator for determining the output timing and the determination timing for each pin.

However, as the number of pins under test advances like VLSI,
Providing the above timing generation circuit for each pin
There is a problem that the hardware of the semiconductor device increases, the price increases, the power consumption increases, and the like.

[Object of the Invention]

The present invention has been made in view of the above-mentioned problems of the prior art, and it is possible to test a multi-pin VLSI with high precision timing, and to suppress an increase in hardware, an increase in price, an increase in power consumption, etc. It is an object of the present invention to provide a semiconductor test apparatus capable of performing the above.

[Outline of Invention]

The semiconductor test apparatus of the present invention is applied to a semiconductor test apparatus that outputs a test waveform to each pin of a semiconductor and stabilizes the pass / fail of the semiconductor from the response signal thereof, and has the following features. There is.

That is, an integer of the period T of the basic clock signal is output according to the first means for outputting the basic timing selection signal, which is provided in common for each pin, and the basic timing selection signal output from the first means. A second means for outputting a plurality of basic timing signals delayed by a double time, which is provided for each pin in common, and each address stores different timing setting values less than the cycle of the basic clock signal, And the above first
Which receives the basic timing selection signal output from the means as an address signal and outputs the timing setting value stored at the address, the register storing an arbitrary offset time, and the memory output from the memory. An adder for adding the timing set value and the offset time output from the register, and one of the plurality of basic timing signals, the unit of which is the cycle T of the basic clock signal, and the time corresponding to the output of the adder. First delay circuit for delaying the basic timing signal only, a synchronizing circuit for synchronizing the basic timing signal output from the first delay circuit and the basic clock signal, and a basic timing signal output from the synchronizing circuit , T / n (n is a positive integer)
A second delay circuit for delaying and outputting by a time corresponding to the output of the adder in the unit of the above, and a third means provided corresponding to each pin. It is characterized in that the test waveform is output and whether the test result is passed or not is determined in accordance with the output timing signal.

According to the present invention, the third means delays the basic timing signal by a predetermined time in units of the cycle T of the basic clock signal, and then synchronizes the delayed basic timing signal with the basic clock signal. Even if the propagation delay time of each circuit through which the basic timing signal passes changes due to the fluctuation of the ambient temperature or the fluctuation of the power supply voltage, if the change of the delay time is within one cycle of the basic clock. If so, it will be possible to absorb it automatically.

Further, according to the present invention, the second delay circuit of the third means outputs the basic timing signal output from the synchronization circuit after delaying it by a predetermined time in units of T / n. It is possible to remove an error in the test timing based on the propagation delay time of various circuits through which the basic timing signal passes, the length of the signal line, and the like.

Therefore, according to the present invention, the multi-pin VL can be used without increasing the hardware, increasing the price, and increasing the power consumption.
SI test can be performed with high precision timing.

Example of Invention

Hereinafter, the present invention will be described in more detail with reference to the embodiments shown in the accompanying drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention,
As shown in the figure, it is composed of an oscillator 100, a pattern generator 101, a basic timing generator 102, and pin control units 103a to 103n. The pin control units 103a to 103n are
The pin control units 103a to 103n are provided in the same number as the number of pins of the device under test, and have the same configuration.
Therefore, in the following description, the pin control unit 103a will be used.

The oscillator 100 outputs the basic clock signal 1 to the basic timing generator 102. The basic timing generator 102 outputs the basic timing selection signal 2 output from the pattern generator 101.
The basic clock signal 1 is divided in accordance with 2, and has a cycle (n ₁ T, n ₂ T, etc., hereinafter referred to as a test cycle) that is an integral multiple of the cycle T of the basic clock signal 1 as shown in FIG. The test cycle signal 23 is output. At the same time, the basic timing signal generator 102 outputs the test period signal 23 at the output time t according to the basic timing selection signal 22 as shown in FIG.
A plurality of basic timing signals 3 delayed from ₁ and t _{2 by} a time m ₁ T, m ₂ T which is an integral multiple of the period T of the basic clock signal 1.
Is output. Here, as shown in FIG. 2, the test cycle (n ₁ T, n
₂ T) changes according to the basic timing selection signal 22,
Similarly, the delay time of one basic timing signal 3 (m ₁ T, m
₂ T, etc.) is also changed in accordance with the basic timing selection signal 22.

The pattern generator 101 outputs a plurality of test pattern signals 2 over the test cycle defined by the test cycle signal 23 described above.

The selector 104a of the pin control unit 103a selects one test pattern signal from the plurality of test pattern signals 2 and outputs it as the test pattern signal 4 to the waveform formatter. Similarly, the selector 104a selects the test pattern signal 5 indicating the expected value of the test result from the plurality of test pattern signals 2 and outputs it to the digital comparator 109a. Similarly, the secreter 105a selects at least one basic timing signal from the plurality of basic timing signals 3 and outputs the basic timing signal to the timing adjusters 106a and 107a.
Output as 6,7.

The timing adjusters 106a and 107a are respectively the selector 105
After receiving the basic timing signals 6 and 7 selected in a and the basic clock signal 1 and synchronizing with the basic clock signal 1, the timing signals 8 and 9 having a resolution higher than that of the basic clock signal 1 are output.

The waveform formatter 108a receives the test pattern signal 4 and the timing signal 8 and creates a test waveform, and the driver 11
Output via 0a. This test waveform is input to the device under test (not shown), and the response signal from the device under test is input to the comparator 111a.

The comparator 111a compares the response signal from the device under test with a predetermined voltage and outputs a digital response signal. The digital comparator 109a makes a comparison / judgment at the input timing of the timing signal 9 as to whether or not the digital response signal and the test pattern signal 5 indicating the expected value of the test result match. As described above, the device under test is tested for each pin.

Next, details of the operation of the timing adjusters 106a and 107a shown in FIG. 1 will be described with reference to FIGS. Since the timing adjusters 106a and 107a have the same configuration,
Here, the timing adjuster 106a will be described. Third
As shown in the figure, the timing adjuster 106a includes a memory 202 that stores a timing setting value that is less than the cycle of the basic clock signal 1, and a register 201 that stores an offset value for adding an arbitrary time offset to the timing setting. An ALU 203 that performs addition operation of the offset value 24 output from the register 201 and the timing information 25 read from the memory 202
And a delay circuit for delaying the timing signal 7 created with the resolution of the basic clock signal 1 with the resolution of the basic clock.
204, a D flip-flop 205 that takes the timing signal 20 delayed by the delay circuit 204 and the cycle of the basic clock signal 1,
It is composed of a delay circuit 206 that delays the output 21 of the D flip-flop 205 with a resolution equal to or higher than the basic clock signal 1. Here, the resolution indicates, for example, in what time unit it is possible to control the rising times t ₃ and t ₄ at which the timing signals 20 and 9 have the theoretical value “1”. I have it. Specifically, the second
Since the rising time of the basic timing signal 3 shown in the figure can be controlled only in units of an integral multiple of the period T, the resolution is T.

According to FIG. 4, the timing adjuster 106a shown in FIG.
Will be described. The memory 202 is read by the timing selection signal 22 and the timing information 25 is output. On the other hand, the offset value 24 is output from the register 201, the ALU 203 adds the timing information 25 and the offset value 24, and outputs the added value 26. The added value 26 sets the delay times of the delay circuits 204 and 206. Here, the delay circuit 204 is configured so that the delay time can be set in units of T (T is the cycle of the basic clock signal 1) according to the added value 26. Due to the function of the delay circuit 204, the timing signal 7 is delayed by the unit of T for the set time,
Converted to timing signal 20. This timing signal 20
Is synchronized with the basic clock signal 1 at the D flip-flop 205 and then input to the delay circuit 206.

The delay circuit 206 is T / n (n is an integer) according to the added value 26.
The delay time can be set in units of. By the function of the delay circuit 206, the timing signal 21 having the resolution T is converted into the timing signal 9 having the resolution T / n.

The timing adjusters 106 and 107 have the following functions.
When the pin control units 103a to 103n corresponding to each pin select the same timing signal by the selectors 104 and 105 and the same timing setting is performed, the test waveform output from the pin control units 103a to 103n is the element under test. The input is made at the same timing. Another function is to control each pin control unit 103a from the device under test.
This is because the same determination result can be obtained when the output signals are input to 103n at the same timing. This is because of variations in the propagation delay time of the semiconductor elements that form the pin control units 103a to 103n.
The difference in the wiring length from 3a to 103n to the device under test is given to the register 201 in the timing adjusters 106 and 107 as the offset value 24 to correct it. In this way
Timing signal with test timing error due to propagation delay time and signal line length is removed, and resolution is T / n.
Is formed.

As is apparent from the above description, according to the above embodiment, the pin control unit 10 provided for each pin is provided.
Without providing a timing generator for all 3a to 103n,
Since a single basic timing generator is provided and a timing adjuster is provided in each of the pin control units 103a to 103n, a waveform under test can be output with high timing accuracy, and a pass / fail judgment can be performed with high timing accuracy. A test device can be provided.

〔The invention's effect〕

According to the present invention, even if the propagation delay time of various circuits through which the basic timing signal passes changes due to the fluctuation of the ambient temperature or the fluctuation of the power supply voltage, the change of the delay time is within one cycle of the basic clock. If it is a change of, it can be automatically absorbed. Further, according to the present invention, it is possible to eliminate an error in the test timing based on the propagation delay time of various circuits through which the basic timing signal passes, the length of the signal line, and the like. Further, according to the present invention, it is possible to provide a semiconductor test apparatus capable of performing a multi-pin VLSI test with high precision timing without increasing hardware, increasing cost, and increasing power consumption. .

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a semiconductor test apparatus according to the present invention, FIG. 2 is a time chart showing the operation of the embodiment shown in FIG. 1, and FIG. 3 is a summary of the embodiment shown in FIG. FIG. 4 is a block diagram showing a timing adjuster which is a part of FIG.
6 is a time chart showing the operation of the timing adjuster shown in the figure. 100 ... Oscillator, 101 ... Pattern generator, 102 ... Timing generator, 103a to 103n ... Pin control section, 10
4a ... Selector, 105a ... Secreter, 106a, 107a ... Timing generator, 108a ... Waveform formatter, 109a ...
Digital comparator, 110a …… Driver, 111a ……
Comparator, 201 ... Register, 202 ... Memory, 203
... ALU, 204 ... delay circuit, 205 ... D flip-flop, 206 ... delay circuit.

Claims (1)

(57) [Claims] 1. A semiconductor test apparatus for outputting a test waveform to each pin of a semiconductor, and judging whether the semiconductor is acceptable or not from the response signal thereof. One of them is provided commonly to each pin for outputting a basic timing selection signal. Common to each pin, which outputs a plurality of basic timing signals delayed by an integral multiple of the period T of the basic clock signal according to the first means and the basic timing selection signal output from the first means. A second means provided for each address, and different timing setting values less than the cycle of the basic clock signal are stored in each address, and the basic timing selection signal output from the first means is used as an address signal. The memory that receives and outputs the timing setting value stored at that address, the register that stores the arbitrary offset time, and the memory An adder for adding the output timing set value and the offset time output from the register, and one of the plurality of basic timing signals, and using the cycle T of the basic clock signal as a unit, A first delay circuit for delaying the basic timing signal by a time corresponding to the time, a synchronizing circuit for synchronizing the basic timing signal output from the first delay circuit and the basic clock signal, and an output from the synchronizing circuit. A second delay circuit that receives the basic timing signal and delays for a time corresponding to the output of the adder in units of T / n (n is a positive integer) and outputs the delayed signal And a pass / fail judgment according to the timing signal output from the third means.