JP3063357B2 - LSI tester - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI tester having a pin multi-mode for transmitting and receiving test data to and from a device under test (hereinafter referred to as "DUT") at a frequency higher than a test rate. LSI that exchanges test data with DUT based on clock
About testers.

[0002]

2. Description of the Related Art FIGS. 4 and 5 are time charts for explaining the operation of a conventional LSI tester in a pin multi-mode, in which two test data are output from a digital signal generation module to a DUT during one rate. It is a thing.
FIG. 4 shows a data format operation in the formatter, and FIG. 5 shows a latch clock format operation in the formatter.

Here, it is assumed that the digital signal generation module uses a 32-bit memory and outputs two data to the formatter at the same time. For this reason, in the memory, the odd bits of the data D _ai (i
= 1 to n), and the even bits are used for the data D _bi for the B channel. Then, one bit of which is used for Fomatto the latch clock CK _R. Here, one rate refers to the operation cycle of the memory.

In FIG. 4, (A) is a test rate clock CK _T , and (B) is a digital signal generation module A
The data D _ai , (C) output from the channel are the data D _bi , (D), (E) output from the B channel of the digital signal generation module, and the edge clocks CK _EA0 , C output from the timing generator to the formatter.
K _EB0 , (F) is the data D output from the formatter
_ai, D _bi, (G) is a data D _A input to the DUT.

[0005] (1) from the timing generator test rate clock CK _T is input, the memory outputs from the odd bit data D _ai in Fomatta outputs from even bit data D _bi to Fomatta. (2) Next, the formatter receives edge clocks CK _EA0 and CK _EB0 obtained by delaying the test rate clock CK _T from the timing generator.

(3) The formatter uses the edge clock CK _EA0
And Fomatto data D _ai outputted from the A channel, further Fomatto data D _bi output from the B-channel on the basis of the edge clock CK _EB0 based on. (4) The data D _ai and D _bi of the A and B channels are formatted by the formatter and then output to the DUT via the OR gate.

In FIG. 5, (H) and (I) show high-level signals H _A ,
H _B , (J) to (M) are edge clocks CK _EA1 , CK _EA2 , CK _EB1 , and CK output from the timing generator.
_EB2 , (N) is data D created by channel A
A latch clock CK _RA for latching _ai , (O) is a latch clock CK _RB for latching data D _bi generated by the B channel, and (P) is a latch clock CK _R output from the formatter to the DUT. The high-level signals H _A and H _B are output using one bit of the memory.

(1) The memory outputs the data D _ai and D _bi of the A and B channels to the formatter, and the signals H _A and H _{B in} which two bits not used for the data of the A and B channels are at a high level. Is output. (2) Subsequently, Fomatta the edge clock CK _EA1 and edge clock CK _EA2 obtained by delaying t ₂ hours the test rate clock CK _T from the timing generator obtained by delaying t ₁ hour is inputted.

(3) The formatter formats a latch clock CK _RA for latching data of channel A based on the high-level signal _HA input from the memory and the edge clocks CK _EA1 and CK _EA2 input from the timing generator. . (4) Subsequently, the formatter receives from the timing generator the edge clock CK _EB1 obtained by delaying the test rate clock CK _T by time t ₃ and the edge clock CK _EB2 obtained by delaying the test rate clock CK _T by time t ₄ .

[0010] (5) Fomatta is Fomatto the latch clock CK _RB for latching the data of the B-channel on the basis of the edge clock CK _EB1, CK _EB2 inputted from the high level signal H _B and timing generator to be input from the memory . (6) The formatter sets the latch clocks CK _RA and CK _RB to O.
The data is output to the DUT via the R gate, and the DUT latches the data D _ai and D _bi input from the OR gate based on the latch clocks CK _RA and CK _RB .

[0011]

SUMMARY OF THE INVENTION Such a conventional LS
The I tester generates a jitter in a latch clock for latching data due to a timing error between the edge clock CK _EA1 and the edge clock CK _EB1 as shown by a broken line in FIG. 5, for example, and the period T of the latch clock CK _R becomes T _1. , T ₂
And fluctuate unstablely. This causes a decrease in the S / N ratio in the measurement of the DA converter. Also, in the measurement of the AD converter, because of the jitter of the latch clock, the
An error occurs at the time of conversion, and the SN ratio decreases.

The present invention has been made in view of the above points, and obtains a latch clock to be output to a DUT based on a basic clock of a clock generator, and obtains a rate clock by dividing the basic clock. It is an object of the present invention to provide an LSI tester which can latch data output from a formatter by a latch clock having no jitter and accurately measure an LSI in which an analog circuit and a digital circuit are mixed.

[0013]

In order to achieve the above object, the present invention provides a method in which test data is exchanged with a test object at a frequency higher than a test rate clock, and an analog circuit and a digital circuit are mixed. L for inspecting inspection object
In an SI tester, a clock generator that divides the test rate clock by dividing a basic clock output from a synthesizer, and a plurality of digital signals that are simultaneously output by a digital signal generation module based on the test rate clock are used as the test rate clock. A formatter that formats with a plurality of edge signals obtained with a delay, a strobe circuit that holds a plurality of digital signals output by the object to be inspected with a plurality of strobe clocks obtained by delaying the test rate clock, A formatter latches a digital signal output to the object to be inspected, and a latch clock for latching a digital signal output to the strobe circuit by the object to be inspected is obtained based on the basic clock. Thailand to give things It is characterized by comprising a ring generator, a.

[0014]

The timing generator outputs an edge clock to the formatter and a strobe clock to the strobe circuit based on the test rate clock obtained from the clock generator. Further, the timing generator outputs a latch clock to the DUT based on the basic clock obtained from the clock generator, latches digital data input from the formatter, and latches digital data output from the DUT to the strobe circuit.

[0015]

An embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a configuration block diagram showing one embodiment of an LSI tester of the present invention. In the figure, reference numeral 10 denotes a mixed signal unit (hereinafter abbreviated as MS unit),
The digital signal and the analog signal for testing the UT 20 are output, and the digital signal and the analog signal output from the DUT 20 are analyzed. 30 in the test head DUT 20 is mounted, MS unit 10 performs signal Conde _Lee Shoninggu and switching of signals exchanged with DUT 20.

[0016] 40 is a clock generator, to obtain a test rate clock CK _T made reference operation of the device based on the basic clock CK ₀ to the output of the synthesizer 40 _1.
41 is a timing generator, to obtain an output to basic clock CK ₀ and test rate clock CK timing clock from the _T in the operating timing of the reading of the memory clock generator 40.

[0017] In MS unit 10, 11 is a digital signal generation module (hereinafter abbreviated as DSS module), the digital data of the test data to DUT20 based on a test rate clock CK _T input from the timing generator 40 D _{a i} , D _bi . 11
₁ is a source memory which test data is stored, 11 ₂ is a sequence generating circuit for designating an address of the source memory 11 _1.

[0018] 12 c _d Bufomu generator module for outputting a test waveform S _A analog to DUT (hereinafter, abbreviated as WFG module), 12 ₁ the sequence generator, 12 ₂ source memory, 12 ₃ DA It is a converter. 13 is a digital signal capture memory module (hereinafter abbreviated as a DSC module)
In a digital coded signal D _B is stored in the capture memory 13 ₁ in DUT 20, and analyzed. 13 ₂ is the start / stop control circuit for instructing writing of data to the capture memory 13 _1.

[0019] In 14 c _d Bufomu digitizer module (hereinafter abbreviated as WFD module), D
The analog signal S _A output from the UT 20 is converted to an AD converter 14 _1.
In after digital conversion, stored in the capture memory 14 _2, analyzing. 14 ₃ is a start / stop control circuit for instructing writing of data to the capture memory 14 _2.

[0020] In the test head 30, 31 is a
Source memory 11₁Digital data input from
TA D_ai, D_biFrom the timing generator 41
Edge clock CK_EA, CK_EBFormat based on
And driver 31₁To the DUT 20 via the. Seo
Memory 11₁Consists of 32 bits,
Data is stored to support multi-mode.
You. For example, the source memory 11₁Operating frequency, ie,
Test rate clock CK_TInspection data at twice the frequency of
In the case of pin multi mode that outputs
Even bits are assigned to channel B for A channel.
Hit.

When an address is designated from the sequence generation circuit 11 ₂ to the source memory 11 ₁ , the source memory 11 ₂
Outputs the data D _ai and D _ai of the A and B channels to the formatter 31 at the same time. The data D _ai and D _ai of the A and B channels input to the formatter 31 are formatted by two edge clocks CK _EA and CK _EB having different delay times input from the timing generator 41. That is, the digital data D _A is A during one rate.
DUT2 with B channel inspection data included
Output to 0.

Digital data D input to the DUT 20
_A is a signal from the timing generator 40 to the clock terminal C.
It is latched by the latch clock CK _R input to _R. DUT20 is the case of the DA converter, analog converted data S _B is output to the WFD module 14 by the input of the latch clock CK _R.

[0023] 32 is a strobe circuit for holding the digital data D _B which is input through the multiplexer (Figure omitted) from DUT 20, the delay time inputted from the timing generator 40 different strobe clock CK
_SA, holds data by CK _SB, stored in the capture memory 13 _1. The timing of the capture memory 13 ₁ of the writing is controlled by the test rate clock CK _T.

The reading of data from the DUT 20 to the strobe circuit 32 is performed by the latch clock CK _R output from the timing generator 41. For example, DU
When T20 is like an AD converter, WFG module 1
Analog signal input from the 2 is latched by the latch clock CK _R of the timing generator ₄₁ is digitally converted. As described above, in the LSI tester of the present invention, since the latch clock CK _R obtained by delaying the basic clock CK ₀ of the clock generator 40 becomes a timing signal at the time of data conversion, it is not necessary to consider generation of jitter.

FIG. 2 is a block diagram of a clock generator for generating a timing clock of the LSI tester of the present invention and a timing generator. 40 ₂ switch which outputs a basic clock CK ₀ to other modules,
40 ₃ basic clock CK to the output of the synthesizer 40 _1
A frequency dividing circuit that divides ₀ to obtain a test rate clock CK _T , and in this case, divides the basic clock CK ₀ by half.

The partial test rate clock CK _T output from the division circuit 40 _3, Dereirain 41 _1, 41 ₂ is output to the DSS module 11 and DSC module 13 via a programmable de Rei lines 41 _3, 4
Output 1 ₄ Fomatta 31 and strobe 32 through. Note that the programmable delay lines 41 ₃ and 41 ₄
The edge clocks CK _EA , CK _EB and the strobe clocks CK _SA , CK _SB output from the CPU have different delay times. In this case, two types are output. 41 ₅ In Dereirain delaying the basic clock CK _0, the output of which is output to the clock terminal of DUT20 as latch clock CK _R.

FIG. 3 is a timing chart for explaining the operation of the present invention, showing a case where a DA converter is tested in a pin multi-mode as an example. (A) shows the basic clock CK ₀ output from the clock generator 41,
(B) the test rate clock CK _T the clock generator 41 is outputted, (C) data D _ai outputted from the A channel of the source memory 11 _2, (D) data D output from the B-channel source memory 11 _{2 bi} , (E),
(F) shows the edge clocks CK _EA and CK _EB output from the timing generator 41, and (G) shows that the formatter 31
The data D _ai , D _bi , (H) output to the UT 20 correspond to the latch clock C output from the timing generator 41.
K _R, (I) is an analog signal S _B which DUT20 outputs the WFD module 14.

[0028] (1) When the test rate clock CK _T from the timing generator 41 is input to the source memory 11 _2, source memory 11 ₂ outputs the data D _a1 from A channel to Fomatta 31, data from the B-channel _Db1 is output. (2) Fomatta 31, subsequently, test rate clock CK _T edge obtained by delaying t ₁ hour clock CK _EA and edge clock CK _EB obtained by t ₂ time delay from the timing generator 41 is input.

(3) The formatter 31 outputs the edge clock C
The data D _a1 is formatted based on K _EA, and the data D _b1 is formatted based on the edge clock CK _EB . The data D _ai and D _bi output from the formatter 31 are output to the DUT 20 via an OR gate.

(4) The data D _ai input to the DUT 20,
D _bi is latched by the latch clock CK _R input to the clock terminal CR. (5) DUT 20 outputs the data D _ai, the analog signal S _B, based on D _bi the WFD module 14.

[0031]

As described in detail above, the L of the present invention
Since the SI tester obtains the latch clock applied to the DUT based on the basic clock, the latch clock has no jitter and can measure the DUT with high accuracy.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of an LSI tester according to the present invention.

FIG. 2 is a configuration block diagram of a clock generator and a timing generator of the LSI tester of the present invention.

FIG. 3 is a timing chart illustrating the operation of the present invention.

FIG. 4 is a time chart for explaining an operation of a conventional LSI tester in a pin multi-mode.

FIG. 5 is a time chart for explaining a pin multi-mode operation of a conventional LSI tester.

[Explanation of symbols]

 31 formatter 32 strobe circuit 40 clock generator 41 timing generator

Claims (1)

(57) [Claims] 1. An LSI tester for transmitting and receiving test data at a frequency higher than a test rate clock to an object to be inspected and inspecting the object to be inspected in which an analog circuit and a digital circuit are mixed, wherein the test rate clock is output from a synthesizer. A clock generator obtained by dividing the basic clock to be processed, and a plurality of digital signals output simultaneously by the digital signal generation module based on the test rate clock are formatted by a plurality of edge signals obtained by delaying the test rate clock. A formatter; a strobe circuit for holding a plurality of digital signals output from the object to be inspected by a plurality of strobe clocks obtained by delaying the test rate clock; and a digital signal output to the object to be inspected by the formatter. While latching A timing generator that obtains a latch clock for latching a digital signal output from the inspection object to the strobe circuit based on the basic clock and provides the latch clock to the inspection object. Tester.