JPS61228365A - System for testing signal processing lsi - Google Patents

System for testing signal processing lsi

Info

Publication number
JPS61228365A
JPS61228365A JP60068483A JP6848385A JPS61228365A JP S61228365 A JPS61228365 A JP S61228365A JP 60068483 A JP60068483 A JP 60068483A JP 6848385 A JP6848385 A JP 6848385A JP S61228365 A JPS61228365 A JP S61228365A
Authority
JP
Japan
Prior art keywords
signal processing
signal
processing lsi
testing
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60068483A
Other languages
Japanese (ja)
Inventor
Toshiji Yoshiki
吉木　利治
Isao Kato
功 加藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP60068483A priority Critical patent/JPS61228365A/en
Publication of JPS61228365A publication Critical patent/JPS61228365A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE:To make it possible to perform a test by one testing terminal, by providing a testing selector in a signal processing LSI and connecting the same to an external demultiplexer and an external memory. CONSTITUTION:A signal processing LSI2 is tested by selecting the parallel signal issued out from an objective digital signal processing block (DSP1)3 by a selector 9 operated in synchronous relation to an internal clock 8 and sending out said signal from a testing terminal C to accumulate the same in a memory 11 through an external demultiplexer 10. This operation is repeated a number of times corresponding to the number of signal bits. This accumulated memory content is converted by a D/A converter 12 to perform evaluation by a measuring device (M2)13. Therefore, only one terminal C may be used as the testing terminal and it is unnecessary to make a chip size large and the initial evaluation of planning is enabled and a planning time can be shortened.

Description

【発明の詳細な説明】 （産業上の利用分野） 本発明は高速動作の信号処理ＬＳＩ（大規模集積回路）
の試験方式に関する。[Detailed Description of the Invention] (Industrial Application Field) The present invention is a high-speed operation signal processing LSI (Large-scale integrated circuit)
Regarding the test method.

（従来の技術） 従来、信号処理ＬＳＩの試験方式は第２図に示す如きブ
ロック図で構成されていた。第２図において、デジタル
パタン発生器１から送出された信号は信号処理ＬＳＩ２
に入力されデジタル信号処理ブロック３，４を経て畝コ
ンバータ５でアナログ信号に変換され測定機６へ取込ま
れる。信号処理ＬＳ　Ｉ　２の試験は、対象となるデジ
タル信号処理ブロック（ＤＳＰＩ）３から出た信号をバ
タンチェッカ７に導き設計に対する評価を行なう。(Prior Art) Conventionally, a test method for a signal processing LSI has been constructed using a block diagram as shown in FIG. In FIG. 2, the signal sent from the digital pattern generator 1 is transmitted to the signal processing LSI 2.
The signal is input to the digital signal processing blocks 3 and 4, converted to an analog signal by the ridge converter 5, and taken into the measuring device 6. In testing the signal processing LSI 2, the signal output from the target digital signal processing block (DSPI) 3 is guided to the button checker 7 and the design is evaluated.

（発明が解決しようとする問題点） しかしながら、上記従来の方式によると、ＬＳＩは試験
のだめの端子（ａｔ〜ａｎ）ｅ信号のピット数に等しい
数（ｎ本）必要とし、このためＬＳＩチップのサイズが
犬きくな９、又設計時間も長くなってしまい、高速動作
の信号処理ＬＳＩには不適という欠点があった。(Problems to be Solved by the Invention) However, according to the above-mentioned conventional method, the LSI requires a number (n) of test terminals (at to an) equal to the number of pits of the e signal. It has disadvantages in that it is small in size9 and requires a long design time, making it unsuitable for high-speed operation signal processing LSIs.

この発明の目的は、信号処理ＬＳＩのチップサイズを必
要以上に犬きくすることなく初期の設計に対する評価が
可能で、しかも設計時間が短縮できる試験方式を提供す
ることにある。An object of the present invention is to provide a test method that allows evaluation of an initial design without increasing the chip size of a signal processing LSI more than necessary and that can shorten the design time.

また、高速動作の信号処理ＬＳＩ内部のアナログ評価を
も可能とする試験方式を実現することを目的とする。Another object of the present invention is to realize a test method that enables analog evaluation of the inside of a high-speed signal processing LSI.

（問題点を解決するための手段） 上記目的を達成するだめの本発明の特徴は、外部のデジ
タルパタン発生器からの信号を受入れ、内部状態を端子
を介して外部に取り出し試験する信号処理ＬＳＩの試験
方式において、信号処理ＬＳＩが内部クロックに同期す
るセレクタを有し外部にと９出す信号を順次選択して当
該信号の数よシ少ない試験端子により外部にとシ出し、
外部にとり出された信号を外付のデ・マルチプレクサを
介してメモリに蓄積した後該メモＩＪ　’ｒ読出して試
験する信号処理ＬＳＩの試験方式にある。(Means for Solving the Problems) The present invention is characterized by a signal processing LSI that accepts signals from an external digital pattern generator and outputs internal states via terminals for testing. In this test method, a signal processing LSI has a selector synchronized with an internal clock, sequentially selects nine signals to be output to the outside, and outputs them to the outside through test terminals smaller than the number of the signals.
This is a signal processing LSI test method in which a signal taken out to the outside is stored in a memory via an external demultiplexer, and then read out from the memory and tested.

（作用） 上記構成において、内部クロックに同期したセレクタは
ＬＳＩの内部信号を順次選択して、直列信号の形で外部
に提供する。従って、試験端子の数は直列信号の数（例
えば１）で十分であり、内部信号の数（又は従来の試験
端子数の数）に比べてはるかに少なくてすむ。外部にと
９出された信号はデ・マルチプレクサにより並列信号に
再変換されてメモリに蓄積され、該メモリを読出して試
験が行なわれる。(Operation) In the above configuration, the selector synchronized with the internal clock sequentially selects the internal signals of the LSI and provides them to the outside in the form of a serial signal. Therefore, the number of test terminals is sufficient for the number of serial signals (for example, 1), and is much smaller than the number of internal signals (or the number of conventional test terminals). The signals output to the outside are reconverted into parallel signals by a demultiplexer and stored in a memory, and the memory is read out for testing.

（実施例） 第１図はこの発明の構成例を示すブロック図である。(Example) FIG. 1 is a block diagram showing an example of the configuration of the present invention.

第１図においてデジタルパタン発生器１から送出した信
号は信号処理ＬＳＩ２に入力されデジタル信号処理ブロ
ック３，４ｔ−経て０４．コンバータ５でアナログ信号
に変換され測定機（Ｍｌ）６へ取込まれる。信号処理Ｌ
ＳＩ２の試験は対象となるデジタル信号処理ブロック（
ＤＳＰｔ）ａから出力された時系列のパラレル信号を内
部クロック８に同期して動作するセレクタ９により、ま
ず初めに信号ビットａｎが選択され信号ビットａｎ　の
時系列データが試験用端子Ｃから送出されデ・マルチプ
レクサ１０ヲ経てメモ１月１に蓄積される。続いて２回
目のデジタルパタン発生ではセレクタ９によシ信号ビッ
トａｎ−□が選択され信号ピッ）　ａｎ−１の時系列デ
ータがＣの試験用端子から送出されデ・マルチプレクサ
１０ヲ経てメモリ１１に蓄積される。In FIG. 1, the signal sent out from the digital pattern generator 1 is input to the signal processing LSI 2 and passes through the digital signal processing blocks 3 and 4t. It is converted into an analog signal by the converter 5 and taken into the measuring device (Ml) 6. Signal processing L
The SI2 test is based on the target digital signal processing block (
The selector 9, which operates in synchronization with the internal clock 8, selects the time-series parallel signal output from the DSPt)a, and the signal bit an is first selected, and the time-series data of the signal bit an is sent from the test terminal C. The memo will be accumulated on January 1 after 10 demultiplexers. Subsequently, in the second digital pattern generation, the selector 9 selects the signal bit an-□, and the time series data of the signal an-1 is sent out from the test terminal of C and sent to the memory 11 via the demultiplexer 10. Accumulated.

この動作が信号ビットの数ｎ回だけ繰り返されることに
より時系列のｎビットパラレル信号がメモリ上に蓄えら
れ、°これ”ｔＤＡコンバータ１２によりデジタル・ア
ナログ変換し測定機（Ｍ２）１３でアナログ信号として
の評価が行なわれる。By repeating this operation n times, the number of signal bits, a time-series n-bit parallel signal is stored in the memory, which is converted from digital to analog by the DA converter 12 and converted into an analog signal by the measuring device (M2) 13. An evaluation will be conducted.

また１本試験方式の測定システムを用いることにより初
期の設計段階にある信号処理ＬＳＩ内部の試験したい信
号処理ブロックに任意にセレクタを設けることによって
試験が容易に行なうことができ、設計時間を短くできる
。In addition, by using a measurement system with a single test method, testing can be easily performed by providing a selector for the signal processing block to be tested inside the signal processing LSI in the early design stage, and the design time can be shortened. .

さらに、−担メモリ内に蓄えられたデータを直接ｎビッ
トパラレルに呼び出すことにより従来通シバタンチェッ
カを用いた試験も可能である。Furthermore, by directly reading data stored in the carrier memory in n-bit parallel fashion, it is also possible to perform a test using a conventional checker.

（発明の効果） この発明は以上説明したように信号処理ＬＳＩ内部に試
験用のセレクタを設は測定システムとして外部にデ・マ
ルチプレクサとメ°モＩＪ　ｋ接続することによシ試験
用端子が一端子（端子Ｃ）のみですむという利点がある
。更にデジタル・バタン発生を繰返し行なうことによっ
て高速動作の信号処理ＬＳＩの試験に適している。更に
信号処理ＬＳＩ内部の信号が容易に取出せアナログ信号
への変換もできるので波形・雑音特性・信号レベル・位
相のアナログ評価が可能である。また、初期設計段階で
の設計時間の短縮が出来る。(Effects of the Invention) As explained above, the present invention provides a test selector inside a signal processing LSI and connects a demultiplexer and a memory IJ to the outside as a measurement system, thereby making it possible to connect test terminals to the outside. This has the advantage that only a terminal (terminal C) is required. Furthermore, by repeatedly generating digital bangs, it is suitable for testing high-speed operation signal processing LSIs. Furthermore, since the signals inside the signal processing LSI can be easily taken out and converted into analog signals, analog evaluation of waveforms, noise characteristics, signal levels, and phases is possible. Moreover, the design time at the initial design stage can be shortened.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明によるＬＳＩの試験方式を示すブロック
図、第２図は従来のＬＳＩの試験方式を示すブロック図
である。 １、デジタル・バタン廃生器、２．信号処理ＬＳＬ３、
信号処理ブロック１．４．信号処理ブロック２．５、　
Ｄ／Ａコンバータ１．６．測定機１，７．バタンチェッ
カ、８．内部クロック、９．セレクタ、１０．デ・マル
チプレクサ、１１．メモリ（ＲＡＭ）　、　１２．Ｄ／
Ａコンバータ、１３測定機２．ａ１．試験用端子ａ、（
データＬＳＢ）、ａｙｅ、試験用端子ａｎ（データＭＳ
Ｂ）、Ｃ１試験用端子Ｃ（１ピントデータ）FIG. 1 is a block diagram showing an LSI testing method according to the present invention, and FIG. 2 is a block diagram showing a conventional LSI testing method. 1. Digital slam waste generator, 2. Signal processing LSL3,
Signal processing block 1.4. signal processing block 2.5,
D/A converter 1.6. Measuring device 1, 7. Batanchecka, 8. Internal clock, 9. Selector, 10. Demultiplexer, 11. Memory (RAM), 12. D/
A converter, 13 measuring devices 2. a1. Test terminal a, (
data LSB), aye, test terminal an (data MS
B), C1 test terminal C (1 pinto data)

Claims (2)

【特許請求の範囲】[Claims] （１）外部のデジタルパタン発生器からの信号を受入れ
、内部状態を端子を介して外部に取り出し試験する信号
処理ＬＳＩの試験方式において、信号処理ＬＳＩが内部
クロックに同期するセレクタを有し外部にとり出す信号
を順次選択して当該信号の数より少ない試験端子により
外部にとり出し、外部にとり出された信号を外付のデ・
マルチプレクサを介してメモリに蓄積した後該メモリを
読出して試験することを特徴とする信号処理ＬＳＩの試
験方式。(1) In a signal processing LSI test method that accepts a signal from an external digital pattern generator and outputs its internal state to the outside via a terminal for testing, the signal processing LSI has a selector that synchronizes with the internal clock and is Sequentially select the signals to be output and take them out through fewer test terminals than the number of signals concerned, and connect the signals taken out to the outside with an external device.
A test method for a signal processing LSI characterized by storing data in a memory via a multiplexer and then reading out the memory for testing. （２）前記試験端子の数が１であることを特徴とする特
許請求の範囲第１項記載の信号処理ＬＳＩの試験方式。(2) The signal processing LSI test method according to claim 1, wherein the number of test terminals is one.
JP60068483A 1985-04-02 1985-04-02 System for testing signal processing lsi Pending JPS61228365A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60068483A JPS61228365A (en) 1985-04-02 1985-04-02 System for testing signal processing lsi

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60068483A JPS61228365A (en) 1985-04-02 1985-04-02 System for testing signal processing lsi

Publications (1)

Publication Number Publication Date
JPS61228365A true JPS61228365A (en) 1986-10-11

Family

ID=13374973

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60068483A Pending JPS61228365A (en) 1985-04-02 1985-04-02 System for testing signal processing lsi

Country Status (1)

Country Link
JP (1) JPS61228365A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63256877A (en) * 1987-04-14 1988-10-24 Mitsubishi Electric Corp Test circuit
US6949940B2 (en) 1998-06-16 2005-09-27 Infineon Technologies Ag Device for measurement and analysis of electrical signals of an integrated circuit component

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63256877A (en) * 1987-04-14 1988-10-24 Mitsubishi Electric Corp Test circuit
US6949940B2 (en) 1998-06-16 2005-09-27 Infineon Technologies Ag Device for measurement and analysis of electrical signals of an integrated circuit component
US7239162B2 (en) 1998-06-16 2007-07-03 Infineon Technologies Ag Device for measurement and analysis of electrical signals of an integrated circuit component
US7342404B2 (en) 1998-06-16 2008-03-11 Infineon Technologies Ag Device for measurement and analysis of electrical signals of an integrated circuit component

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