JP2001142733A - Internal signal observation device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To output internal information on a time-division basis by capturing data and dynamically processing internal signals which are as many as the number of terminals multiplied by (n) with a small number of terminals by using an internal signal observation device and sampling a plurality of signals of the same time or by using a substitutional means. SOLUTION: The internal signal observation device has a data capture part, a signal selecting means, a preset counter, a counter overflow terminal and an output terminal, and outputs a number of pieces of internal information from a limited number of test terminals by capturing data with a sampling clock and outputting internal signals on a time-division basis.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the efficiency of debugging, evaluation, and analysis in system LSIs, microcomputers, DSPs, and the like. By incorporating this internal signal observation device, time-division processed information is output from a limited number of test terminals, and multiple (test terminal x n) states can be dynamically observed externally, so debugging, evaluation, and analysis Can greatly contribute to

[0002]

2. Description of the Related Art Conventionally, even if several key devices are mounted on one printed circuit board, an interface between the devices is connected by an external output terminal and an external input terminal. Observation of the waveform at that location can be easily realized by measuring equipment because the signal exists outside. However, in recent years, with the progress of the process, the approach of integrating the entire system into one chip has been rapidly advanced, so that even the signals connected by the external output terminal and the external input terminal between the conventional key devices are wired in silicon. Is to be done. Although the in-circuit emulator and the on-board debugging environment have been prepared for the debugging means and analyzing means of each key device, it is not easy to observe the waveform of the connection signal on the measuring instrument.

Now, a specific description of a conventional example will be described with reference to FIGS. 9 and 10. FIG.

In FIG. 9, 1 is a processor, 2 is a memory, 3 is a DSP, 4 is an ASIC, 5 is a user terminal 1 of the processor 1, 6 is a user terminal 2 of the ASIC 4, and 7 is a DS.
User terminals 3 and 8 of P3 are a system LSI in which a plurality of key devices are integrated into a system, and 9 is a processor 1
And the internal wiring of the memory 2, 10 is an observation test terminal 1 of the internal wiring 9, 11 is an observation test terminal 2 of the internal wiring of the processor 1 and the ASIC 4, 12 is an observation test terminal 3 of the internal wiring of the ASIC 4 and the DSP 3, 13 is memory 2 and DS
An observation test terminal 4 for the internal wiring of P3. The test terminal 10, the test terminal 11, the test terminal 12, and the test terminal 13 are unnecessary in the final set.
Since it may be needed at the stage of analysis, it is prepared as an external terminal. This method is not very efficient because the number of terminals increases while many unnecessary test terminals remain during mass production.

Further, Japanese Patent Laid-Open Publication No.
No. 4819 is known. FIG. 10 shows the structure of a conventional "information processing apparatus and evaluation system and evaluation of this apparatus". 14 is an internal signal 0 that can be observed, 15 is an internal signal 1 that can be observed, 16 is an internal signal 2 that can be observed, and 17 is a signal that selects one output signal from eight inputs. 8: 1 selector for selecting one output signal from eight inputs, 19 for an 8: 1 selector for selecting one output signal from eight inputs, and 20 for selector 17 , The selector 18 and the selector 19, the selection signal of the 8: 1 selector,
Reference numeral 21 denotes a block ISO for selecting three output signals from the 24 input signals by using the selection signal 20. It comprises a selecting means for selecting a part of signals from a plurality of internal signals in accordance with a selection signal and outputting the selected signal to the outside.

[0006]

In this "information processing apparatus and evaluation system and evaluation of this apparatus",
There is a need for an evaluation device that can be observed externally in real time. Since the selection signal 20 is set statically, it is impossible to observe more than the number of test terminals. Therefore, in order to observe a plurality of signals at the same time, it was necessary to incorporate the ISO 21 into a plurality of blocks. According to the first aspect of the present invention, a plurality of signals at the same time are sampled or replaced by a means for data capture, dynamically processing the number of terminals × n internal signals with a small number of terminals, and outputting the internal information in a time sharing manner. With the goal.

[0007]

In order to solve this problem, the present invention requires that a signal that can be observed is determined in advance so that data can be captured. The data capture means can also be realized by FIFO. By combining this with the selection means and the preset counter, data capture information is output in a time sharing manner. At this time, it is necessary for the external measuring device to simultaneously observe the test terminal, the clock, and the counter overflow signal.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention has a data capture section, a signal selecting means, a preset counter, a counter overflow terminal, and an output terminal.
An internal signal observation device characterized by outputting a large number of internal information from a limited number of test terminals by time-divisionally outputting after capturing multiple internal signals with a sampling clock, and Has the effect that the states of the multiple signals can be observed externally.

According to a second aspect of the present invention, there is provided the internal signal observing apparatus according to the first aspect, and further comprising an edge detecting unit, a synchronization circuit, or a process for masking information update during data output. The internal signal observation device according to claim 1, wherein data is output to the outside with priority on information update. The invention of claim 1 is to acquire data at the same time by sampling. In No. 2, since the state changed by the edge detection circuit is recorded in the data capture unit, it has the effect of eliminating acquisition errors and jitter due to sampling timing.

According to a third aspect of the present invention, there is provided the internal signal observing device according to the first or second aspect, and further comprising a data holding unit capable of freely setting the selection order of the signal selecting unit. And an observation signal combination means capable of changing the order and combination of output to the outside. The internal signal observation apparatus according to claim 1, wherein Since the combination can be set in a programmable manner, only the internal signal of interest can be output to the external test terminal.

The first embodiment of the present invention will be described below with reference to FIGS.

(Embodiment 1) FIG. 1 is a block diagram showing a basic configuration of an internal signal observation device.

In FIG. 1, reference numeral 22 denotes an internal signal observation device;
Reference numeral 3 denotes an internal signal that may output a signal inside the silicon and be observed, 24 denotes a data capture unit that obtains the internal signal 23 by a sampling clock, and 25 denotes internal information obtained under the conditions of the data capture unit 24. , 26 are selection means, 27 is an external terminal, a test terminal for observing an internal signal, 28 is a preset counter, 29 is an output of the preset counter 28, a select signal for controlling a select terminal of the selection means 26, 30 is a preset counter 28 Reference numeral 31 denotes an overflow terminal of the preset counter 28.

FIG. 2 shows a more detailed embodiment. This is described as four types of internal signals,
The preset counter 28 and the selection means 2 having the basic configuration of FIG.
By increasing or decreasing the number of test terminals 6 and the number of test terminals 27, the same operation can be achieved. 2230 is an internal signal, a signal 0 that may be observed, 2231 is an internal signal, a signal 1 that may be observed, 2232 is an internal signal, a signal 2 that may be observed, and 2233 is an internal signal. Signals 3 and 32 that can be observed are flip-flops that latch signal 2230 at the overflow terminal 31 of the preset counter, 33 are flip-flops that latch signal 2231 at the overflow terminal 31 of the preset counter, and 34 is a signal that presets signal 2232 Flip-flop latched at the overflow terminal 31 of the counter, 3
A flip-flop 5 latches the signal 2233 at the overflow terminal 31 of the preset counter.

FIG. 3 is a truth table of the selection means 26.

FIG. 4 is a timing chart of the internal signal observation device.

4230 is an input timing of the signal 2230; 4231 is an input timing of the signal 2231;
2 is the input timing of the signal 2232 and 4233 is the signal 2
233 is the input timing of the source clock 30 of the preset counter 28, 428 is the output timing of the preset counter 28, 431 is the output timing of the overflow of the preset counter 28, 429 is the select input timing of the selection means 26,
427 is an output result of the test terminal by the sampling means. Reference numerals 36, 37, and 38 indicate sampling clocks at the rising edge of the overflow 431.

Hereinafter, embodiments will be described step by step with reference to the timing charts of FIGS.

The internal signals that need to be observed in advance need to be wired to the signals 2230, 2231, 2232, and 2233 of the internal signal observation device.

The source clock CLK30 of the preset counter 28 is input from an external terminal. This can use the internal system clock, and if a clock divider is added, the sampling rate can be changed. To output four types of signals, the preset counter 428 changes from 0 → 1 → 2 → 3 → 0, and when it reaches 0, the OVR 431 is set. The OVR 431 is connected to the sampling clocks 36 and 37 of the data capture unit 24,
Use 38. As shown in the truth table of FIG. 3, the selection means 26 outputs one of the four signals to the test terminal 427 using the select signal 429 as a four-input signal. The control of the select signal 429 is dynamically performed by the preset counter 428.
This is achieved by using the output of When observed externally, it changes as shown by the test terminal 427, but since four types of signals are output in a time-division manner, it becomes impossible to associate the respective signals. OVR431 to judge it
The signal can be determined by observing the clock signal and the clock signal 430 at the same time.

The reason for using the preset counter 28 is as follows.
This is in order to respond to a request to observe three types of signals. In order to externally output three types of signals in this configuration, when the preset counter 28 is set to x'3 ', the preset counter 428 changes from 0 to 1 to 2 to 0. However, the signal 2230, the signal 2231, the signal 2232
Will be limited.

(Embodiment 2) Next, Embodiment 2 of the present invention will be described with reference to FIGS.

FIG. 5 is a block diagram showing a configuration in which a change in the internal signal of the internal signal observation device is output with priority. In FIG. 5, 5230 is an internal signal, a signal 0 that may be observed, 5231 is an internal signal, a signal 1 that may be observed, 5232 is an internal signal, and a signal 2 and 5233 that may be observed are Signal 3 which is an internal signal and may be observed.

Reference numeral 39 denotes an edge detection circuit for detecting that the signal 5230 has changed, reference numeral 40 denotes an edge detection circuit for detecting that the signal 5231 has changed, and reference numeral 41 denotes a signal 5232.
Is an edge detection circuit for detecting that the signal 5233 has changed, and 42 is an edge detection circuit for detecting that the signal 5233 has changed. 32 is a flip-flop that latches when the signal 5230 changes, 33 is a flip-flop that latches when the signal 5231 changes, and 34 is a flip-flop that latches when the signal 5232 changes. , 35 are flip-flops that latch when the signal 5233 changes. Reference numeral 43 indicates that when the signal 5230 changes while the selection unit 26 outputs the latch data of the signal 5230, a hazard may be generated from the test terminal. A mask gate 44 for preventing this may cause a hazard from the test terminal when the signal 5231 changes while the selector 26 outputs the latch data of the signal 5231. A mask gate 45 for preventing this may cause a hazard from the test terminal when the signal 5232 changes while the selection means 26 outputs the latch data of the signal 5232. A mask gate 46 for preventing this is provided.
When the signal 5233 changes while the latch data of No. 3 is being output, a hazard may be generated from the test terminal.
This is a mask gate for preventing this. 47 is a mask signal S_00 of the mask gate 43; 48 is a mask signal S_01 of the mask gate 44;
Are the mask signals S_11 of the mask gate 46, which can be generated by a decode signal from the select signal 29 of the selection means 26.

FIG. 6 is a timing chart when the edge detection circuit of FIG. 5 is incorporated. 6230 is the signal 52
30, 6231 is the input timing of the signal 5231, 6232 is the input timing of the signal 5232, 6233 is the input timing of the signal 5233, 630.
Is the input timing of the source clock 30 of the preset counter 28, 628 is the output timing of the preset counter 28, 631 is the overflow output timing of the preset counter 28, 629 is the select input timing of the selection means 26, and 627 is the edge detection means. It is the output result of the test terminal at the time. 648 is the signal 62
31 is a signal indicating that the signal 31 is being output.
148. This is the select signal 2 of the selection means 26.
9 is generated by decoding. 51 is signal 6
Latch timing at a change point of 232, 52 is a signal 62
Latch timing at a change point of 31;
1 and the latch timing at the transition point of the signal 6233, 54
Is the latch timing at the transition point of the signal 6232, 55 is the latch timing at the transition point of the signal 6233, 56 is the latch timing at the transition point of the signal 6230, and 57 is the latch timing at the transition point of the signal 6233. When this apparatus is used, the effect of this apparatus can be read by comparing the results of the test terminal 427 of FIG. 4 and the test terminal 627 of FIG. At the latch timing 52, the signal 6231
However, the signal 6231 is being output to the test terminal 627, and a hazard occurs when the signal changes asynchronously. The mask gate 44 functions to prevent this. The gate control is S_0148 and the timing signal is 648
As shown in FIG.

Third Embodiment Next, a third embodiment of the present invention will be described with reference to FIGS.

FIG. 7 is a block diagram showing a configuration in which the output order and combination of the internal signal observation device can be changed.

In FIG. 7, 7230 is an internal signal, a signal 0 that can be observed, 7231 is an internal signal, a signal 1 that can be observed, and 7232 is an internal signal, a signal 2 that can be observed. , 7233 are internal signals which are signals 3 which may be observed. 39 is signal 7
Edge detection circuit for detecting that 230 has changed, 4
0 is an edge detection circuit that detects that the signal 7231 has changed, 41 is an edge detection circuit that detects that the signal 7232 has changed, and 42 detects that the signal 7233 has changed. This is an edge detection circuit. 32 is a signal 723
A flip-flop that latches when 0 has changed,
33 is a flip-flop that latches when the signal 7231 changes, 34 is a flip-flop that latches when the signal 7232 changes, and 35 is a signal 7233.
Is a flip-flop that latches when there is a change. Reference numeral 43 indicates that when the signal 7230 changes while the selection unit 26 outputs the latch data of the signal 7230, a hazard may be generated from the test terminal. The mask gate 44 for preventing this is selected by the selecting means 26 from the signal 7231.
When the signal 7231 changes while the latch data is output, there is a possibility that a hazard may come out from the test terminal. A mask gate for preventing this, 45 is a selecting means 26
While the latch data of the signal 7232 is being output.
When there is a change in, there is a possibility that a hazard may come out from the test terminal. Mask gate 46 for preventing this
When there is a change in the signal 7233 while the selection unit 26 is outputting the latch data of the signal 7233, there is a possibility that a hazard may come out from the test terminal. This is a mask gate for preventing this. 58 is a register SR0 for selecting when the output of the preset counter 28 is 0, and 59 is a register SR for selecting when the output of the preset counter 28 is 1.
1 and 60 are registers SR2 and 61 for selecting when the output of the preset counter 28 is 2, and the registers SR2 and 61 are
Is a register SR3 to be selected when the output is 3. SR
0 58, SR1 59, SR2 60, SR3 61
Is the select signal 29 of the selection means 26
Is a two-bit register.

FIG. 8 shows a timing chart when SRn of FIG. 7 is incorporated.

Reference numeral 8231 denotes an input timing of the signal 7231; 8233, an input timing of the signal 7233;
Is the input timing of the source clock 30 of the preset counter 28, and 828 is x ′ to the preset counter 28.
Counter output timing when 2 'is set, 831
Is the overflow output timing 829 of the preset counter 28 is the select input timing of the selection means 26,
Reference numeral 827 denotes an output result of the test terminal when the observation signal combination means SRn is incorporated. 848 is the signal 8231
Is a signal indicating that S_01 is being output.
48. This is generated by decoding the select signal 29 of the selection means 26. 850 is the signal 82
A signal indicating that 33 is being output is S_1 in FIG.
150. This is the select signal 2 of the selection means 26.
9 is generated by decoding. 62 is signal 8
Latch timing at the change point of 231, 63 is the signal 82
Latch timing at a change point of 31;
The latch timing at the change point of No. 3 is 65, and 65 is the signal 8233
Is a latch timing at a change point of the signal 8233, and 66 is a latch timing at a change point of the signal 8233.

A feature of the present invention is that the internal signals can be freely ordered,
Since the combination can be set, the case where the signal 8231 and the signal 8233 are observed is described in FIGS.
This will be described in detail with reference to FIG.

First, x'1 'and SR1 are added to SR0 58.
Set x'3 'to 59.

Next, it is only necessary to set x'2 'in the preset counter 28 in order to observe two types of signals. Even in this case, there is no particular problem because a mask gate for preventing a hazard is included. When this apparatus is used, the effect of this apparatus can be read by comparing the results of the test terminal 627 of FIG. 6 and the test terminal 827 of FIG.

In FIG. 6, at the latch timing 53, the signal 6233 latches x'C ', but the test terminal 6
27 is not output. This means that an output omission has occurred because the data is periodically output to the outside by the time division processing. The problem is solved by enabling the output order and the output setting of only necessary signals.

In the above description, an example is described in which the present invention is implemented by hardware. However, the present invention can be implemented in the same manner by using other software. For example, system LSI
The same effect can be obtained by mounting a small-scale microcomputer, reading internal information from the port and outputting the data from the port after data processing. In the medium, not only silicon but also F
D and the software on the HDD enable the same concept.

[0036]

As described above, according to the first aspect of the present invention,
The invention described in (1) has a data capture unit, a signal selection means, a preset counter, a counter overflow terminal, and an output terminal, and captures a plurality of internal signals with a sampling clock, and then outputs the signals in a limited number by time-sharing output. This is an internal signal observation device characterized by outputting a lot of internal information from a test terminal, and enables external observation of the state of a plurality of signals at the same time.

According to a second aspect of the present invention, there is provided the internal signal observing device according to the first aspect, and further comprising an edge detection unit, a synchronization circuit, or a process for masking information update during data output. The internal signal observation device according to claim 1, wherein data is output to the outside with priority on information update. The invention of claim 1 is to acquire data at the same time by sampling. In No. 2, since the state changed by the edge detection circuit is recorded in the data capture unit, there is an effect of eliminating an acquisition error and jitter due to sampling timing.

According to a third aspect of the present invention, there is provided the internal signal observation device according to the first or second aspect, and further comprising a data holding unit capable of freely setting the selection order of the signal selection unit. And an observation signal combination means capable of changing the order and combination of output to the outside. The internal signal observation apparatus according to claim 1, wherein Since the combination can be set programmably, it is possible to output only the internal signal of interest to the external test terminal.

[Brief description of the drawings]

FIG. 1 is a block diagram of a basic configuration of an internal signal observation device.

FIG. 2 is a diagram showing a detailed example of an internal signal observation device.

FIG. 3 is a truth table of selection means.

FIG. 4 is a timing chart of a test terminal by a sampling unit.

FIG. 5 is a configuration block diagram when a change in an internal signal of the internal signal observation device is preferentially output.

FIG. 6 is a timing chart when edge detection means is incorporated.

FIG. 7 is a configuration block diagram in which the output order and combination of the internal signal observation device can be changed.

FIG. 8 is a timing chart when the observation signal combining means SRn is incorporated.

FIG. 9 is a diagram showing a conventional example when an internal signal is observed.

FIG. 10 is a diagram showing a conventional internal signal observation means described in JP-A-6-214819.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Processor 2 Memory 3 DSP 4 ASIC 5 User terminal 1 6 User terminal 2 7 User terminal 3 8 System LSI in which a plurality of key devices were made into a system-on-chip 9 Internal signal connecting processor 1 and memory 2 10 Test terminal 1 11 Test Terminal 2 12 Test terminal 3 13 Test terminal 4 14 Internal signal 0 15 Internal signal 1 16 Internal signal 2 17 8: 1 selector 18 8: 1 selector 19 8: 1 selector 20 Selection signal SEL0-SEL2 21 Conventional internal signal observation means ISO 22 Basic configuration of internal signal observing device 23 Internal signal that may output a signal in silicon and observe it 24 Data capture unit that acquires internal signal by sampling clock 25 Internal information after capture 26 Selection means 27 Test terminal 28 Preset Counter 29 Select signal for controlling select terminal of selection means 30 Preset counter source clock CLK 31 Preset counter overflow terminal OVR 32 Flip-flop 33 Flip-flop 34 Flip-flop 35 Flip-flop 36 Sampling timing 37 Sampling timing 38 Sampling timing 39 Signal 0 Edge detection circuit that detects that there has been a change in signal 40 edge detection circuit that detects that there has been a change in signal 1 41 edge detection circuit that detects that there has been a change in signal 2 42 a change in signal 3 Edge detection circuit 43 for detecting the presence of a signal 43 Mask gate for signal 0 44 Mask gate for signal 1 45 Mask gate for signal 2 46 Mask gate for signal 3 47 Mask signal S for mask gate _00 48 Mask gate mask signal S_01 49 Mask gate mask signal S_10 50 Mask gate mask signal S_11 51 Latch timing at change point of signal 2 52 Latch timing at change point of signal 1 53 Change point of signal 1 and 3 Latch timing at the transition point of signal 2 55 latch timing at the transition point of signal 3 56 latch timing at the transition point of signal 1 57 latch timing at the transition point of signal 0 58 Register SR0 59 which is selected when the output is 0 Register SR1 60 which is selected when the output of the preset counter is 1 Register SR2 61 which is selected when the output of the preset counter is 2 Register SR3 62 which is selected when the output of the preset counter is 3 At the point of change Latch timing 63 at the transition point of signal 1 64 Latch timing at the transition point of signal 3 65 Latch timing at the transition point of signal 3 66 Latch timing at the transition point of signal 3 427 Output result of test terminal by sampling means 428 Output timing of preset counter 429 Select input timing of selection means 430 Input clock of source clock of preset counter 431 Output timing of overflow of preset counter 627 Output result of test terminal when edge detection means is incorporated 628 Output timing of preset counter 629 Select input timing of selection means 630 Input timing of source clock of preset counter 631 Output timing of overflow of preset counter 648 Timing of mask signal S_01 of mask gate 827 Output result of test terminal when observation signal combination means SRn is incorporated 828 Output timing of preset counter 829 Select input timing of selection means 830 Input clock of source clock of preset counter 831 Preset counter Output timing 848 timing of the mask signal S_01 of the mask gate 850 timing of the mask signal S_11 of the mask gate 2230 signal 0 input terminal 2231 signal 1 input terminal 2232 signal 2 input terminal 2233 signal 3 input terminal 4230 input timing of signal 0 4231 Input timing of signal 1 4232 Input timing of signal 2 4233 Input timing of signal 3 6230 Input timing of signal 0 6231 input timing of the input timing 8233 signal 3 of the input timing 8231 signal 1 input timing 6233 signal 3 of the input timing 6232 signal 2 signal 1

Claims (3)

[Claims] 1. A limited number of test circuits having a data capture section, a signal selection means, a preset counter, a counter overflow terminal, and an output terminal, and capturing a plurality of internal signals with a sampling clock and then time-divisionally outputting the signals. An internal signal observation device characterized by outputting a lot of internal information from terminals. 2. The apparatus according to claim 1, further comprising an edge detector and a synchronizing circuit or a process for masking information update during data output, thereby providing information update to the outside with priority. 2. The internal signal observation device according to claim 1, wherein data is output. 3. An order for outputting to the outside by providing the internal signal observing device according to claim 1 or 2 and having a data holding means capable of freely setting the selection order of the signal selecting means. An internal signal observation device comprising an observation signal combination means capable of changing a combination.