JPS6342485A - Multiple-scan test system - Google Patents

Abstract

PURPOSE:To finish a function test within a short time even when the number of gates increases by providing an output to be connected to a scan test input of each scan chain of a body to be tested. CONSTITUTION:Respective bits of respective scan-in data outputted by a scan-in data storage device 12 are propagated through respective logic circuits of corresponding scan chains of the body 10 to be tested with scan clock pulses of a scan clock generator 14 which are gated out with scan chain selection pulses corresponding to respective scan test data bits from a scan chain selecting device 16. Respective tests output data corresponding to the scan data bits inputted to the body 10 to be tested are outputted to corresponding scan test outputs, and their test output data bits are supplied to a comparator 24 through a selector 20. At the same time, scan-out bits corresponding to the test output data bits are supplied from a scan-out data storage device 22 to the comparator 24 and both of them are compared with each other.

Description

[Detailed Description of the Invention] [↑Required] The scan data of each scan chain of the test object is applied bit serially to the scan test input in a time-division manner, and the bit serial output from each scan test output is tested. The test time, which increases as the number of scan gates of the test object increases, is shortened by comparing the output data and the corresponding bit serial scan-out data in a time-division manner while maintaining their correspondence.

[Industrial application field]

The present invention relates to a multiple scan test system, and more particularly, to a multiple scan test system in which a scan test object of a test object is divided into several divisible groups and parallel scan tests are performed on these groups. .

Information processing devices, etc. are constructed using multiple LSI mounting boards, but these boards are
It is necessary to test whether the semiconductor logic circuit system formed in I operates as designed. As the number of logic circuits to be tested increases, the test time increases accordingly, which does not meet the demand for completing the test in a short period of time.

[Prior Art] As a conventional system for performing the above-mentioned test, there is a scan test system. This system prepares the logic design of the device under test, scan-in data and scan-out data obtained from its simulation, and then applies the scan-in data to all the logic circuits of the device under test manufactured in a bit-serial manner. The test object is tested by comparing the test output data that is propagated through the scan test output (see FIG. 6) and scan out data that has been prepared in advance.

[Problem that the invention seeks to solve]

As mentioned above, this conventional scan test system connects all the logic circuits formed therein in series during testing, regardless of the number of logic circuits (gates) formed on the device under test. Since the test is performed by sending the scan-in data prepared as described above from the input input bit serially, the more gates are formed on the device under test, the longer the test takes. This results in a long period of time.

The present invention was created in view of such problems, and an object of the present invention is to provide a multiple scan test system that can complete a faction test in a short time even when the number of gates increases. .

[Means for solving problems]

FIG. 1 shows a block diagram of the principle of the present invention. As shown in the figure, the present invention has an output 12A for connecting to the scan test input (Si1...5tN) for each scan chain of the device under test 10, and transmits data bits for each scan chain to the output. A scan-in data storage device 12 that can output bits serially, and a scan clock that outputs scan clock pulses synchronized with the serial bits.

a scan chain selection device 16 that generates a scan chain selection pulse, and an input connected to the output of the scan clock generator 14 and the scan chain selection Hals output (Sl...SN) corresponding to each scan chain. and an AND gate 181 for each scan chain having an output connected to the corresponding scan clock input (CLK1 to CLKN) of the device under test.
18N, and each scan test output S of the test object.
a selector 20 connected to ol...SoN and outputting corresponding test output data in response to a scan chain selection pulse corresponding to each of the scan chains;
a scan-out data storage device 22 that outputs scan-out data corresponding to each of the scan chains in a bit-serial manner in synchronization with the serial bits output from the scan-in data storage device 12; This is a multiple scan test system comprising a comparator 24 for comparing serial test output data.

[Operation] Each bit of each scan-in data that is output bit-serially from the scan-in data storage device 12 when the system of the present invention starts operating is connected to a scan chain corresponding to each scan test data bit from the scan chain selection device 16. The scan clock pulse of the scan clock generator is gated out via the corresponding AND gate by the selection pulse, and is propagated through each logic circuit of the corresponding scan test logic circuit system (scan chain) of the device under test. go. That is, each separate scan test data bit is fed sequentially into a corresponding scan chain in a time-shared manner.

In this way, each separate test output data as a response result to the scan data bits input to the test object is output bit-serial to the corresponding scan test output. Each test output data bit is applied to a comparator 24 via a selector 20. At the same time, the scan-out bit corresponding to the test output data bit is provided from the scan-out data storage device 22 to the comparator 24 and compared with the test output data bit from the selector 20.

In this way, each scan chain of the test object is tested in parallel with a one-scan crotch shift in time series, so the test can be completed in a short time.

〔Example〕

FIG. 2 shows an embodiment of the invention. This embodiment shows a configuration example of a multiple scan test system in which a scan test object of a test object 10 can be divided into four scan chains. Therefore, the DUT 10 has four scan-in inputs, four scan clock inputs, and four scan-out outputs (i.e., Sil to Si4. CLKI to CL
K4 and Sol~5o4), each of which corresponds to each scan chain. Each scan-in input Sil to Si4 has a scan-in data memory 12'.
output is connected. This memory 12° contains the third
The scan-in data is stored bit-serial in the manner shown in the figure, and these bits are sequentially read out using the count value of the address counter 26, which is counted up by the clock pulse output from the scan clock generator 14. It has become. Then, each bit corresponding to the scan chain read out in this way (see Figure 5) is converted to the scan clock CLKi (i=
1 to 4) are sequentially inputted by the clock pulse of the scan clock generator 14 sent through the AND gate 18+ (i-1 to 4).

These AND gates 18i are scan chain selection pulses (bit gate pulses) Si (i=
1 to 4), it operates to output the clock pulse of the scan clock generator 14.

As described above, the test output data pits (see FIG. 5) of each scan chain as a response result to the scan-in data sequentially input to each scan chain of the test object 10 are controlled by the above-mentioned signal Si. It is selectively outputted via the selector 20 located below and applied to the comparator 24.

Corresponding scan-out data (expected data and conveyor mask data) is output from the scan-out data memory 22'. This output function is
2 stores the scan out data in exactly the same manner as in FIG. It becomes possible.

In this way, in the comparator 24, the same conventional checks for each scan chain can be performed in parallel with a one scan clock shift in time series, so the scan test of the entire test object can be performed in a short time. It will be possible to complete it.

Details of the gate pulse generation circuit 16 that generates the bit gate pulse (scan chain selection pulse) Si that enables such a scan test will be explained in conjunction with a detailed diagram of the scan chain selector 30 in FIG. 4. .

The details of the scan chain selector 30 are shown in FIG. Bit gate pulses Si continue to be generated sequentially in a cyclic manner. For this purpose, the D-latch 16i1. A NOR gate 16iz, an inverter 16i3 and an AND gate 16i,s are provided, and in addition to being connected in a cascade format in which the Q output of the D-latch in the previous stage is connected to the D input of the D-latch in the next stage.
-Latch 161. A set input is connected to the input S of the D-latch 1641, and a Q output of the D-latch 1641 is connected to the D input as a feed bank. Also, each D-latch 1611
is the clock pulse CLK of the scan clock generator 14
and D-latch 161 . AND gate 161 responsive to the Q output of and the output of inverter 1613
A scan chain selection pulse Si is generated from 4.

A signal CC for counting the length of each scan chain is generated from an AND gate 32 receiving the Q output of the D-latch 1614 and a clock pulse CLK, and a current scan latch number counter 34 receiving this signal CC generates a signal CC for counting the length of each scan chain. Produces an up movement. The count value of this counter 34 is constantly updated to the scan latch number register 38 by the conveyor and latch circuit 36i (i=1 to 4).
i (i=1 to 4), and when there is a match between them, the above-mentioned signal Ci is generated.

When this signal is generated, the corresponding D-latch 161 becomes through, and the scan test of the next scan chain is immediately started i4. In other words, there is no need to interpolate dummy data as shown in Figure 3.
(See t in the figure). This has the effect of reducing the required memory capacity.

Note that this scan chain selection circuit is just one example, and other configurations may be adopted.

〔Effect of the invention〕

As described above, according to the present invention, even if the number of scan test target circuits of the test object increases, the test time for the entire test object can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle of the present invention. FIG. 2 is a diagram showing an embodiment of the present invention. FIG. 3 is a diagram showing an example of how scan-in data is stored. FIG. 4 is a detailed diagram of the scan chain selector. , FIG. 5 is an explanatory diagram of a scan test aspect of the present invention, and FIG. 6 is an explanatory diagram of a conventional scan test aspect. 1 and 2, 10 is a test object, 12 is a scan-in data storage device, 12' is a scan-in data memory, 14 is a scan clock generator, 16 is a scan chain selection device, and 181 to 18N are ANDs. 20 is a selector, 22 is a scan-out data storage device, 22' is a scan-out data memory, and 24 is a comparator. Chain l 5cQn LOtch num
berl-Ch, 2SLI→Ch, 3sLI →Ch
, 4SLl → Ch, 1SL2 → Ch, 2SL2 →
Ch, 3SL2 → Ch, 4Si2 →------
→Ch, 1SLn -0Ch, 3SLn---C
h, 4SLn→−−−−+Ch, ISLm−m↑ Ch, 4SLm −=−−−Ch,! SLk
-Ch, l5Lk++ Scan index - Evening tree 4,000 gates sad, 1st row Figure 3

Claims (1)

[Claims] An output (
12A) and capable of outputting data bits for each scan chain bit-serially at its output; and a scan clock generator outputting scan clock pulses synchronized with the serial bits. (14), a scan chain selection device (16) that generates a scan chain selection pulse, and an output of the scan clock generator (14) and a scan chain selection pulse output (S) corresponding to each scan chain.
1...SN) and the corresponding scan clock inputs (CLK1 to CLKN) of the device under test.
AND gates 18_1...18_N for each scan chain having outputs connected to the respective scan test outputs So1...
a selector (20) connected to the SoN and outputting corresponding test output data in response to scan chain selection pulses corresponding to each of the scan chains; and a serial bit output from the scan-in data storage device (12). a scan-out data storage device (22) that outputs scan-out data corresponding to each of the scan chains in a bit-serial manner in synchronization with the bit-serial scan-out data; and a comparator that compares the bit-serial scan-out data with the bit-serial test output data. (24) A multiple scan test system comprising: