JP2509685B2 - Logic circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention particularly relates to a large-scale logic circuit device integrated into an IC (integrated circuit).

(Prior Art) Generally, in a large-scale logic circuit device, especially in an LSI, in order to test the device, for example, Kikuchi “CMOS gate array with automatic diagnostic function”, magazine “Electronic Materials”, 1
A method called a scan path as described in July 986, p.92-97. May be applied. This scan path method (hereinafter referred to as scan design method)
The shift register realizes the function of setting arbitrary data from the outside (scan-in) and the function of outputting the data to the outside (scan-out) to the storage element in the logic circuit device by using the shift register. This is a method of testing the logic circuit device by scanning in, then scanning out, and comparing with a predetermined expected value. In the scan design method, transmission of scan data between each storage element is generally performed by connecting all storage elements serially or by dividing into several blocks and connecting them serially. is there.

Now, the scan design method is generally used for testing a logic circuit device. However, it is also possible to use this method during system operation and monitor the state of the logic circuit device during system operation. In this case, the data in the storage element is used for external sampling while repeating scan-in and scan-out for each system cycle.

(Problems to be Solved by the Invention) As described above, it is conceivable to use the scan design method for monitoring the internal state of the logic circuit device during system operation. However, the conventional scan design method is used for the logic circuit device. Since the data of the storage element in the inside is sampled, especially in the case of a large-scale logic circuit device, a huge amount of data must be sampled although the storage element to be monitored is limited. In addition, since there is a huge amount of data, there is a problem that a large amount of time is required for each sampling.

Therefore, the problem to be solved by the present invention is to selectively take out only the data of an arbitrary storage element in the logic circuit device while utilizing the scan design method,
This allows efficient sampling during system operation,
Moreover, the test of the logic circuit device using the scan design method can be performed as usual.

[Structure of the Invention] (Means for Solving the Problem) The present invention provides a logic circuit device including a logic circuit including a plurality of storage elements having a scan function and capable of forming a scan path. Selectors provided correspondingly, which select shift-in data to the corresponding storage element or shift-out data from the same storage element as shift-in data for the storage element in the next stage, and data from the outside. A serial input parallel output shift register that can be set, in which each bit of parallel output data corresponds to the selector in a one-to-one correspondence, and a shift register used as a selection signal of the corresponding selector and a memory corresponding to the selector. The same applies during the period when the shift-in data to the element is selected as the shift-in data to the storage element in the next stage. It is characterized in that a gate for inhibiting a clock input for setting the shift-in data element.

(Operation) According to the above configuration, when the logic circuit is tested, the data for selecting the shift-out data from the corresponding storage elements by all selectors as the shift-in data for the storage element of the next stage is set in the shift register. By doing so, a scan path in which all storage elements in the logic circuit are serially connected is formed, and a normal scan test for all storage elements can be performed. On the other hand, by setting the data for selecting the shift-out data from the corresponding storage element as the shift-in data for the next-stage storage element in the shift register, only the arbitrary selector of all the selectors corresponds to this selector. It is possible to form a scan path in which only the storage elements in the logic circuit to be connected are serially connected, and the shift-in data setting operation in the storage elements removed from the scan path is prohibited by the corresponding gate, and the original data Since the holding operation is performed, only the state of any storage element during the system operation can be correctly sampled through the scan path formed at that time.

(Embodiment) FIG. 1 is a block diagram showing a part of a logic circuit device according to an embodiment of the present invention. The logic circuit device of FIG. 1 is, for example, a gate array, 11 is a logic circuit,
Reference numeral 12 is a memory element included in the logic circuit 11, and 13 is a combinational circuit included in the logic circuit 11. The storage element 12 is a flip-flop having a scan function (flip-flop having a scan function), and has a data input terminal D, a clock terminal C, a non-inverting output terminal Q, and an inverting output terminal like the D-type flip-flop. In addition, four terminals used during scan operation, namely, data input terminal (shift data in port) SI during scan operation, data output terminal (shift data out port) during scan operation
Clock terminals A and B to which a two-phase clock (scan clock) for shifting the data in SO and storage element 12 is input
Have. This memory element 12 is D when the inputs of terminals A and B are fixed at, for example, "H" level (high level).
Type flip-flops. Also storage element 12
Functions as a scan flip-flop that shifts data in accordance with the clocks input to the terminals A and B when the input to the terminal C is fixed at, for example, "H" level. That is, in the memory element 12, the input at the terminal C is "H".
In this case, when a valid clock (negative pulse in this case) is input to the terminal A, the data input to the terminal SI appears at the terminal Q (that is, Q = SI), and the valid data is input to the terminal B. When a clock (here, positive pulse) is input, terminal Q
The data appearing at the terminal appears at the terminal SO. The terminal D of the storage element 12 is connected to the output of the combination circuit 13, and the terminal Q of the storage element 12 is connected to the input of another combination circuit 13.

14 is a shift register for designating a storage element to be scanned among the storage elements 12, 15 is a storage element provided corresponding to the storage element 12, and 16 is a plurality of storage elements 15 connected in series and in multiple stages. A serial chain (hereinafter referred to as a data path 16) for configuring the shift register 14.
The storage element 15 includes a data input terminal SI, a data output terminal SO,
It has clock terminals A and B to which a two-phase clock (shift clock) for shifting the data of the storage element 15 is input. The terminal SO of the storage element 15 is connected to the terminal SI of the storage element 15 of the next stage by the data path 16. 17 is a memory element
An input data path which is provided corresponding to 12 and which transfers the scan-in data from the outside to the corresponding terminal SI of the storage element 12 or the output data from the terminal SO of the storage element 12 of the previous stage (or earlier). , 18 are provided corresponding to the storage element 12, and output data from the corresponding terminal SO of the storage element 12 is connected to the terminal of the storage element 12 of the next stage (or later).
Output data path for transferring as input data to SI or scan-out data to the outside, 19 is storage element 15
And a selector provided corresponding to the storage element 12 similarly to the data paths 17 and 18. The selector 19 receives data guided to the terminal SI of the corresponding storage element 12 via the data path 17 or the data from the terminal SO of the corresponding storage element 12 to the data path 18.
One of the data output to the terminal SI of the storage element 12 of the next stage according to the state of the terminal SO of the corresponding storage element 15
It is designed to be selected as input data to or scan-out data to the outside.

Reference numeral 21 is a system clock line used for transferring a system clock, 22 _A and 22 _B are scan clock lines used for transferring a clock (scan clock) necessary for data shift (scan operation) of the storage element 12, 23 _A , 23 _B is a memory element 15
Is a shift clock line used for transferring a clock (shift clock) necessary for the data shift of. 24 _A and 24 _B are provided corresponding to the storage elements 12 and 15, and the scan clock line 2
An AND gate that outputs the scan clocks (A scan clock, B scan clock) on 2 _A and 22 _{B to} the terminals A and B of the corresponding storage element 12 according to the state of the terminal SO of the corresponding storage element 15. .

Next, the operation of the configuration shown in FIG. 1 will be described. In the configuration shown in FIG. 1, a first operation of performing a scan-in and a scan-out using all the storage elements 12 of the logic circuit 11 by a scan design method to test the logic circuit 11 and a logic circuit during system operation Secondly, the internal state of an arbitrary portion of the logic circuit 11 during system operation is monitored by selectively setting 11 arbitrary storage elements 12 as a scan target and taking out the data of the storage elements 12 to the outside by a scan design method. Two basic operations are prepared.

First, the first operation will be described. When performing the first operation, first, the shift register 14 is configured, and the logical "1" data is set in all the storage elements 12 provided corresponding to each storage element 15 in the logic circuit 11. This data set, provides a logic "1" data from the outside to the data path 16, respectively whereas the effective two-phase shift clock to the shift clock line 23 _A, 23 _B in this state (A shift clock),
This is performed by repeatedly supplying the other (B shift clock) for the number of storage elements 15 (that is, by performing the shift operation for the number of storage elements 15 configuring the shift register 14). When the logical "1" data is set in each storage element 15 that constitutes the shift register 14, the state of the terminal SO (SO output) becomes the logical "1". Each selector 19 has a corresponding storage element 15
When the SO output is logic “1”, the SO output of the corresponding storage element 12 is selected. As a result, all storage elements 12 in the logic circuit 11 are
A so-called scan path is formed by connecting in series in multiple stages. In addition, the SO of the storage element 15 that constitutes the shift register 14
When the output becomes logic "1", the corresponding AND gate 24 _A , 24
_B is an output Ready state, and outputs a scan clock (A scan clock, B scan clock) from the scan clock line 22 _A, 22 _B as it is terminal A of the corresponding storage element 12, the B. This state is the selector 19, AND gate 24 _A , 24
_This is the same as the state of the conventional scan design circuit having no _B (and the shift register 14), and its operation has already been described in the section “Prior Art”, and therefore will be omitted here.

Next, the second operation will be described. When performing the second operation, first, of all the memory elements 15 configuring the shift register 14, the logic circuit to be the scan target
Only the memory element 12 corresponding to the memory element 15 in 11 has the logic "1".
Data is set, and logical "0" is set to the other storage elements 12.
Set the data. This data set sequentially gives a sequence of data (serial data) to be set in each storage element 15 in the shift register 14 to the data path 16 from the outside, and is effective to the shift clock lines 23 _A and 23 _B in synchronization with this. It is performed by repeatedly supplying one (A shift clock) and the other (B shift clock) of the two two-phase shift clocks by the number of storage elements 15.

According to the above data set, the selector 19 corresponding to the storage element 15 in which the logical “1” data is set selects the SO output of the corresponding storage element 12 in the same manner as in the first operation described above, and selects the logical “1”. "The AND gates 24 _A and 24 _B corresponding to the storage element 15 in which the data is set are in the output enable state. On the other hand, unlike the first operation described above, the selector 19 corresponding to the storage element 15 in which the logical “0” data is set selects the SI input of the corresponding storage element 12, and selects the logical “0” data. AND gates 24 _A and 24 _B corresponding to the storage element 15 in which is set
Is in the output prohibited state. As a result, among all the storage elements 15 configuring the shift register 14, only the storage element 12 corresponding to the storage element 15 in which the logical “1” data is set forms the actual scan path. In addition, in the storage element 12 removed from this scan path (the storage element 12 corresponding to the storage element 15 in which logical "0" data is set), its terminal
Since the AND gates 24 _A and 24 _B prohibit the input of the scan clocks from the scan clock lines 22 _A and 22 _B to _A and _B , (the data held by the scan clock cannot be changed. Instead, the original data determined by the D input contents is held.

Now, the storage element 15 in the shift register 14 corresponding to the storage element 12 to be scanned in the logic circuit 11
In, setting the selective logic "1" data as described above, respectively whereas the shift clock line 23 _A, 23 valid two-phase shift clock _B (A shift clock), the other (B
The shift clock) is repeatedly supplied by the number of storage elements 15 in which logical "1" data is set,
The operation for scanning out the held data (Q output data) is performed. In this scan-out operation, the B scan clock is applied to the scan clock line 22 _B , the Q output of the memory element 12 to be scanned is taken out as the SO output, and then the A scan clock is applied to the scan clock line 22 _A to take out the above. The operation of taking in the SO output from the terminal SI of the memory element 12 of the next stage on the scan path and taking it out to the terminal Q of the memory element 12 of the next stage is performed by the number of the memory elements 15 to which the logical "1" data is set. It is done by repeating only. Then, during this scan-out period, by sequentially sampling the SO output from the storage element 12 forming the final stage on the scan path, the data holding state of each scan target storage element 12 at any timing during system operation. Can be detected.

Now, in this embodiment, the SO output (scan-out data) from the storage element 12 forming the final stage on the scan path is returned to the terminal SI of the storage element 12 forming the first stage on the same scan path to scan in. Eventually, when the last scan-out data from the final-stage storage element 12 on the scan path is scanned in to the first-stage storage element 12, the storage element 12 on the scan path (the storage element to which the logical “1” data is set) The state of the storage element 12) corresponding to 15 returns to the state before the series of scan (shift) operations described above. This series of scan operations is performed during the period when the system clock is not newly generated. Then, after a series of scan operations, the next system clock is generated by one clock (and then applied to the system clock line 21), so that the logic circuit 11 performs a new system operation. The second operation is performed by performing the system operation while alternately repeating the scan-out and scan-out data sampling by the generation of the scan clock and the generation of the system clock.

[Effects of the Invention] As described in detail above, according to the present invention, among a large number of storage elements in a logic circuit device, a storage element targeted for scan-in or scan-out is arbitrarily set by setting data to a shift register. Since the data of this designated storage element can be externally extracted by using the scan design method, sampling during system operation can be performed efficiently in a short time, and hardware for large-scale logic circuit devices can be used. It is extremely effective for wear debugging, troubleshooting, performance evaluation, etc. Further, according to the present invention, the test of the logic circuit device using the scan design method can be performed as usual by only changing the setting data in the shift register.

[Brief description of drawings]

FIG. 1 is a block diagram showing a part of a logic circuit device according to an embodiment of the present invention. 11 …… Logic circuit, 12 …… Memory element, 14 …… Shift register, 19 …… Selector, 21 …… System clock line, 22 _A ,
22 _B …… Scan clock line, 23 _A , 23 _B …… Shift clock line, 24 _A , 24 _B …… AND gate.

Claims (1)

(57) [Claims] 1. A logic circuit device comprising a logic circuit including a plurality of storage elements having a scan function and capable of forming a scan path, wherein each of the storage elements is provided in correspondence with each of the storage elements. A selector for selecting the shift-in data or the shift-out data from the same storage element as the shift-in data for the storage element in the next stage, and a serial input parallel output shift register capable of external data setting Each bit of data corresponds to the selector on a one-to-one basis, and a shift register used as a selection signal of the corresponding selector and shift-in data to the storage element corresponding to the selector are shifted to the storage element of the next stage. The above shift-in data is set in the same memory element during the period selected as the in-data. A gate for inhibiting clock input for selecting the shift-out data from the storage elements corresponding to all the selectors as shift-in data for the storage element of the next stage at the time of testing the logic circuit. When data is set in the shift register and the state of any storage element in the logic circuit is sampled during system operation, only the selector corresponding to the storage element outputs the shift-out data from the storage element. A logic circuit device characterized in that data for selecting as shift-in data for a storage element of a next stage is set in the shift register.