JPH02201275A - Logic circuit device - Google Patents

Abstract

PURPOSE:To efficiently conduct sampling in the course of a system operation by setting in a shift register the data for selecting shift-out data from a storage element as shift-in data for another storage element of the succeeding stage. CONSTITUTION:A test of a logic circuit 11 is conducted by executing scan-in and scan-out by using all storage elements 12 of said logic circuit 11 according to a scan design system. Besides, an arbitrary one of the storage elements 12 of the logic circuit 11 in the course of a system operation is selected and set as an object of scan, the data in said storage element 12 are taken outside according to the scan design system, and thereby the internal state of any part of the logic circuit 11 in the course of the system operation is monitored. These two basic operations are prepared.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention particularly relates to a large-scale logic circuit device formed into an IC (integrated circuit).

(Prior Art) In general, in large-scale logic circuit devices, especially in LSI, in order to test the device, for example, Kikuchi, "CMOS Gate Array with Built-in Automatic Diagnosis Function," Magazine R Electronic Materials J, 19813, 7. Month.

9.92-97. In some cases, a method called a scan path as described in . This scan path method (hereinafter referred to as scan design method) is
The function of setting arbitrary data from the outside to the memory element in the logic circuit device (scan-in) and the function of outputting that data to the outside (scan-out) are realized using a shift register, and arbitrary data can be scanned in. This is a method of testing the logic circuit device by scanning it out and comparing it with a predetermined expected value. In the scan design method, scan data is generally transmitted between each memory element by connecting all memory elements serially, or by dividing the blocks into several blocks and connecting them serially. be.

Now, the scan design method is generally used to test logic circuit devices.

However, it is also conceivable to use this method during system operation to monitor the state of the logic circuit device during system operation. In this case, data in the storage element is sampled externally while repeating scan-in and scan-out every system cycle.

(Problems to be Solved by the Invention) As mentioned above, it is conceivable to use the scan design method to monitor the internal state of a logic circuit device during system operation. Especially in the case of large-scale logic circuit devices, it is necessary to sample a huge amount of data even though the number of storage elements to be monitored is limited. Moreover, since the amount of data is huge, there is a problem that it takes a lot of time for each sampling.

Therefore, the problem to be solved by this invention is that it is possible to selectively retrieve only the data of an arbitrary memory element in a logic circuit device to the outside while using the scan design method, thereby making it possible to efficiently sample data during system operation. Moreover, it is possible to test logic circuit devices using the scan design method as before.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides a logic circuit device including a logic circuit including a plurality of memory elements having a scanning function and capable of forming scan paths. a selector provided correspondingly, which selects shift-in data to the corresponding storage element or shift-out data from the same storage element as shift-in data to the next-stage storage element; A configurable serial input parallel output shift register, in which each bit of parallel output data corresponds one-to-one to the selector, and a shift register used as a selection signal for the corresponding selector, and a memory to which the selector corresponds. and a gate that prohibits clock input for setting the shift-in data to the storage element during a period when the shift-in data to the element is selected as the shift-in data to the next-stage storage element. It is something to do.

(Function) According to the above configuration, when testing a logic circuit, all selectors set data in the shift register to select shift-out data from the corresponding storage element as shift-in data to the next stage storage element. By doing so, it is possible to form a scan path in which all the memory elements in the logic circuit are serially connected, and to perform a normal scan test targeting all the memory elements. On the other hand, by setting data in the shift register to select the shift-out data from the corresponding storage element as the shift-in data for the next stage storage element, only an arbitrary selector among all the selectors can correspond to this selector. Only memory elements in a logic circuit that can be serially connected can form a scan path, and the shift-in data setting operation for memory elements removed from the same scan path is prohibited by the corresponding gate, and the original data is Since the holding operation is performed, it is possible to correctly sample only the state of an arbitrary storage element during system operation via the scan path formed at that time.

(Embodiment) FIG. 1 is a block diagram showing a part of a logic circuit device according to an embodiment of the present invention.

The logic circuit device shown in FIG. 1 is, for example, a gate array.
1 is a logic circuit, 12 is a memory element included in the logic circuit 11, and 13 is a combinational circuit included in the logic circuit 11. The memory element 12 is a flip-flop with a scan function (a flip-flop with a scan function), and like a D-type flip-flop, it has a data input terminal and a clock terminal C.
In addition to the normal rotation output terminal Q and the inversion output terminal Q, there are four terminals used during scan operation, namely, a data input terminal during scan operation (shift data input terminal).
Port 1) Sl, data output terminal (shift data out port) during scan operation SO1 has clock terminals A and B to which a two-phase clock (scan clock) for shifting data of the storage element 12 is input. This memory element 12 functions as a D-type flip-flop when each input of terminals A and B is fixed at, for example, an "H" level (high level). Furthermore, when the input to the terminal C is fixed at the "H" level, the memory element 12 functions as a scan flip-flop that shifts data in accordance with the clocks input to the terminals A and B. That is, in the memory element 12, the input to the terminal C is "Ho".
In this case, when a valid lock (in this case a negative pulse) is input to terminal A, the data input to terminal SI appears at terminal Q (that is, it becomes Q-SI), and a valid lock is input to terminal B. (Here, a positive pulse) is input, the data appearing at terminal Q appears at terminal SO. A terminal of the memory element 12 is connected to an output of a combinational circuit 13, and terminals Q and 0 of the memory element 12 are connected to an input of another combinational circuit 13.

14 is a shift register for specifying a memory element to be scanned among the memory elements 12; 15 is a memory element 12;
A memory element 16 provided corresponding to the memory element 16 is a serial chain (hereinafter referred to as data bus 16) for configuring the shift register 14 by connecting a plurality of memory elements 15 in series in multiple stages. The memory element 15 has data input terminals Sl,
Data output terminal SO1 A clock terminal A to which a two-phase clock (shift clock) for shifting the data of the storage element 15 is input.

It has B. The terminal SO of the memory element 15 is connected to the data bus 1
It is connected to the terminal SI of the next stage storage element 15 by B. Reference numeral 17 is provided corresponding to the memory element 12 to transfer external scan-in data or output data from the terminal SO of the previous stage (or earlier) memory element 12 to the terminal SI of the corresponding memory element 12. An input data bus 18 is provided corresponding to the storage element 12, and inputs output data from the terminal SO of the corresponding storage element 12 to input data to the terminal SI of the next (or subsequent) storage element 12. An output data bus 19 for transferring scan-out data to the outside is a selector provided corresponding to the memory element 12, similar to the memory element 15 and data buses 17 and 18. The selector 19 selects either the data guided to the terminal SI of the corresponding memory element 12 via the data bus 17 or the data output from the terminal SO of the corresponding memory element 12 to the data bus 18.
Depending on the state of the terminal SO of the corresponding memory element 15, the data is selected as input data to the terminal Sl of the primary stage memory element 12 or as scan-out data to the outside.

21 is a system clock line used for transferring the system clock; 22A; 22B is a scan clock line necessary for data shifting (scanning operation) of the storage element 12 and used for transferring a lock (scan clock); 23A;
, 23B are shift clock lines necessary for data shifting of the storage element 15 and used for transferring a lock (shift clock). 24A, 24B are provided corresponding to the memory elements 12.15, and scan clock lines 22A, 2
The scan clocks (A scan clock, B scan clock) on 2B are connected to the terminal SO of the corresponding memory element 15.
This is an AND gate that outputs to the terminals A and B of the corresponding memory element 12 according to the state of the memory element 12.

Next, the operation of the configuration shown in FIG. 1 will be explained. In the configuration shown in FIG. 1, the first operation is to test the logic circuit 11 by performing scan-in and scan-out using all the memory elements 12 of the logic circuit 11 using the scan design method, and the first operation is to test the logic circuit 11 while the system is operating. The second system monitors the internal state of any part of the logic circuit 11 during system operation by selecting and setting an arbitrary memory element 12 of 11 as a scan target and extracting the data of the memory element 12 to the outside using the scan design method. There are two basic operations available:

First, the first operation will be explained. When performing the first operation, first, the shift register 14 is configured, and logical "1" data is set in all memory elements 12 provided corresponding to each memory element 15 in the logic circuit 11. This data set is applied to the data bus 1B from the outside as a logic “1”.
data is applied, and in this state shift clock lines 23^, 2
One of the two-phase shift clocks valid for 3B (A shift clock).

This is performed by repeatedly supplying the other (B shift clock) as many times as the number of storage elements 15 (that is, by performing a shift operation as many as the number of storage elements 15 forming the shift register 14). When logic "1" data is set in each storage element 15 constituting the shift register 14, the state of the terminal SO (So output) becomes logic "1". Each selector 19 is
When the SO ratio output logic of the corresponding memory element 15 is “1”,
The SO ratio output of the corresponding memory element 12 is selected. As a result, all memory elements in the logic circuit 11! 2 are connected in series in multiple stages to form a so-called scan path. Further, when the SO ratio output logic of the storage element 15 constituting the shift register 14 becomes "1", the corresponding AND gate 24A.

24B is enabled for output, and the scan clock line 22A
, 22B (A scan clock, B scan clock) are output as they are to the terminals A and B of the corresponding memory element 12. This state is similar to the state of a conventional scan design circuit that does not have the selector 19, analogues 24A, 24a (and shift register 14), and its operation has already been described in the section "Prior art". Therefore, it is omitted here.

Next, the second operation will be explained. When performing the second operation, first, among all the memory elements 15 constituting the shift register 14, only the memory element 12 corresponding to the memory element 15 in the logic circuit 11 to be scanned has a logic "1". Set data and other memory elements 12
Set logical mO° data to . This data set is made by sequentially supplying a column of data (serial data) to be set in each storage element 15 in the shift register 14 to the data bus 16 from the outside, and in synchronization with this, the shift clock line 2
3A.

Each one of the two-phase shift clocks (A
Shift clock) and the other (B shift clock) are repeatedly supplied as many times as there are memory elements 15.

According to the above data set, the selector 19 corresponding to the memory element 15 set with logic "1" data selects the SO ratio output of the corresponding memory element 12 in the same manner as in the first operation described above, and selects the SO ratio output of the corresponding memory element 12, and 'AND gate 24A corresponding to the memory element 15 in which data is set, 24. becomes ready for output. On the other hand, unlike the first operation described above, the selector 19 corresponding to the memory element 15 to which the logic "aO" data is set selects the SI large input of the corresponding memory element 12, and the logic "0" data is set to the selector 19. The AND gates 24A and 24B corresponding to the set memory elements 15 are prohibited from outputting.As a result, among all the memory elements 15 forming the shift register 14, the memory elements 15 to which logic "1" data has been set are disabled. Only the corresponding memory element 12 forms the actual scan path.Furthermore, in the memory element 12 removed from this scan path (the memory element 12 corresponding to the memory element 15 to which logical "0" data is set), , the scan clock line 22A is connected to its terminals A and H,
Since input of the scan clock from 22B is prohibited by AND gates 24A and 24B, the original data determined by the contents of the D input is held (the data held is not changed by the above scan clock). It will be in a state where it is

Now, when the logic "1m data is selectively set in the storage element 15 in the shift register 14 corresponding to the storage element 12 to be scanned in the logic circuit 11 as described above, the shift clock line 23A.

Each one of the two-phase shift clocks (A
shift clock), and the other (B shift clock) as logic “
1m data is repeatedly supplied as many times as the number of memory elements 15 set, and an operation is performed to scan out the data held in the memory element 12 to be scanned (Q output data). This scan-out operation is performed by applying a B scan clock to the scan clock line 22B to scan the storage element 1 to be scanned.
The Q output of 2 is taken out as the SO output, and then the A scan clock is applied to the scan clock line 22A, and the taken out SO output is sent to the next stage storage element 12 on the scan path.
This operation is performed by repeating the operation of taking in data from the terminal Sl of the memory element 12 and taking it out to the terminal Q of the memory element 12 at the next stage as many times as the number of memory elements 15 in which logic "1" data is set. During this scan-out period, by sequentially sampling the SO output from the memory element 12 forming the final stage on the scan path, the data retention state of each scan target memory element 12 at any timing during system operation is determined. can be detected.

Now, in this embodiment, the SO output (scanout data) from the storage element 12 forming the final stage on the scan path
is returned to the terminal S1 of the first-stage storage element 12 on the same scan path and scanned in. Eventually, when the last scan-out data from the final stage storage element 12 on the scan path is scanned in to the first stage storage element 12, the memory element 12 on the scan path (the storage element to which logical "1" data is set) is scanned into the first stage storage element 12. The state of the memory element 12) corresponding to number 15 returns to the state before the series of scan (shift) operations described above. This series of scan operations is performed during a period when no new system clock is generated. Then, after a series of scan operations, one clock of the next system clock is generated (and applied to the system clock line 21), whereby a new system operation is performed in the logic circuit 11. The above-described second operation is performed by performing the system operation while alternately repeating the scan-out and sampling of scan-out data by generating the scan clock and the generation of the system clock.

[Effects of the Invention] As detailed above, according to the present invention, a memory element to be scanned in or scanned out from among a large number of memory elements in a logic circuit device can be arbitrarily selected by setting data to a shift register. Since only the data in the specified memory element can be retrieved externally using the scan design method, sampling during system operation can be performed quickly and efficiently, making it easier to use hardware for larger scale logic circuit devices. This is extremely effective for software debugging, troubleshooting, performance evaluation, etc. Further, according to the present invention, testing of logic circuit devices using the scan design method can be performed as before by simply changing the setting data to the shift register.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a part of a logic circuit device according to an embodiment of the present invention. If...Logic circuit, 12-...Storage element, 14...
Shift register, 19... Selector, 21... System clock line, 22A, 22B... Scan clock line, 23^, 23B... Shift clock line, 2
4A, 24B...and gate. Applicant's agent Patent attorney Takehiko Suzue

Claims (1)

[Scope of Claims] A logic circuit device including a logic circuit including a plurality of memory elements having a scan function and capable of forming scan paths, wherein each of the memory elements is provided corresponding to each of the memory elements, and the corresponding memory element is provided in correspondence with each of the memory elements. A selector that selects shift-in data to or shift-out data from the same storage element as shift-in data to the next stage of the storage element, and a serial input parallel output shift register that allows data to be set from the outside. Each bit of the output data corresponds to the selector on a one-to-one basis, and the shift register is used as a selection signal for the corresponding selector, and the selector transfers the shift-in data to the corresponding storage element to the next stage storage element. and a gate that prohibits clock input for setting the shift-in data to the memory element during a period selected as shift-in data, and when testing the logic circuit, all of the selectors correspond to the memory. When data for selecting shift-out data from an element as shift-in data for the next stage storage element is set in the shift register, and the state of any storage element in the logic circuit is sampled during system operation. is characterized in that only the selector corresponding to the same memory element sets data for selecting shift-out data from the same memory element as shift-in data for the next stage memory element in the shift register. logic circuit device.