JP2000090700A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device which assures less amount of overhead of circuit, reduces external terminals led out as the test terminals of a RAM, prevents increase of chip size and improves wiring capability. SOLUTION: This semiconductor integrated circuit device is provided with a first shift register 3-2 to give a serial data including address and input data to a plurality of address terminals and a plurality of input signal terminals of a semiconductor storage device 4, a second shift register 3-3 to convert the data output from a plurality of output signal terminals of the semiconductor storage device 4 to the serial data, a bit/word size judging circuit 5 to measure the number of address terminals and input data signal terminals from the input clock signal and a control means to control the write and read operation of the semiconductor storage device 4 from the serial input signal and bit/word size judging circuit 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device in which a general-purpose logic circuit and a semiconductor memory device (hereinafter, referred to as a RAM) are mixed, and in particular, a test of a RAM built in the semiconductor integrated circuit device. Circuit configuration for

[0002]

2. Description of the Related Art Conventionally, in an integrated circuit in which a general-purpose logic circuit and a RAM are mixedly mounted, to perform a unit test of the RAM, a method using a self-test circuit by a built-in self test (hereinafter, referred to as BIST) and a method of using a RAM. There is a method in which a test terminal is directly pulled out to perform a test.

FIGS. 4 and 5 show a method of testing a RAM using a conventional self-test circuit. FIG. 4 is a block diagram showing a method for testing a RAM using a conventional self-test circuit. FIG. 5 shows an example of a test pattern used when performing the RAM test method shown in FIG.
(A) is an input signal to the BIST circuit given from the input terminal of FIG. 4, (b) is an output signal of a test output terminal when the RAM operates normally, and (c) is a RAM.
Is the output signal of the test output terminal when the device has failed.

[0004] A semiconductor integrated circuit device 100 as shown in FIG. 4 is used in a conventional RAM test method using a self-test circuit. This semiconductor integrated circuit device 100
Are input terminal 101, input buffer 102, BIST circuit, RAM 104, output terminal 106, and output buffer 1
05.

An input terminal 101 is connected to a BIST circuit 103 via an input buffer 102,
3 and the RAM 104 are connected by an input / output bus 104-3. Further, the BIST circuit 103 includes an output buffer 105
Is connected to the output terminal 106 via the.

If there is no failure in a specific address or data in the RAM 104, the BIST circuit 103 synchronizes with the input signal as shown in FIG. Continue to output a constant output signal.
Only when a failure occurs at a specific address or data of the RAM 104, the BIST circuit 103 outputs a signal having a logic different from a normal output signal at a certain time, as shown in FIG. Make up. The identification of the address and data of the RAM 104 in which a failure has occurred can be calculated from the number of input data and the bit / word configuration of the RAM 104 to be tested.

Next, FIG. 6 shows a method of performing a test by directly pulling out a test terminal of a conventional RAM to the outside. FIG.
FIG. 3 is a block diagram showing a method for testing a RAM by directly pulling out a test terminal of the conventional RAM to the outside.
Pull out the test terminal of the conventional RAM directly to the outside and
A semiconductor integrated circuit device 110 as shown in FIG. 6 is used for a method of performing an AM test. The semiconductor integrated circuit device 110 includes a test input terminal 111, input / output buffers 112 and 116, a test switching terminal 113, and a RAM 114.
, An output terminal 115, an input buffer 117, and a general-purpose logic circuit 118.

Test input terminals 111-1, 111-
, 111-n are connected to the RAM 1 via the first input / output block 112 comprising an input buffer or an input / output buffer.
., 115-n, which are connected to an input bus 114-4 dedicated to the test and test output terminals 115-1, 115-2,.
Are connected to a test-only output bus 114-2 of the RAM 114 via a second input / output block 116 composed of an output or input / output buffer.

First and second input / output blocks 112 and 11
6 is connected to the general-purpose logic circuit 118. Further, the test switching terminal 113 is connected to the first and second input / output blocks 112 and 116 and R via the input buffer 117.
AM 114.

When the RAM 114 is to be tested, the test switching terminal 113 is set to a specific logic, and all signals input from the test input terminals 111-1, 111-2,. Is controlled to be output to the input bus 114-4.

Similarly, test output terminals 115-1 and 115-1
5-2,... 115-n are controlled so as to be input from the test-dedicated output bus 114-2. With such a configuration, a pattern for testing the RAM 114 is provided from the test input terminals 111-1, 111-2,... 111-n, and the output results are output to the test output terminals 115-1, 115-2. , ... 11
The test of the RAM 114 can be performed by observing from the 5-n.

When the test of the general-purpose logic circuit 118 is performed, the test switch terminal 113 is set to a logic different from the logic of the test of the RAM 114, so that the first and second test circuits are set.
The signals of the input / output blocks 112 and 116 are
18 to be transmitted. With such a configuration, the test of the RAM 114 mounted on the integrated circuit can be performed without increasing the number of tester terminals by sharing the input / output terminal and the test terminal of the normal logic circuit.

[0013]

However, in the conventional method using the self-test circuit, the BIST circuit requires an address generation, data generation, a BIST control signal, and an output determination circuit. Therefore, when a plurality of RAMs having different bits / words are mounted, it is necessary to mount a plurality of BIST circuits, so that the gate size of the BIST circuit increases and the overhead of the circuit increases.

On the other hand, in the conventional method of directly pulling out the test terminals of the RAM to the outside, it is necessary to take out almost all functional terminals of the RAM as test terminals to the outside. In addition to the increase in the degree, it is necessary to secure an area for wiring, and there is a problem that the chip size increases. Further, as the word size / bit size of the RAM increases, the number of bit terminals and data terminals of the RAM increases, so that the number of external terminals increases, and there is a problem that the wiring property deteriorates.

SUMMARY OF THE INVENTION The present invention has been made in view of such a problem, and has a small circuit overhead and a small RAM.
It is an object of the present invention to provide a semiconductor integrated circuit device capable of reducing external terminals to be taken out as test terminals, preventing an increase in chip size, and improving wiring properties.

[0016]

A semiconductor integrated circuit according to the present invention comprises: a first shift register for providing serial data including an address and input data to a plurality of address terminals and a plurality of input signal terminals of a semiconductor memory device; A second shift register that converts data output from a plurality of output signal terminals of the semiconductor memory device into serial data; and a bit / counter that measures the number of address terminals and input data signal terminals of the semiconductor memory device from an input clock signal. The semiconductor memory device is characterized by comprising a word size determination circuit, and control means for controlling writing and reading of the semiconductor memory device from the serial input signal and the bit / word size determination circuit.

Further, a semiconductor integrated circuit according to the present invention comprises an input terminal, a clock terminal, a reset terminal, and an output terminal.
A first shift register for providing serial data including an address and input data to a plurality of address terminals and a plurality of input signal terminals of the semiconductor memory device, and converting data output from the plurality of output signal terminals of the semiconductor memory device into serial data A second shift register for conversion, a bit / word size determination circuit for measuring the number of address terminals and input data signal terminals of the semiconductor memory device from the input clock signal, and a serial / input signal and bit / word size determination circuit. Control means for controlling writing and reading of the semiconductor memory device.

In the present invention, the semiconductor memory device may be of a compile type having a variable address and data width, and the bit / word size determination circuit may include a counter for counting the sum of an address signal and a data signal. And a latch circuit that holds a logical value.

In the present invention, the control means for controlling writing and reading of the semiconductor memory device may be a logic circuit, and an input signal is supplied to the control means for controlling writing and reading of the semiconductor memory device. A configuration including a third shift register may be employed.

Further, according to the present invention, an address and data pattern creation circuit required for the BIST circuit can be omitted, and the number of gates used can be greatly reduced.

Furthermore, in the present invention, the external terminals can be composed of only a data input terminal, a clock terminal, a reset terminal, and an output terminal, so that the wiring properties are good. Furthermore, even if the word size / bit size of the RAM increases, the number of external terminals does not change, so that it is possible to prevent the wiring performance from deteriorating.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor integrated circuit device according to an embodiment of the present invention will be specifically described below with reference to the accompanying drawings. FIG. 1 is a block diagram showing a semiconductor integrated circuit device according to an embodiment of the present invention.

The semiconductor integrated circuit device 10 according to the embodiment of the present invention includes an input terminal 1-1, a clock terminal 1-2, a reset terminal 1-3, an output terminal 8, an input buffer 2, an output buffer 7, And a first shift register 3-1 for providing serial data including input data to a plurality of address terminals and a plurality of input signal terminals of the semiconductor memory device 4,
A second shift register for converting data output from a plurality of output signal terminals of the semiconductor storage device into serial data; and determining the number of address terminals and input data signal terminals of the semiconductor storage device from the input clock signal. A bit / word size determination circuit 5 to be measured; a logic circuit 6 as control means for controlling writing and reading of the semiconductor memory device 4 from the serial input signal and the bit / word size determination circuit 5 as input signals; And a third shift register 3-3 for providing an input signal to the third shift register 3-6.

An input terminal 1-1 is connected to an input of a serial input type shift register as a third shift register 3-3 and an input of a serial input type shift register as a first shift register 3-1 via an input buffer 2, The first and second outputs of the third shift register 3-3 are connected to the write terminal W and the read signal R of the RAM 4 via the logic circuit 6 together with the output of the word / bit size determination circuit 5. . The output of each stage of the first first shift register 3-1 is connected to the address and data input 4-1 of the RAM 4.

A clock terminal 1-2 is input to a clock of a parallel input type shift register as a third shift register 3-3 and a second shift register 3-2 via an input buffer 2, and has a word / bit size. It is input to the judgment circuit 5. The clock of the first shift register 3-1 is supplied from the word / bit size determination circuit 5. The input of each stage of the second shift register 3-2 is a RAM4
Of the second shift register 3
The output of -2 is connected to the output terminal 8 via the output buffer 7, and the input control signal of the second shift register 3-2 is connected to the read signal R of the RAM 4.

The reset terminal 1-3 is connected to the bit / word size determination circuit 5. When the write operation and the read operation of the RAM 4 are respectively performed, the write signal W and the read signal R to be applied have the same logic.

Next, the operation of the semiconductor integrated circuit device 10 according to the present embodiment will be described. First, a reset signal is supplied from the reset terminal 1-3 to reset the bit / word size determination circuit 5. Bit / word determination circuit 5
The reset operation of the first shift register 3-1
Set the state so that the clock can be supplied to
Then, the logic circuit 6 is controlled so that the data of the third shift register 3-3 is not transmitted to the write signal W and the read signal R of the RAM 4.

Next, data is serially supplied from the input terminal 1-1 so that the address signal and the data signal of the RAM 4 become desired data. At this time, the clock terminal 1-
2, the data input from the input terminal 1-1 is 1
It is sequentially shifted by the clock and by the first shift register 3-1.
A clock is input until the value of the shift register of each stage corresponding to the pair becomes desired data.

On the other hand, the data input from the input terminal 1-1 is input to the third shift register 3-3, but since the bit / word size determination circuit 5 controls the logic circuit 6, the data of the RAM 4 Write signal W and read signal R
No signal is transmitted.

Here, the number of clocks to be given is determined by the RAM 4
At this time, the bit / word size determination circuit 5 stops the clock supplied to the first shift register 3-1 and additionally outputs the third shift register 3-3. The logic circuit 6 is controlled so that signals are transmitted to the write signal W and the read signal R of the RAM 4.

Next, in order to perform a write operation of the RAM 4,
Signals are serially applied from the first shift register 3-1 so that the write signal W and the read signal R of the RAM 4 have desired set values. At this time, data input from the input terminal 1-1 in synchronization with the clock terminal 1-2 is sequentially shifted by the third shift register 3-3 every clock. At this time, the bit / word size determination circuit 5
The logic circuit 6 is controlled so that the value of each stage of the shift register 3-3 is transmitted to the write signal W and the read signal R of the RAM 4. Further, a bit / word size determination circuit 5
Since the clock supplied to the first shift register 3-1 is also stopped, the RMA 4 can write desired data to a desired address.

Subsequently, when data is read from the determined address, the data is input from the data input terminal 1-1 to the RAM 4
In such a manner that the read signal R has a desired set value. At this time, the third shift register 3-3 corresponding to the write signal W
The logic value of 3 is set to the logic set in the read signal R at the time of the write operation, and the logic of the write operation and the logic of the read operation of the RAM 4 are the same, so the third shift register 3 corresponding to the write signal W The logic of -3 is different from the logic of the write operation, and the logic of the read operation can be set correctly. Similarly to the write operation, the bit / word size determination circuit 5 operates the logic circuit 6 so that the value of each stage of the third shift register 3-3 is transmitted to the write signal W and the read signal R of the RAM 4 in the read operation. , And the bit / word size determination circuit 5
Since the clock supplied to the shift register 3-1 is also stopped, the RMA 4 outputs data from a desired address. On the other hand, the input control signal of the second shift register 3-2 is activated by the read terminal R of the RAM 4,
The output data of AM4 is transmitted to each stage of the second shift register 3-2, and the logical value of one stage of the second shift register 3-2 can be obtained from the output terminal 8 via the output buffer 7.

Further, in order to repeat the write operation of the next address or data, an operation of applying a reset signal to the reset terminal 1-3 and sequentially providing desired data from the input terminal 1-1 is as described above. is there.

Looking at the output data of the RAM 4, only one bit of the output data of the RAM 4 can be obtained from the output terminal 8 immediately after the read operation. When the reset signal is input, the second shift register 3-2 is shifted, and the data of the RAM 4 set in the previous stage can be taken out. After this time, the input of the second shift register 3-2 is deactivated by setting the read signal R of the RAM 4 to a logic different from that of the read operation. Further, in parallel with the data input operation for performing the next write operation, the second shift register 3-2
Are sequentially shifted, and the data of each stage set in the second shift register 3-2 can be extracted from the output terminal 8 via the output buffer 7 during the read operation.

Another embodiment of the present invention will be described with reference to the accompanying drawings. The same components as those in the embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. FIG. 2 is a block diagram illustrating a test method according to another embodiment of the present invention. FIG. 3 shows the waveform of each terminal of the present embodiment. FIG. 3A shows an input waveform of the input terminal,
(B) shows the input waveform of the clock terminal, (c) shows the input waveform of the reset terminal, (d) shows the signal supplied from the bit / word size determination circuit to the clock of the shift register, e) shows the waveform of the output terminal. Note that T0, T1,..., T13 in FIG. 3 represent the lapse of time for each unit time of the waveform.

This embodiment is different from the embodiment in that the RAM 4
Are the address signal A0, the data input signals DI0, DI
1. It has data output signals DO0 and DO1, and the output of each stage of the serial input type first shift register 3-1 is RAM
4 address terminal A0, data input signals DI0, DI1
They are connected and have a three-stage configuration. The data output signals DO0 and DO1 of the RAM 4 are output from the parallel input type
It is connected to the input of the shift register 3-2 and has a two-stage configuration. Other than these, the configuration is the same as that of the embodiment. In the present embodiment, the logic given in the read and write operations of the RAM 4 is 1.

In this embodiment, the clock waveform is input to the clock terminal 1-2 from time T0 to time T7, and the second and third shift registers 3-3, 3-3
2 and the operation timing of the bit / word size determination circuit 5.

At time T0, a reset signal is supplied from the reset terminal 1-3 to reset the bit / word size determination circuit 5. First, the reset operation of the bit / word determination circuit 5 sets a state so that the clock supply of the first shift register 3-1 can be performed from the CCLK terminal of the bit / word determination circuit 5, and secondly, the RAM 4 Write signal W and read terminal R to third shift register 3-3
The logic circuit 6 is controlled so that no data is transmitted.

Next, at times T1, T2 and T3, R
When the address signal A0 of AM4 is 0 and the data signals DI0 and D
Data is serially supplied from the input terminal 1-1 so that I1 becomes 0 and 0, respectively. At this time, clock terminal 1
The data input from the input terminal 1-1 in synchronism with -2 is sequentially shifted every clock and by the first shift register 3-1 and is one-to-one corresponding to the address signal A0 and the data signals DI0 and DI1 of the RAM 4. The clock is input when the value of the shift register of each corresponding stage is set, and the time T
Confirm with 3.

On the other hand, the data input from the input terminal 1-1 is input to the third shift register 3-3. However, since the bit / word size determination circuit 5 controls the logic circuit 6, the data in the RAM 4 is written. No signal is transmitted to signal W and lead terminal R.

At time T3, the bit / word size determination circuit 5 stops the clock supplied to the first shift register 3-1 after the next time, and additionally outputs the output of the third shift register 3-3 to the write signal of the RAM 4. The logic circuit 6 is controlled so that a signal is transmitted to W and the read signal R.

Next, in order to perform a write operation of the RAM 4,
At time T4, 1 is supplied from the input terminal 1-1, and at time T5, 0 is supplied from the input terminal 1-1. At this time, data input from the input terminal 1-1 in synchronization with the clock terminal 1-2 is sequentially shifted by the third shift register 3-3 every clock. At this time, since the bit / word size determination circuit 5 controls the logic circuit 6 so that the value of each stage of the third shift register 3-3 is transmitted to the write signal W and the read signal R of the RAM 4, At time T5, the write signal W
And read signal R are set to 1 and 0, respectively.
Further, since the bit / word size determination circuit 5 also stops the clock CCLK supplied to the first shift register 3-1, the RMA 4 sets the value of the RAM 4 to 0 at time T5.
Write data 00 to the address.

Subsequently, in order to read data from address 0, at time T6, input terminals 1-1 to 1 are given. At this time, the logical value of the third shift register 3-3 corresponding to the write terminal W is set to the logical value 0 set to the read terminal R during the write operation. In the read operation, as in the write operation, the bit / word size determination circuit 5 stores the value of each stage of the third shift register 3-3 in the RAM 4
Since the logic circuit 6 is controlled so as to be transmitted to the write terminal W and the read terminal R, and the bit / word size determination circuit 5 also stops the clock supplied to the first shift register 3-1. , RMA4 data output signal D
In O0 and DO1, data 0,
0 is output.

On the other hand, the input control signal of the second shift register 3-2 is activated by the read terminal R of the RAM 4, and outputs the output data of the RAM 4 to the second shift register 3-2.
, And the value 0 of the data output signal DI1 can be obtained from the output terminal 8 via the output buffer 7.

At time T7, the bit / word size determination circuit 5 is reset before the next write operation of the RAM 4 is performed. This operation is equivalent to the reset operation described above. At this time, since the input control signal of the second shift register 3-2 is activated by the same logic as the read signal of the RAM 4, the input control signal becomes inactive at time T7, and is deactivated by the clock input from the clock terminal 1-2. The 2-shift register 3-2 is shifted, and the value 0 of the data output signal DI0 of the RAM 4 can be obtained from the output terminal 8 via the output buffer 7.

As described above, the signals extracted at times T6 and T7 are compared with the expected values, and the RAM 4 is tested.

On the other hand, the read and write timing of the RAM is determined by the unit time of each time and the pulse width inputted from the clock terminal 1-2, so that it can be easily controlled from the outside.

In this embodiment, when the address signal is 1
The RAM 4 having two data signals has been described.
The present invention is not limited to this, and even if it is a compile type RAM in which the address and the data width are variable, there is no particular problem simply by changing the number of stages of the shift register and the bit / word size determination circuit 5. Further, the bit / word size determination circuit 5 can be easily realized by a combination of a counter for counting the sum of the address signal and the data signal of the RAM to be tested and a latch circuit for holding a logical value.

[0049]

As described in detail above, according to the present invention,
Since it can be composed of only a shift register, bit / word determination, and a small-scale logic circuit, circuits for address generation, data generation, BIST control, and output determination required for a test by a BIST circuit are not required, and circuit overhead is reduced. be able to.

Further, according to the present invention, the external terminals can be constituted only by the data input terminal, the clock terminal, the reset terminal and the output terminal, so that the wiring property is good. Furthermore,
The number of external terminals does not change even when the word size / bit size of the RAM increases, so that it is possible to prevent the wiring performance from deteriorating.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 3A is an input waveform of an input terminal, and FIG.
Is an input waveform at the clock terminal, (c) is an input waveform at the reset terminal, (d) is a signal supplied from the bit / word size determination circuit to the clock of the shift register, and (e) is FIG. 4 is a diagram illustrating a waveform of an output terminal.

FIG. 4 is a block diagram illustrating a method of testing a RAM using a conventional self-test circuit.

FIG. 5 (a) is a BIST given from the input terminal of FIG. 4;
(B) is an output signal of a test output terminal when the RAM operates normally, and (c) is an input signal to the circuit.
FIG. 6 is a diagram showing an output signal of a test output terminal when a RAM has failed.

FIG. 6 is a block diagram showing a method for directly pulling out test terminals of a conventional RAM to the outside.

[Explanation of symbols]

 1-1 Input terminal 1-2 Clock terminal 1-3 Reset terminal 2, 102, 117 Input buffer 3-1 First shift register 3-2 Second shift register 3-3 Third shift register 4, 104, 114 RAM 4-1 Address and data input 4-2 Data output 5 Bit / word size determination circuit 6 Logic circuit 7 Output buffer 8 Output terminal 10, 100, 110 Semiconductor integrated circuit Device 101: input terminal 103: BIST circuit 105: output buffer 106: output terminal 111-1 to 111-n: test input terminal 112: input or input / output buffer 113: test switching terminal 115-1 to 115-n: test output Terminal 116: Output or input / output buffer 118: General-purpose logic circuit A0: Address signal DI0, DI1: Data input signal DO0, DO1 ... data output signal

Claims (6)

[Claims] 1. A first shift register for applying serial data including an address and input data to a plurality of address terminals and a plurality of input signal terminals of a semiconductor memory device, and output from a plurality of output signal terminals of the semiconductor memory device. A second shift register for converting data into serial data, a bit / word size determination circuit for measuring the number of address terminals and input data signal terminals of the semiconductor memory device from an input clock signal, Control means for controlling writing and reading of the semiconductor memory device from a word size determination circuit. An input terminal, a clock terminal, a reset terminal, and an output terminal; a first shift register that applies serial data including an address and input data to a plurality of address terminals and a plurality of input signal terminals of the semiconductor memory device; A second shift register that converts data output from a plurality of output signal terminals of the semiconductor memory device into serial data; and a bit / counter that measures the number of address terminals and input data signal terminals of the semiconductor memory device from an input clock signal. A word size determination circuit;
Control means for controlling writing and reading of the semiconductor memory device from a word size determination circuit. 3. The semiconductor memory device is of a compile type in which an address and a data width are variable.
Or the semiconductor integrated circuit device according to 2. 4. The semiconductor integrated circuit device according to claim 1, wherein control means for controlling writing and reading of said semiconductor memory device is a logic circuit. 5. The semiconductor integrated circuit according to claim 1, further comprising a third shift register that supplies an input signal to a control unit that controls writing and reading of the semiconductor memory device. apparatus. 6. The semiconductor according to claim 3, wherein said bit / word size determination circuit comprises a counter for counting the sum of an address signal and a data signal, and a latch circuit for holding a logical value. Integrated circuit device.