JPS6067869A - Timing signal generator - Google Patents

Abstract

PURPOSE:To simultaneously form a timing signal and a delayed strobe signal with high accuracy, by forming a test cycle signal, the delay signal thereof and a clock signal synchronous to both signals while counting and delaying said clock signal. CONSTITUTION:In order to form a delay test synchronous signal obtained by delaying a test cycle signal 11 over a definite time (TRTD), a counter 47 and a delay line 49 read a delay time from delay memory 48 to load the same to the counter 47 and holds the value, obtained by applying adding operation to the values held to a register 52 by an adder 51, to the register 52 to set the delay time of the delay line 49. Therefore, a delayed test cycle signal 26 is outputted so as to be delayed over the delay time with respect to the test cycle signal 11 formed by a start control circuit 36.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a timing signal generator, and more particularly to a timing signal generator suitable for semiconductor testing equipment and the like.

[Background of the invention]

In recent years, semiconductor devices such as ICs and LSIs are becoming more highly integrated and faster due to advances in microfabrication technology. Therefore, semiconductor testing equipment for testing these ICs and LSIs also needs to perform high-speed, high-precision testing. However, conventional test equipment has low test accuracy, particularly low timing accuracy, making it difficult to accurately test ICs and LSIs capable of high-speed operation.

FIG. 1 shows a configuration diagram of the test equipment, and the cause will be explained with reference to the diagram. The test equipment has a device under test 9.
A pattern generator 1 that generates a test pattern 12 to be applied to a test pattern 12 and an expected value pattern 13 of an output signal of the device under test 9, and a timing signal 14 and a pattern generator that control the timing of a test waveform 18 that is applied to the device under test 9. A timing generator 2 for generating a strobe signal 16 that instructs the timing for comparing the expected value pattern 13 from the pattern signal generator 1 with the output signal 19 of the device under test 9, and the test pattern 12 from the pattern signal generator 1 and timing. A waveform formatter 4 for shaping the test signal 17 to be applied to the device under test 9 according to the timing signal 14 from the signal generator 2, and an expected value pattern 13 from the pattern generator 1 and the output signal 19 of the device under test 9. A digital comparator 5 that performs comparison using a strobe signal 16, a fail memory 6 that stores the comparison result 21 of the comparator 5, and a driver that adapts the test signal 17, which is the output of the waveform formatter, to the logic amplitude of the device under test 9. 7 and the output signal 19 of the device under test 9 is compared with the reference voltage, resulting in logic "0".

It is comprised of an analog comparator 8 for determining "1" and a delay element 3 for delaying the strobe signal 15 of the timing generator 2.

The device under test 9 is tested using the test apparatus having the configuration shown in FIG. 1 as follows. First, the pattern signal generator 2 generates and outputs a test pattern 12 for each test cycle based on the test cycle signal 11 generated by the timing signal generator 2. The test pattern 12 is transmitted to the timing signal generator 2 in the waveform formatter 4.
According to the timing signal 14 from the waveform formatter 4
After the propagation delay time (T4) of
Outputs 7. The test signal 17 is converted into a logic amplitude for the device under test 9 by the driver 7, and the test waveform 18 is applied to the device under test 9 after the propagation delay time (T7) of the driver 7. The test waveform 18 causes some kind of response to be transmitted from the device under test 9 and appears as an output waveform 19 after a propagation delay time (T9). This output waveform 19 is compared with the voltage after the propagation delay time (T8) by the analog comparator 8, and its output quality is compared with the expected value pattern 13 from the pattern generator 1 by the digital comparator to determine whether it is good or bad. It will be done.

This pass/fail determination can be divided into a test to see if the logic of the device under test 9 is normal, and a test to see if it operates within the time stipulated in the specifications.

Of these, the latter test is performed using the propagation delay time (
T9) is to be accurately measured. Therefore, the propagation delay time of the test equipment, that is, the propagation delay time of the waveform formatter 4 (T4), the propagation delay time of the driver 7 (T7)%, the propagation delay time of the analog comparator 8 (
The strobe signal 15 of the timing signal generator 2 is delayed by the delay element 3 by the propagation delay time TRTD, which is the sum of T8) and the Kerpul propagation delay time (Tc) used for the connection between the valley units. The digital comparator 5 performs the quality determination by correcting the timing of the quality determination. The delay time of this delay element 3 is several tens to several hundred ns, which is several times to several tens of times the maximum test cycle of the test equipment.

Therefore, conventional timing signal generators cannot delay the strobe signal over several cycles to several tens of cycles, and the strobe signal has to be delayed outside the timing signal generator.

However, in order to achieve a high-precision delay, it is necessary to use a distributed constant type composite coaxial cable, which is expensive and requires an increased mounting area, making it impractical.

It is also conceivable to use an inexpensive and small lumped constant type delay element, but this has the disadvantage that the delay time accuracy decreases, making it difficult to perform high-precision timing tests.

[Purpose of the invention]

An object of the present invention is to provide a timing signal generator for testing a device under test that operates at high speed with high time accuracy.

[Summary of the invention]

A timing signal generator according to the present invention includes: delayed test period signal generating means for outputting a test period signal delayed by a certain period; clock signal generating means for generating a clock signal synchronized with the delayed test period signal; Counting and delaying means for counting and delaying signals shall not be provided.
The device is characterized in that the timing signal can be output after being delayed with high precision within its own timing signal generator.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to FIGS. 2 to 6. FIG. 2 is a block diagram showing the main parts of the timing signal generator, and the pulse waveform (a) in FIG.
The test periodic signal 11 shown in and the test periodic signal 11
is delayed for a certain period of time (TRTD), and the pulse waveform shown in Figure 3 (
d), a clock signal path synchronized with the test period signal 11 shown in pulse waveform (b) in FIG. 3, and a clock signal 31 synchronized with the delayed test period signal shown in FIG. and a clock signal 28 synchronized with the test period signal 11 or the delayed test period signal 26.
, 31, and the timing of the test signal 14 as shown in FIG. 3(c) and applied to the device under test, and the determination strobe signal 1 as shown in FIG. 3(f).
Phase generators 24a and 24b that generate and output 5
! It has a J configuration.

The internal configuration of the late generator B shown in FIG. 2 is shown in FIG. 4, and will be explained along with its operation. In FIG. 4, the same reference numerals as in FIG. In the figure, 36 is a start control circuit to which the start signal 35 is input and controls startup, 37 is an oscillator, 37a is an oscillation element, and the wing is an adder for adding the output of the late memory 40 and the output of the register 39. belongs to. Timing information is written into the late memory 40, and a sear address is specified by the timing selection signal 10, and the test cycle is changed every test cycle. 41 is late memory 40
゜Counter that receives the output signal of register 39 as input, 42
is an OR circuit, and 43 is provided at the output section of the OR circuit 42.
c delay line, 44 is a first-in-first-out memory (FIFO), 45 is an OR circuit,
46 is the output of FI FO4, 4 and the delay memory 48
This is a selector that operates when the output of the delay memory 48 is input and the output of the delay memory 48 is selected. 47 is a counter, 4
Reference numeral 9 denotes a delay line which delays the test periodic signal 11 by a certain period of time (TRTD).
This is an element for reading out the data from the delay memory 48 and loading it into the color printer 47. 51 is an adder that adds the output of the selector 46 and the output of the register 52 and outputs the addition result to the register 52.

To explain the operation of the circuit configured as shown in FIG. 4, it is first activated by inputting the start signal 35, but after opening the start control circuit, it first resets the registers 39 and 52 and selects the output of the delay memory 48. The selector 46 is controlled accordingly. Next, OR circuits 42 and 45.

A positive pulse is output at the j mark for one period of the oscillator 370. As a result, the OR circuit 42. At the same time that the test cycle signal 11 is output via the delay line 43, the counter 41 receives current test cycle information from the late memory 40. Also, adder ABBA, register 3
9 and a set value of the oscillator 37 in the late memory 40 that is less than the basic cycle, the result is held in the register 39 for one test cycle, and the delay time of the delay line 43 is controlled by the value.

Further, the current test cycle information, that is, the output of the late memory 40, is written into the FIFO 44.

On the other hand, counter 47. Delay line 49 In order to create a delayed test periodic signal by delaying the Hatist periodic signal 11 by a certain period of time (TRTD), the delay time (TRTD) is read out from the delay memory 48, loaded into the counter 47 via the selector 46, and added. The delay time of the delay line 49 is set by holding in the register 52 the value obtained by adding the value held in the register 52 by the device 51. Therefore, the content of the delay memory 48, that is, the delay time (TR
TD) After a delay, the delayed test period signal A is output. Since the output of the FIFO 44 has been selected by the selector 46 and the start control circuit before this point, timing information in the late memory 40 is input to the counter 47 and the adder 51 via the FIFO 44. Therefore, from now on, a delayed test period signal % obtained by delaying the test period signal 11 by the delay time (TRTD) will be output.

Note that the adders 38 and 51 and the registers 39 and 52 are used to increase the resolution of the test period signal 11 and the delayed test period signal beyond the fundamental period of the oscillator 37. The delay line 43 is calculated based on the result of the addition operation with the set value less than the previous basic cycle, that is, the value held in the registers 39 and 52.
, 49, and the addition result is greater than or equal to the fundamental period fc
In this case, the counters 41 and 47 count one extra count.

Further, the timing selection signal IO specifies the address of the late memory 40 in which timing information is written,
The test cycle cannot be changed every test cycle.

Furthermore, FIG. 5 shows the configuration of the 7-AIDS clock generator B shown in FIG. 2, which generates a clock signal synchronized with the test period signal 11 and a clock signal 3 synchronized with the delayed test period signal A. Let me explain the points.

In FIG. 5, the same reference numerals as in FIGS. 2 and 4 have the same functions, and the D1/I line 53, respectively.
, FIFO54, delay line 55. register 56
, 57 as constituent elements. The phase clock generator 23 as shown in FIG. 5 delays the basic clock signal of the oscillator 37 by delay lines 53 and 54, and provides a clock signal path synchronized with the test period signal 11 and a clock signal synchronized with the delayed test period signal 26. signal 3
1 is created. The delay in 53 sets the value of the register 39 that holds the setting value of the delay line 43 that delays the test cycle signal 11 to the value held again in the register 56. On the other hand, the delay line 55 is set to the value held again in the register 57, which is the value of the register 52 holding the set value of the delay line 49 that delays the delay test cycle signal station.

Therefore, the basic tally clock signal of the oscillator 37 is delayed by delay-ins 53 and 55, and the test period signal 11 is delayed.
a clock signal path synchronized to and a delayed test period signal 26
A clock signal 31 synchronized with is created.

The PIFO 54 converts the timing selection signal 10 to the time TRTD.
A delay l, , is for supplying the 7A generator 24b in FIG. The timing selection signal 10 is written by the test period signal 11, read from the FIFO 54 by the delayed test period signal 26, and the phase generator 24b is controlled to be delayed by the time TRTD.

Next, the test periodic signal 11 created as described above is
', 26 are further counted, and the timing signal 14. Phase generator 24a that creates the strophe signal 15
, 24b will be explained using FIG. As shown in FIG. 6, the phase generators 24a and 24b have the same configuration, so only one configuration is shown. As shown in the figure, a phase memory 58 in which timing information is written;
It is composed of a clock signal path from the phase clock generator B, a counter 59 which takes 31 as an argument, and a delay in 60 which can control the delay time.

The phase generator U receives a timing selection signal 30 (
33), the timing information is read out from the 7-AIDS memory 58 and loaded into the counter 59 by the test period signal 29 (or delayed test period signal 32). After counting the value set by the clock signal 28 (31), the counter 59 outputs the count amplifier output signal 61, and outputs the timing signal 14 (strobe signal 15) via the delay line 60 in which the delay amount is set in advance. Output. Although the embodiment has been described using two sets of phase generators, the same effects can be achieved even when there are three or more sets of phase generators.

〔Effect of the invention〕

As is clear from the above embodiments, the timing generator according to the present invention creates a test periodic signal, a test periodic signal delayed by a certain period of time, and a clock signal synchronized with each periodic signal, and counts the clock signal. Since it is delayed, it is possible to generate a timing signal and a strobe signal delayed by a certain period of time at the same time and at high nK, making it ideal as a timing signal generator for testing semiconductor devices that operate at high speed.

[Brief explanation of the drawing]

FIG. 1 is an overall configuration diagram of a semiconductor operation test device, FIG. 2 is a block configuration diagram of a timing signal generator showing an embodiment of the present invention, and FIG. 3 is for explaining the operation of the circuit block in FIG. 2. The time charts of FIGS. 4 to 6 are specific circuit configuration diagrams of each part shown in FIG. 2. 2...Timing signal generator, n...Rate generator, n...Phase clock generator, 屓a
, 24b...phase generator. Agent Patent Attorney Tadashi Akimoto Figure 1 35 Figure 2 5 μ 56 Factor 6 8

Claims (1)

[Claims] delayed test periodic signal generating means for outputting a test periodic signal delayed by a certain period of time; clock signal generating means for outputting a clock signal synchronized with the output signal from the delayed test periodic signal generating means; counting the clock signal; A timing signal generator comprising counting and delay means for delaying the timing signal.