JPH11125660A - Timing generator for semiconductor test device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent an increase of cable net number especially the increase of printed wiring board, by providing a periodical operation means also in a delay generator, and giving fraction data to a delay operation means in resonance with period initiation data from the period generator. SOLUTION: A period operation means 3 is added for constitution on a delay generator 2i and the fraction data of the operation results of the period operation means 3 is given to a delay operation means 11. Thus, the fraction data transmission line to a delay generator 2i from a conventional period generator 1 is eliminated and the transmission line is reduced to only 1 bit line of a period initiation data. When a start signal is inputted in an input terminals a0 of the period generator 1 and the delay generator 2i, a latch circuit g1 is turned on and a latch circuit 5 of the period operation means 3 is cleared. By the next reference clock, a latch circuit g2 is turned on and the latch circuit 5 latches the period data of the operation results. At this moment, integer data only is utilized in the period generator 1 and fraction data only is utilized in the delay generator 2i. The rest part is the same as before.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing generator in which a period generator and a delay generator are separated from each other in a semiconductor test apparatus, and particularly to a semiconductor test suitable for adapting a perpin tester to a frame processor (FP). The present invention relates to an apparatus timing generator.

[0002]

2. Description of the Related Art First, an outline of a conventional semiconductor test apparatus will be described. FIG. 3 shows a basic configuration diagram of the semiconductor test apparatus. The test processor 31 controls the entire apparatus, and supplies a control signal to each unit via a tester bus. The pattern generator 32 is a DUT (device under test) 3
9 and an expected value pattern to be applied to the pattern comparator 37. The timing generator 33 generates a timing pulse signal for obtaining a test period signal and a test timing of the entire apparatus, and supplies the timing pulse signal to the waveform shaper 34, the comparator 36, the pattern comparator 37, and the like to obtain a test timing.

A waveform shaper 34 shapes the applied pattern from the pattern generator 32 into a test signal waveform, and a driver 35
, A test signal is given to the DUT 39. DUT39
Are compared by a comparator 36, and the resulting logic signal is supplied to a pattern comparator 37. The pattern comparator 37 performs a logical comparison between the logical pattern of the test result from the comparator 36 and the expected value pattern from the pattern generator 32 to detect a match / mismatch, and determines the quality of the DUT 39. In the case of a failure, information is given to the fail memory 38 and stored together with the information from the pattern generator 32, and failure analysis is performed later.

The timing generator 33 has a RATE setting table and a clock setting table. The RATE setting table records pattern period (Test Period) data, and the clock setting table stores timing data such as driver waveforms. It has been recorded. By combining these data, a plurality of groups, for example, a TS1 group, a TS2 group, a TSn group, and the like are prepared and read to generate timing pulses such as a set signal and a reset signal.

In the timing generator 33, the pattern period to be set is based on a reference clock (Reference Clock).
In many cases, a fraction is generated at an integral multiple of the reference clock, but the generation of the pattern period in hardware is set to an integral multiple of the reference clock. On the other hand, the timing pulse signal is 1 / of the reference clock.
, 1/16,..., 1/256, etc., with high precision. Fractional data of the reference clock is obtained by adding the fractional data from the previous pattern cycle and the set fractional data, the resulting integer data is delayed by digital means, and the fractional data is delayed by an analog variable delay circuit. . This will be specifically described.

FIG. 4 shows a basic configuration diagram of the timing generator 33. The configuration is roughly divided into one cycle generation unit 1 and a plurality of delay generation units 2i (i = 1 to n). Since the cycle generator 1 determines the test cycle of the entire semiconductor test apparatus, one cycle generator may be used. However, the delay generator 2i has many timings to be applied to the pins of the LSI of the DUT 39 and the pattern comparator 37. .
As will be described later, recently, a per-pin tester has appeared and the delay generation unit 2i is incorporated in the FP. Therefore, if the number of pins of the LSI is, for example, 1,024 or more, the delay generation unit 2i is 1,024 or more We are preparing things.

The configuration and operation will be described with reference to FIG. As an example of a test condition in which the pattern cycle has information below the reference clock, a reference clock having a frequency of 100 MHz and a cycle of 10 ns (nanosecond) (hereinafter, the cycle of the reference clock is represented by “T”) is used. (5 + 3 /
4) Assume that a timing pulse signal of (3 +＋ １) T is continuously generated for T and a timing delay time. It is assumed that the RATE setting table R1 of the cycle generator 1 stores the pattern cycle (5 + 3/4) and the clock setting table R2 of the delay generator 2i stores the timing delay data (3 + 1/2) in advance. . FIG. 6 shows a timing chart in that case.

The main structure of the period generating section 1 is a period calculating means 3
And a reference clock delay means 6 and a plurality of latch circuits gi and 9 for timing adjustment.
The latch circuit is composed of a D-type flip-flop,
Some have WE (Write Enable) and some do not. The period calculating means 3 includes a RATE setting table R1, an adder 4, and a latch circuit 5 for temporarily storing output data from the adder 4.
The latch circuit 5 sends the integer data to the reference clock delay means 6, sends the fractional data to one input terminal of the adder 4, and adjusts the sending timing by the latch circuits g4 to g6 from the output terminal b1 to the delay generator 2i. To the input terminal a1. The reference clock delay means 6 includes a down counter 7 and a coincidence circuit 8, and generates a signal delayed by an integer of the pattern period.

At the start of a test, when a start signal is input from an input terminal ao, a latch circuit g1 is supplied with a reference clock.
To temporarily clear the latch circuit 5 of the period calculating means 3 and send a signal to the next stage g2. The latch circuit 5 of the cycle calculating means 3 sends a 0 signal (start signal) to the reference clock delay means 6, and the reference clock delay means 6 sends a cycle start signal to the delay generator 2i via the latch circuit 9 and the output terminal b2. At the next reference clock, g2 turns on, and with this on signal, the latch circuit 5 of the period calculating means 3 latches the data of the adder 4 and sends an on signal to the next stage g3. At the next reference clock, g3 turns on, and the down counter 7 of the reference clock delay means 6 loads the integer data of the latch circuit 5.

The RATE setting table R of the cycle calculating means 3
1 stores a pattern cycle (5 + 3/4). In the generation of the first timing pulse, the fraction data is 0 because the latch circuit 5 is cleared by the start signal, and the output data of the adder 4 is (5 + 3 /
4). The integer of 5 of the output data is loaded into the down counter 7, and the fraction data of 3/4 is supplied to one input terminal of the adder 4, and the latch circuits g4 and g
5, and are sent to the delay generation unit 2i through g6.

Therefore, the cycle calculating means 3 of the cycle generator 1 sets the first cycle to 5 and the fraction data to 3 after the start signal.
/ 4, the second cycle is 6, the fraction data is 1/2, the third cycle is 6, the fraction data is 1/4,
The cycle of the fourth shot is 6, the fraction data becomes 0, and from the fifth shot, 5 and 3/4, 6 and 1/2,... 1-bit signal of this periodic data and multi-bi of fractional data
The ts signal is sent to all the delay generators 2i. Although the number of bits of the fractional data varies depending on the cycle resolution, (1/256) 8 bits data is sent as normal high-resolution data.

The main configuration of the delay generator 2i is as follows.
0, delay operation means 11, reference clock delay means 12, retiming means 13, and analog variable delay means 14. Then, fraction data of the previous pattern cycle is input from the input terminal a1, a cycle start signal is input from a2, and a reference clock is input from a3. a
When a cycle start signal is input from 2, the latch circuit f1 of the input means 10 is write-enabled (Write Enable), and the cycle start signal is also supplied to the latch circuit f2. The timing delay data (3 + ／) has already been stored (memory) in the clock setting table R2. (Hereinafter, the timing delay data is referred to as “set delay data”). a3
Is supplied to the latch circuit f1 to latch the fractional data from a1.
1 to the adder K, to the latch circuit f2 to latch the cycle start signal from a2,
Is supplied to the load terminal of the down counter C, and the integer data N output from the adder K is loaded (input). The adder K has already output data obtained by adding the fraction data and the set delay data. The reference clock is also applied to the clock terminal of the down counter C.

In the generation of the first timing pulse, the fraction data from a1 is 0, so that the input data of the adder K of the delay calculation means 11 is 0 and (3 + 1/2), and the output data is (3 + 1/2). 3 + ／). FIG. 6D
reference. The integer data N of 3 is output to the down counter C of the reference clock delay means 12, and the fractional data of 1/2 is output to the latch circuit f4 of the analog variable delay means 14. At the signal of the start of the cycle, the down counter C loads 3 data,
The number is decremented by one with the reference clock from a4, and the data is output from the data out terminal do. When the output signal of the data out terminal do becomes zero with the three reference clocks, the coincidence circuit h1 matches the output signal with zero, and outputs a reference clock delay signal S. The latch circuit f3 of the retiming means 13 and the analog variable delay means 14 And to the latch circuit f4.

The retiming means 13 always adds a fixed offset time by the fixed delay D to the reference clock in order to remove the delay time of the reference clock delay signal S from being varied by the down counter C or the like. This is a circuit for setting the timing of a fixed delay time. Therefore, the reference clock signal from a4 is passed through the fixed delay device D having a delay time slightly larger than the maximum delay time from the input terminal a1 to the retiming means 13 and passed through the gate circuit h2 which is already open. Is used as a reference for the timing pulse. See FIG. 6E. The analog variable delay means 14 delays the time of the fraction data (1/2) latched by the latch circuit f4, and
From (3+ パ ル ス) T. See FIG. 6F. When the first pattern cycle ends,
Fractional data (3/4) of pattern period (5 + 3/4) T
Is applied to the input terminal a1. FIG. 5 shows a configuration diagram of the analog variable delay means 14 for reference.

The delay time of the second timing pulse is the sum of the fractional data (3/4) applied to the input terminal a1 and (3 + 1/2) of the memory in the clock setting table R2, and is added by the adder K. And outputs data of (4 + ／). See FIGS. 6C and 6D. The integer data of 4 is output to the down counter C, the fractional data of (1/4) is output to the analog variable delay means 14, and is delayed by the digital means and the analog variable delay means in the same manner as the first one, and (4 + 1)
/ 4) A timing pulse delayed by T is output. See FIG. 6F.

In the third pattern cycle, the fraction data of the first and second pattern cycles is (3/4 + 3 /
4) = (1 + ／), so that the integer data of 1 is incorporated into the pattern cycle by the cycle generator 1 and the 6 reference clocks obtained by adding 1 to 5 reference clocks are used as the pattern cycle. See FIG. 6A. Therefore, the fraction data of the pattern cycle becomes (1/2) and is supplied to the input terminal a1. Since the data of R2 is (3 + ／), the addition result is 4. Therefore, the output data of 4 from the adder K is sent to the down counter C, and only the digital means is delayed to generate a timing pulse. See FIG. 6F. The above operation is performed even after the fourth shot, and the timing pulse is continuously transmitted.

In FIG. 4, as test conditions, the basic clock has a frequency of 100 MHz, one cycle is 10 ns, the pattern cycle is (5 + 3/4) T, and the timing delay time is (3 + 1).
/ 2) T timing pulse signals were continuously generated. That is, the pattern cycle was 57.5 ns, and the timing delay time was 35 ns. Thus, only one timing pulse signal can be generated within one pattern period. However, recently, within one pattern cycle,
In many cases, four timing pulses are required. In order to generate a plurality of timing pulses within one pattern period, the timing pulses are generated by an interleave method, and the interleave method has become indispensable. The interleaving method refers to a method of alternate arrangement. Although the description of the circuit of the interleave method is omitted, the cycle is generated in the cycle generator 1 in the interleave method, and the cycle data and the fraction data are distributed to the delay generator 2i. That is, the data line between the cycle generator 1 and the delay generator 2i in the interleave system usually has a cycle data of 2 bits and a fraction data of 16 bi.
ts.

By the way, the development of semiconductor ICs is remarkable, and the ICs are becoming more and more highly integrated. In recent LSIs (large-scale integrated circuits), there have appeared LSIs in which a combinational circuit and a memory element are composed of complicated sequential circuits. To test these complex LSIs, LSSD (Level Sensitive Scan Des
ign) technique is used. As described above, with the development of the LSI as the DUT 39, the semiconductor test apparatus is also developing. Conventional shared resource tester (Shared Reso
urce Tester) for VLSI
An advanced tester called Per-pin Resource Tester has also appeared. Also called a shared tester or a perpin tester. Here, the shared tester is a tester that shares a plurality of resources (timing generator, reference voltage, etc.) with all tester pins,
The per-pin tester is a tester having a function of setting test parameters applied to the DUT independently for each pin. The per-pin tester is suitable for advanced logic IC testing because it can generate more complicated test patterns and timing conditions than a shared tester that uses test parameters commonly for each pin.

Therefore, in the perpin tester, the delay generator 2i of the timing generator 33 shown in FIG.
4 are collectively assigned to each pin. A combination of the delay generator 2i corresponding to each pin, the waveform shaper 34, and the like is referred to as a frame processor (FP).
That. That is, the FP means a pin signal generation portion, and a combination of the conventional timing generator 33, waveform shaper 34, pattern comparator 37, and calibration unit is assigned to each pin. With this function, independent timing and waveform can be output independently for each pin as compared with the conventional shared tester. Specifically, the waveform of the entire test can be set by combining each pin with a frame called a single frame, which has a waveform formed for each test cycle. The number of frames at this time differs depending on the model, but four to 32 types are prepared, and further, waveform selection from eight patterns can be performed within one type of frame. Although the present invention has been devised with the above-described FP of the perpin tester, it is naturally applicable to a shared tester.

[0020]

As described above, the DU
The high-density and high-speed semiconductor ICs that are T
Along with this, semiconductor test equipment has been advanced, and LSIs for each functional block have been developed. In the timing generator 33 in the perpin tester of the semiconductor test apparatus, only one cycle generator 1 is required for one system, but the delay generator 2i for the timing pulse requires several I / O pins of the DUT 39. It has become. That is, there is a one-to-many relationship.

The problem is that when the frame processor FP is made into a custom LSI, the number of connection signals from the cycle generator 1 to the delay generator 2i increases in proportion to the number of FPs, and Increase in the number of wirings on the printed wiring board. In order to solve the above-mentioned problem, the present invention reduces the number of wiring nets by reducing the number of connection signal lines from the cycle generation unit 1 to the delay generation unit 2i to one, and reduces hardware, especially a printed wiring board. The purpose is to prevent an increase in

[0022]

In order to achieve the above object, the present invention has been made in consideration of recent developments in LSI, and
In the tester, a frame processor including a delay generation unit is manufactured by a custom LSI, and in the shared tester, the delay generation unit is manufactured by a custom LSI, and a period calculation unit is provided in the delay generation unit. In recent semiconductor IC fabrication techniques, the number of cells in one chip has increased significantly, and this increase has not become a problem. Then, the cycle calculation means of the cycle generation unit performs calculation based on the pattern cycle data including the fraction data, extracts integer data, and sends only 1 bit of the cycle start data to the delay generation unit.

The cycle calculating means in the delay generating section also calculates based on the pattern cycle data including the fraction data. Here, the fraction data is taken out, synchronized with the cycle start data from the cycle generating section, and the 8-bit fraction data is calculated. Was given to the delay calculation means. Other configurations in the delay generation unit are the same as those in the related art. The same can be applied to an interleaved configuration. In other words, when the number of wires is large in the conventional interleave configuration, for example, a cycle start data line of 2 bits and a fraction data line of 16 bits have to be distributed to 1,024 frame processors from one cycle generation unit. According to the present invention, it is sufficient to distribute the 1-bit period start data to 1,024 frame processors.
Hereinafter, the configuration of the present invention will be described.

The first invention relates to a conventional shared tester, and the timing generator comprises a period generator and a plurality of delay generators. The main components of the cycle generation unit are a cycle calculation means for calculating a pattern cycle based on pattern cycle data including fraction data from the RATE setting table and outputting integer data of the calculation result, and a reference for the number of the integer data. It has a reference clock delay means for delaying a clock, and an output terminal for outputting the cycle start data generated by being delayed. The main configuration of the plurality of delay generators is to calculate the fraction data of the pattern cycle based on the pattern cycle data including the fraction data from the RATE setting table, and synchronize with the cycle start data sent from the cycle generator. A period calculating means for transmitting the fraction data of the calculation result, and adding the fraction data sent from the period calculating means and the setting delay data including the fraction data from the clock setting table to obtain integer data and fraction data of the calculation result. , A reference clock delay means for delaying the reference clock of the number of the integer data from the delay calculation means, and a delayed reference clock delay signal from the reference clock delay means. Analog variable delay means for generating a timing pulse by giving a delay of the value of the fractional data.

The second invention is applied to an interleaved configuration, and the differences from the first invention will be described. The cycle calculating means of the cycle generating section is a cycle calculating means having two or more adders and outputting two or more integer data in one pattern cycle. The cycle calculating means of the delay generating section is a cycle calculating means having two or more adders and outputting two or more fractional data within one pattern cycle. The reference clock delay unit and the analog variable delay unit of the delay generation unit have two or more configurations. Two or more timings within one pattern cycle
A pulse is generated, and a logical sum is output at the output stage and output. Third
In the invention, the first invention and the second invention are configured in a frame processor of a perpin tester. That is, the delay generator of the first invention and the second invention is configured in a frame processor. Specified.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described based on embodiments with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of one embodiment adapted to an interleave configuration of the present invention. 4 are given the same reference numerals. FIG. 1 shows the conventional configuration of FIG. 4 to which the present invention is applied. FIG. 1 will be described.

The cycle generator 1 shown in FIG. 1 is the same as the cycle generator 1 shown in FIG.
And a configuration excluding a transmission circuit for fraction data. That is, the fractional data transmission circuit from the latch circuit 5 of the cycle calculation means 3 to the output terminal b1 is excluded. Other parts are the same. The delay generating section 2i is configured by adding a period calculating means 3 to the conventional one, and has a start signal input terminal ao
Was also provided. In addition, a cycle start signal from the cycle generator 1 is branched and received so that synchronization can be achieved. Then, the fraction data of the calculation result of the cycle calculation means 3 is provided to the delay calculation means 11. With the above configuration, the conventional fractional data transmission line from the cycle generator 1 to the delay generator 2i can be eliminated. Therefore, the transmission line is only the 1-bit line of the cycle start data.

The operation will be briefly described. When a start signal is input to the input terminals ao of the cycle generator 1 and the delay generator 2i, the latch circuit g1 is turned on and clears the latch circuit 5 of the cycle calculator 3. The latch circuit g2 is turned on by the next reference clock, and the latch circuit 5 latches the cycle data of the operation result. At this time, the cycle generator 1 uses only integer data, and the delay generator 2i uses only fractional data.

Thereafter, as in the prior art, the cycle generating section 1 loads the integer data into the down counter 7 of the reference clock delay means 6 to generate and transmit a cycle start signal. In the delay generator 2i, the calculated fraction data is given to the adder of the delay calculating means 11, the integer data is sent to the reference clock delay means 12, and the fraction data is sent to the analog variable delay means 1.
4 to generate a timing pulse.

FIG. 2 is a block diagram of an example in which the present invention is applied to an interleave configuration. Period calculation means 3 of period generator 1
Is a period calculating means 3 having two or more adders and outputting two or more integer data within one pattern period. The cycle calculating means 3 of the delay generator 2i is a cycle calculating means 3 having two or more adders and outputting two or more fractional data within one pattern cycle. The reference clock delay unit 12 and the analog variable delay unit 14 of the delay generation unit 2i have two or more plural configurations. Two or more timing pulses are generated within one pattern period, and the output stage performs OR operation and outputs the result.

[0031]

As described above in detail, according to the present invention, in a timing generator for a semiconductor test apparatus, a signal transmission line between a period generator 1 and a delay generator 2i is 1bi.
Only one of t is needed. Therefore, the number of transmission lines is extremely reduced from 1/9 to 1/18 of the conventional one, and the volume of the printed wiring board in that portion is extremely reduced. In addition, since the number of lines was very small, connection errors and design errors were reduced.

Although the customary LSI is used for the delay generating section 2i, even if the period calculating means 3 is added, the manufacturing cost is almost the same as the conventional one. On the other hand, the number of design steps is reduced and the cost is more advantageous. The present invention makes use of the features of a custom LSI, and although the number of cells in one chip has increased, this has not led to an increase in cost.
It also contributed to miniaturization of semiconductor IC test equipment. Thus, the technical effects of the present invention are great.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a configuration diagram of another embodiment of the interleaving method of the present invention.

FIG. 3 is an example of a basic configuration diagram of a semiconductor test apparatus.

FIG. 4 is an example of a basic configuration diagram of a conventional timing generator.

FIG. 5 is an example of a configuration diagram of an analog variable unit 14;

FIG. 6 is a timing chart of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Period generating part 2i (i = 1 to n) Delay generating part 3 Period calculating means 4, 42 Adder 5, 52 Latch circuit 6 Reference clock delay means 7 Down counter 8 Matching circuit 9 Latch circuit 10 Input means 11, 112 Delay Arithmetic means 12, 122 Reference clock delay means 13 Retiming means 14, 142 Analog variable delay means 15i Analog delay unit 16i Selector 31 Test processor 32 Pattern generator 33 Timing generator 34 Waveform shaper 35 Driver 36 Comparator 37 Pattern comparator 38 Fail memory 39 DUT (device under test) C counter D Fixed delay device R1 RATE setting table R2, R3 Clock setting table N Integer value of setting delay data S Reference clock delay signal T Reference clock period K Adder fi latch Circuit gi latch circuit h1 match circuit h2 gate circuit

Claims (3)

[Claims] 1. A timing generator comprising a cycle generator and a plurality of delay generators, wherein a pattern cycle is calculated based on pattern cycle data including fraction data from a RATE setting table, and integer data of a calculation result is output. One cycle generating unit having a cycle calculating unit for performing the above operation, and a reference clock delay unit for outputting the cycle start data generated by delaying the reference clocks of the number of the integer data. Calculates the fraction data of the pattern cycle based on the 1-bit one transmission line to be transmitted and the pattern cycle data including the fraction data from the RATE setting table, and calculates in synchronization with the cycle start data sent from the cycle generator. A period calculating means for transmitting the resulting fraction data;
Delay calculating means for adding fraction data sent on the transmission line from the cycle calculating means and set delay data including the fraction data from the clock setting table to output integer data and fraction data as a calculation result; A reference clock delay means for delaying the reference clock of the number of integer data from the arithmetic means, and a delay of the fractional data value from the delay arithmetic means to the delayed reference clock delay signal from the reference clock delay means. A timing generator for a semiconductor test apparatus, comprising: a plurality of delay generators having analog variable delay means for generating a timing pulse. 2. The cycle calculating means of the cycle generating section is a cycle calculating means having two or more adders and outputting two or more integer data in one pattern cycle. With two or more adders, two in one pattern period
The above-mentioned cycle calculating means for outputting fractional data, wherein the reference clock delay means and the analog variable delay means of the delay generating section have two or more configurations,
2. An interleaved configuration in which the above-mentioned timing pulse is generated and an OR operation is performed at an output stage.
A timing generator for a semiconductor test apparatus as described in the above. 3. The timing generator according to claim 1, wherein the delay generator is constituted by a frame processor.