JP2001228213A - Semiconductor integrated circuit device and method for inspecting clock skew - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device capable of observing the magnitude of the clock skew, distributed to a plurality of clock using circuits requiring the supply of a clock, from the outside. SOLUTION: A dummy flip-flop(F/F) inputting a clock signal to a data input terminal is provided in the vicinity of the F/F inspecting the skew of the clock signal among a plurality of F/Fs and a test signal is connected to the clock input terminal of the dummy F/F from an external test terminal A and, at the time of testing, the transition timing of the test signal supplied from the external test eterminal A is shifted at every predetermined step and the transition timing of the clock signal supplied to a plurality of dummy F/Fs is detected by reading the logic value taken in each dummy F/F inputting the test signal as the clock signal in each timing step to discriminate the magnitude of clock skew.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit device capable of observing a clock skew in a circuit in a semiconductor integrated circuit and a method of verifying the clock skew.

[0002]

2. Description of the Related Art In recent years, the scale of circuits integrated on one chip has been steadily increasing with the development of miniaturization techniques for semiconductor devices, and semiconductor integrated circuit devices having a circuit scale exceeding one million gates have also been manufactured. -It has been sold, and the operating frequency of the circuit has been increased. With the increase in the circuit scale of the semiconductor integrated circuit device, in the semiconductor integrated circuit device,
The number of clock-using circuits (typically, including flip-flops, latches, counters, shift registers, and any circuits, cells, and macros driven by clocks) that require supply of a clock is also increased, The clock signal wiring that supplies the clock signal has a longer wiring length, and the clock propagation delay time due to the clock signal wiring length also varies greatly depending on the circuit layout, and as a result, the clock supply source distributes the clock signal to each clock-using circuit. The variation of the time shift of the clock signal is also large.

In order to cause a semiconductor integrated circuit device having a plurality of clock using circuits driven by a clock signal serving as a reference of operation timing to perform a desired operation, a clock skew in the clock using circuit in the semiconductor integrated circuit device is required. It is necessary to keep (a time difference generated between clock signals when transmitting a clock signal in a plurality of transmission systems) a specified value. For example, when a synchronous circuit driven by a clock signal is operated in a minimum cycle, a malfunction occurs if the clock skew exceeds a specified value due to variations in clock skew or the like.

For this reason, conventionally, in the design stage of a semiconductor integrated circuit, a buffer for equalizing delay has been optimally inserted into a clock signal wiring network in order to minimize the difference in clock signal propagation time. Design by a clock tree synthesis (CTS) method of laying out in a tree shape and distributing clock signals to circuits using clocks,
Further, the clock skew is minimized by using a layout design or the like in consideration of timing conditions by a timing analysis tool or the like.

As described above, even if a mask pattern is created so as to reduce clock skew at the layout stage of a semiconductor integrated circuit, the capacitance cannot be predicted at the time of design before manufacture due to variations due to process variations in semiconductor manufacturing. In some cases, the clock skew in the manufactured semiconductor integrated circuit device deviates from a design value before the manufacture and increases due to resistance and the like.

In a semiconductor integrated circuit device driven at a high operating frequency, for example, the possibility that a clock skew on the order of hundreds of picoseconds or tens of picoseconds causes a malfunction of the circuit is increasing. After manufacturing a circuit device, it is extremely important to verify clock skew.

[0007]

Several semiconductor integrated circuit devices having a circuit configuration for measuring a clock signal skew of a semiconductor chip have been proposed. Among them, for example, Japanese Patent Application Laid-Open No. H8-15380 discloses a flip-flop 1 connected to a clock signal line and receiving a clock signal CLK at a clock input terminal as shown in FIG.
1 and 12, an external measurement signal DATA is input to each data input terminal of the flip-flops 11 and 12, and the delay time of the external measurement signal to the flip-flop 11 and the delay time to the flip-flop 12 are equalized.
Output terminal of flip-flop 11 and flip-flop 12
Is connected to the input of an exclusive-OR circuit (XOR) 13 to detect a change point of the output level of the exclusive-OR circuit 13 by changing the external measurement signal DATA with the resolution of the LSI tester. Has proposed a configuration for measuring the skew of a clock signal.

However, Japanese Patent Application Laid-Open No. Hei 8-15380 discloses
The test circuit described in the above publication has the following problems.

The first problem is that the flip-flop 11,
In order to make the delay time from the output terminal 12 to each input terminal of the exclusive OR circuit (XOR) 13 equal, an extra design is required. Conversely, an exclusive OR circuit (XO) is output from the output terminals of the flip-flops 11 and 12.
If the signal propagation delay time to the input end of R) 13 is not equal, accurate clock skew cannot be measured. That is, the skew between the output terminals of the flip-flops 11 and 12 and the input terminal of the exclusive OR circuit (XOR) 13 is suppressed to a particularly small value as compared with the clock skew between the two flip-flops 11 and 12. The skew of the clock signal can be measured only when the clock signal is skewed.

The second problem is that one exclusive OR circuit (XOR) is provided for the two flip-flops 11 and 12.
13 means that the chip area increases. That is, the internal circuit of the semiconductor integrated circuit device includes many flip-flops that need to consider clock skew.
According to the configuration described in Japanese Patent Application Publication No.
If one exclusive OR circuit (XOR) is prepared for each of them, the area of the test circuit increases and the chip area increases.

A third problem is that no pulse signal is output from the output terminal OUT when the clock skew between the two flip-flops 11 and 12 is small. That is, when the clock skew is small and the time difference between the transition edges of the output signals of the flip-flops 11 and 12 is small, the output of the exclusive OR circuit (XOR) 13 is kept at the original value without inversion, and the clock skew is kept. Cannot be output, and the pulse signal cannot be observed from the output terminal OUT.

The fourth problem is that the flip-flop 11,
12 outputs a pulse signal having a pulse width corresponding to the skew of the clock input from the output terminal OUT,
Only information on the clock skew time can be obtained,
From this pulse signal, it is not known which of the clocks input to the flip-flops 11 and 12 is advanced in phase or which clock is delayed.

That is, since the ranking cannot be made based on the magnitude of the clock skew, information for determining which clock should be adjusted in timing cannot be obtained, and which clock is shifted among a plurality of clocks is determined. Cannot be specified, so that the clock skew cannot be readjusted properly. Therefore, when adjusting the clock skew, the phase of the clock input to the flip-flops 11 and 12 is adjusted by trial and error until the pulse signal does not appear from the output terminal OUT.

For example, Japanese Patent Application Laid-Open No. 9-292723 discloses that, as shown in FIG. 10, an external clock or an internal clock is distributed to a predetermined number of internal clocks, and the distributed internal clock is further divided into a predetermined number of clocks. A clock tree to be distributed, a skew variation observation circuit 14 provided for a predetermined internal clock and detecting a skew variation between the internal clocks, and a skew variation observation circuit 14 provided for the predetermined internal clock;
A load increasing / decreasing circuit 16 for increasing the load of the internal clock whose phase is relatively advanced among the internal clocks, and a skew variation observing circuit 14 provided in the external clock or the internal clock close to the internal clock source in the skew variation observation circuit 14 sequentially. A configuration is disclosed that includes an order maintaining circuit 18 for fixing the detection state and fixing the load of the internal clock by the load increasing / decreasing circuit 16. The skew variation observation circuit 14 includes a NOR circuit 24 that receives an internal clock output from a plurality of buffers 22 and a plurality of latch circuits 28 that receives the output of the NOR circuit 24 as an input to an enable terminal G. The internal clock output from 22 is delayed by the delay buffer 26, input to the data input terminal of the latch 28, and when the internal clock having a relatively advanced phase among the internal clocks rises, the output of the NOR circuit 24 goes low. Then, the latch circuit 28 whose output is inputted to the enable input terminal G is turned off, and the clock whose phase is relatively advanced among the internal clocks delayed by the delay buffer 28 is held at the high level by the latch. The clock with a relatively delayed phase is held at a low level in the latch, 18 has an output in the number corresponding to the number of stages of the buffer 22 of the clock tree,
Each output is provided with a shift register 34 commonly input to the NOR circuit 24 of the same set of skew variation observation circuits in the same stage.

As described above, Japanese Patent Application Laid-Open No. 9-292723 describes
In the configuration described in Japanese Patent Application Laid-Open Publication No. H11-157, the clock skew in the clock tree is automatically detected, and the clock with advanced phase increases the load, increases the amount of delay, and makes the clock skew uniform. There is
The configuration is such that a delay buffer and a load increase / decrease circuit are added to the signal wiring of the clock tree of the internal clock, and this configuration (the configuration in which various load circuits are connected to the signal wiring of the clock tree) distributes the clock signal. On the other hand, it is difficult to adjust the clock skew at the clock input terminal of the receiving clock using circuit. In addition, as described in
In the configuration described in Japanese Unexamined Patent Application Publication No. 292723/1990, the configuration is not designed to monitor the clock skew at the clock input terminal of the clock using circuit that receives the supply of the clock signal at each end (leaf) of the clock tree. There is no means for observing the clock skew at the clock input terminal of the used circuit.

For example, in Japanese Patent Laid-Open Publication No. Hei 8-15380, a feedback path is provided corresponding to a path for supplying a clock signal, and each of the feedback path and the supply path is formed so that the delay time can be increased or decreased. A variable delay circuit, a phase detection circuit for detecting a phase shift of the transmitted clock signal, a control circuit for adjusting a signal delay time in the variable delay circuit based on the phase shift detection result, and a feedback path. A configuration of a clock skew correction circuit that corrects a phase shift of a clock signal in a clock distribution system based on the signal waveform of (1) is disclosed. However, in the configuration described in JP-A-8-15380,
There is a design constraint that the clock supply path is designed according to a special layout in which the feedback path is routed, which limits the design flexibility and makes it impossible to apply a design method such as clock tree synthesis as it is. It is.

As described above, none of the conventional proposals meet the demand for observing the clock skew of a semiconductor integrated circuit device having high integration and high operating frequency. At present, a design method of a semiconductor integrated circuit device having a function of making it possible to correctly and externally observe a clock skew of an internal node of the circuit device is not provided at present. Therefore, if a semiconductor integrated circuit device product malfunctions due to clock skew,
It is impossible to observe, adjust, and repair the clock skew of the internal circuit from the outside.

Accordingly, the present invention has been devised completely as a result of intensive studies by the present inventors who have recognized the above problems, and the main purpose of the present invention is to distribute to a plurality of clock-using circuits which require clock supply. It is an object of the present invention to provide a semiconductor integrated circuit device capable of externally observing the magnitude of a clock skew, and a clock skew verification method. Other objects, advantages, features, and the like of the present invention will be immediately apparent to those skilled in the art from the descriptions of the embodiments below.

[0019]

According to the present invention, there is provided a semiconductor integrated circuit device having a plurality of clock using circuits receiving a clock signal from a clock supply source. A clock skew monitor latch circuit is provided in the vicinity thereof in correspondence with a predetermined clock use circuit, and a data input terminal of the latch circuit is provided with respect to the clock use circuit corresponding to the latch circuit. A clock signal line for supplying a clock signal with a delay time equal to the delay time of the clock signal supplied from the clock supply source is connected, and a clock input terminal of the latch circuit is inputted from an external test terminal. A test signal line for supplying a test signal as a latch timing clock of the latch circuit is connected. And, the state of the latch circuit is capable read from the external output terminal.

In the present invention, a test signal line for supplying a test signal input from an external test terminal to the latch circuit is connected to a data input terminal of the latch circuit. A clock signal line for supplying a clock signal with a delay time equal to a delay time of a clock signal supplied from the clock supply source to the clock using circuit corresponding to the latch circuit is connected to the input terminal. The state of the latch circuit may be readable from an external output terminal.

In the present invention, the transition timing of the test signal supplied from the external test terminal is defined as
The logic value of the latch circuit at each timing when the test signal transitions is read out from the external output terminal by shifting from the external output terminal at predetermined timing steps over a predetermined time range. The magnitude of the skew of the clock supplied to the circuit can be determined.

[0022]

Embodiments of the present invention will be described below. In a preferred embodiment of the present invention, the clock skew of a plurality of clock-using circuits (a flip-flop, a latch, or any other circuit driven by a clock, a macro cell, a mega cell, or the like) may be selected. A latch circuit is provided in the vicinity of a predetermined clock using circuit for verification, and a data input terminal of the latch circuit has a delay time of a clock signal supplied from a clock supply source to the clock using circuit for verifying clock skew. A clock signal wiring wired so as to supply a clock signal with an equal delay time is configured to be connected, and a test signal from an external test terminal is commonly connected to an input terminal of the latch timing clock, The state of the latch circuit is read from an external output terminal.

An embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a diagram showing a configuration of an embodiment of the present invention. Referring to FIG. 1, a semiconductor integrated circuit device 100 includes a clock supply circuit (not shown) in the vicinity (side) of each of a plurality of flip-flops F / F-α, β, θ, and δ for verifying clock skew. And a skew monitoring dummy flip-flop F / F-1, 2, 3, and 4 receiving the supply of the clock CLK.

A plurality of dummy flip-flops F / F-
1, 2, 3, and 4 are connected to the clock signal CL with delay times equal to the delay times of the clock signals supplied to the flip-flops F / F-α, β, θ, and δ, respectively.
Clock signal wiring 1 wired to supply K,
2, 3, and 4 are respectively connected.

A plurality of dummy flip-flops F /
A test signal from an external test terminal A is commonly connected to clock input terminals of F-1, 2, 3, and 4, and output terminals of a plurality of dummy flip-flops F / F-1 to 4 are
They are connected to output terminals O1 to O4, respectively.

Dummy flip-flops F / F-1,
2, 3, and 4 are preferably the same for the capacitance of the input terminal, the input impedance, and the like. The dummy flip-flops F / F-1, 2, 3, and 4 may have the same configuration as the flip-flops F / F-α, β, θ, and δ. In FIG. 1, the flip-flop F / F
-Α, β, θ, δ are rising edges of the clock,
Although shown as a D-type flip-flop configured to take in data, it goes without saying that the dummy flip-flop is not limited to the D-type flip-flop in the present invention.

In FIG. 1, reference numerals 101 and 102 denote circuit blocks in the semiconductor integrated circuit device 100. In the clock tree of each of the circuit blocks 101 and 102, the clock skew is designed to fall within a standard value at the time of design. Is laid out.

At the time of testing the semiconductor integrated circuit device 100,
A test signal A supplied from an LSI tester or the like to an external test terminal A is changed from a low level to a high level in a certain test cycle, and the timing of the transition edge is changed by a predetermined timing step from a reference clock that defines the test cycle. It shifts every time.

The setting of the signal waveform of the test signal A and the timing of the rising edge (see FIG.
The setting and change of (see) are performed by the test program executed on the LSI tester,
And in a known manner of programming a timing generator.

At the rising edge of the test signal A, in the dummy flip-flops F / F-1, 2, 3, and 4 for latching the clock signal input to the data input terminal,
By reading the logical value of the test signal A taken at each timing step from the external terminals O1, O2, O3 and O4 to the LSI tester, each dummy flip-flop F
/ F-1, 2, 3, and 4 detect the leading (or lagging) phase of each clock signal of the clock signal supplied to each of the clock signals, so that the magnitude of the clock skew can be determined.

An example of a clock skew verification method according to an embodiment of the present invention will be described below.
In the semiconductor integrated circuit device according to the present invention, the flip-flop F / F-α,
β, θ, δ, dummy flip-flop F / F-1,
The skew of all the clock signals distributed to 2, 3, and 4 is adjusted (at design time, the skew is within a specified value).

At the time of layout of the semiconductor integrated circuit device 100, for each of a plurality of flip-flops which need to supply a clock signal, for example, a flip-flop having a minimum delay time and a flip-flop having a maximum delay time are specified in each tree. Every two flip-flops F / F-α of minimum delay and maximum delay,
Dummy flip-flops F / F-1 and 3 are arranged in the vicinity of β, and dummy flip-flops F / F-2 in the vicinity of two flip-flops F / F-θ and δ having the minimum delay and the maximum delay. , 4 are arranged respectively.

The skew of test signals distributed from the test terminal A to the dummy flip-flops F / F-1, 2, 3, and 4 is also adjusted at the time of design. That is, from the test terminal A, the dummy flip-flop F /
The skew in each signal wiring tree up to the input terminals of F-1 to F-4 is adjusted so as to be within the standard value.

After the manufacture of the semiconductor integrated circuit device 100, LS
An external clock is supplied from the driver of the I tester to the semiconductor integrated circuit device 100 under test, and the timing of the rising edge of the test signal supplied to the test terminal A is set in a predetermined time range (for example, (The minimum resolution of the timing generator or its integral multiple).

From the driver of the LSI tester to the semiconductor integrated circuit device 100, in a certain test cycle, a test signal which rises with a predetermined delay from a reference clock (a reference clock inside the LSI tester) defining the test cycle is externally supplied. Supply to test terminal A,
While the test signal is kept at the high level (the signal may be dropped to the low level but is not changed to the high level again), the dummy flip-flops F / F-1, F2, F3, F2, F3 and F3 in the test cycle or the subsequent test cycle. , 4
The values of the external terminals O1 to O4 to which the output terminals of
Read out to LSI tester. That is, the external terminals O1 to O
The value of “4” is compared with, for example, an expected value “0” by a comparator of the LSI tester, and the comparison result of the comparator is stored in a local memory or the like that stores a test vector via an error logic (error flag) that receives an output of the comparator. A known method is used.

Next, the semiconductor integrated circuit device 1 to be tested is
A test signal having a rising edge shifted from the previous timing by a predetermined timing step with respect to a reference clock defining a test cycle is input to a test terminal A of 00. In response to the application of the test signal, the dummy flip-flops F / F-1, 2, 3, 4
From the external output terminals O1 to O4,
The data is stored in a local memory or the like of the LSI tester. For example, when the output value of the external terminal (pin 1) is “0”, the LSI
The error flag value latching the comparison result of the tester comparator (comparing with the expected value “0”) is “0”, and when the output value of the external terminal is “1”, the error flag value is “1”. The value of the flag is stored in the local memory for each timing step that changes the transition edge of the test signal.

From the time-series data of the values of the external output terminals O1 to O4 stored in the local memory of the LSI tester, the rising edge of each clock distributed to the data input terminals of the dummy flip-flops F / F-1 to F-4 Can be detected at the minimum resolution level of the timing generator of the LSI tester.

FIG. 2 is a diagram for explaining the timing operation according to one embodiment of the present invention, where A is a test signal supplied from an LSI tester to an external test terminal A, and (1)
To (4) are dummy flip-flops F / F-1 to 4
FIG. 3 is a diagram showing signal waveforms of clock signals (clock signal wirings 1 to 4) supplied to data input terminals of FIG. At a point in time before the rising edge of the test signal A supplied to the clock input terminals of the dummy flip-flops F / F-1 to 4 through the setup time, the clock signal supplied to the clock input terminal becomes “0” (Low level). )), The value taken by the dummy flip-flop is “0”, and when the clock signal has transitioned to “1” (High level) at a time before the setup time before the rising edge of the test signal A, the dummy flip-flop is The flip-flop takes in the value “1”.

In FIG. 2, at the timing when the rising edge of the test signal A supplied to the clock input terminals of the dummy flip-flops F / F-1 to 4 is t1, all the dummy flip-flops take in "0". At the timing when the rising edge of the test signal A is t2, the dummy flip-flops F / F-1, 3 are "1".
At the timing when the rising edge of the test signal A is t3, the dummy flip-flop F / F-
1, 2, 3, and 4 take "1". As described above, by setting the step of changing the timing of the rising edge of the test signal A to the minimum resolution of the timing generator of the LSI tester, the dummy flip-flop F /
A transition edge (change point from “0” to “1”) of the clock signal supplied to F-1 to F-4 can be detected.

Next, a modification of the embodiment of the present invention will be described. As shown in FIG. 4, in one embodiment of the present invention, dummy flip-flops F / F-1,
Shift registers 2, 3, and 4 connect the output of the dummy flip-flop F / F-1 serially to the serial input terminal (SIN) of another dummy flip-flop F / F-3 when reading data. And a serial connection of the output of the dummy flip-flop F / F-3 to the serial input terminal (SIN) of another dummy flip-flop F / F-2. F / F-1 to F / F-4 are serially connected to form one shift register, the output terminal of the last-stage dummy flip-flop F / F-4 is connected to the output terminal O1, and the dummy flip-flop F / F-4 is connected to the output terminal O1. For example, in the example shown in FIG. 4, the data fetched by F-1 to F-4 is supplied from the output terminal O1 to the dummy flip-flops F / F-4, 2, 3, 1
In this order.

In this case, a test signal from the test terminal A can be used as a shift clock supplied to the shift register (dummy flip-flops F / F-1 to 4) at the time of data reading. Each of the dummy flip-flops F / F-1 to F-4 has a selector for selecting either a data input terminal or a signal from a serial input terminal.
The signal selected by the selector is latched and output. A selection signal (serial mode control signal) in the selector is supplied from an external control terminal, and is set to L during a test.
Set from SI tester.

FIG. 3 is a diagram showing the configuration of the second embodiment of the present invention. In a second preferred embodiment of the present invention, referring to FIG. 3, among a plurality of flip-flops, a plurality of flip-flops F / F-.alpha., .Beta., .Theta. A skew monitor dummy flip-flop F / F-1, 2, 3, 4 for receiving a clock CLK from a clock supply circuit (not shown) is provided near each of δ, and a dummy flip-flop F / F- The flip-flops F / F-α, β, θ, and δ are provided at clock input terminals 1, 2, 3, and 4, respectively.
, And a test signal from an external test terminal A is commonly connected to the data input terminals of the dummy flip-flops F / F-1, 2, 3, and 4. The transition edge of the test signal (data signal) supplied from the tester or the like to the external test terminal A is shifted by a predetermined timing step, and at each timing when the test signal transitions, the dummy flip-flops F / F-1, 2, 3,. 4 to read out the logical value taken in the dummy flip-flop F / F-
The magnitude of the clock skew in 1, 2, 3, and 4 can be determined.

In the above embodiment, the clock signal from the clock supply circuit is connected to the data input terminal and the clock input terminal of the dummy flip-flops F / F-1, 2, 3, and 4.
The test signals from the external test terminal A are connected to each other. In the second embodiment of the present invention,
A test signal from an external test terminal A and a clock signal from a clock supply circuit are connected to data input terminals and clock input terminals of the flip-flops F / F-1, 2, 3, and 4, respectively. Other configurations are the same as those of the above embodiment.

In the second embodiment of the present invention, the timing at which the test signal supplied to the data input terminals of the dummy flip-flops F / F-1, 2, 3, and 4 transitions is shifted, and・ Flip-flop F / F-
A clock signal input to clock input terminals 1, 2, 3, and 4 is used to read out a state when a signal (test signal) at a data input terminal is captured. The clock signal and the data signal (test signal) are read out. Are sequentially changed, and the timing of the transition edge of the clock signal (the timing from the reference clock of the LSI tester) is detected for each of the dummy flip-flops F / F-1, 2, 3, and 4. Things.

The timing operation according to the second embodiment of the present invention is the same as that shown in FIG. (A) of FIG.
Are dummy flip-flops F / F-1, 2, 3, 4
The test signals supplied as data signals to the data input terminals (1) to (4) of FIG. 2 are supplied to the clock input terminals of the dummy flip-flops F / F-1, 2, 3, and 4, respectively. A clock signal (clock signal of clock signal wirings 1 to 4). Control operation and clock skew in an LSI tester, such as control of the timing of a test signal supplied to an external test terminal A, and reading of logical values of dummy flip-flops F / F-1, 2, 3, and 4 from output terminals. Is basically the same as in the above embodiment.

In the first and second embodiments of the present invention described with reference to FIGS. 1 and 3, the output terminals of the dummy flip-flops are connected to dedicated output terminals O1 to O4. However, the present invention is not limited to such a configuration. For example, the output of the dummy flip-flop may not be output from the dedicated test terminal, but may be shared with the normal data output terminal. That is, the output buffer circuit connected to the normal data output terminal includes a selector for switching between the normal data output from the internal circuit and the output of the dummy flip-flop, and selects the output of the dummy flip-flop in the test mode. Thus, the output of the dummy flip-flop may be read from the normal output terminal.

[0047]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to explain the above-described embodiment of the present invention in more detail, an embodiment in which the present invention is applied to a specific circuit will be described with reference to the drawings.

FIG. 5 is a diagram for explaining an embodiment of the present invention, and shows an example of a circuit arrangement (layout) before arranging a dummy flip-flop according to the present invention.

Referring to FIG. 5, clock driver 1
06 to receive the clock supply from the
In each of the circuit blocks 105, a flip-flop (MIN) with the minimum delay time of the clock signal and a flip-flop (MAX) with the maximum delay time of the clock signal are specified from the path information of the clock signal wiring. In the example described below, a flip-flop with a minimum delay (MIN) and a flip-flop with a maximum delay (MAX) are used as flip-flops for verifying clock skew.
A flip-flop at a position corresponding to a predetermined delay time between the minimum and maximum delays, for example, an intermediate delay time, may be used for clock skew verification.

In one embodiment of the present invention, referring to FIG. 6, each circuit block 1 of the semiconductor integrated circuit device 100 will be described.
01-105, dummy flip-flops F / F-1, F / F-2,..., F / F- beside each of the minimum delay and maximum delay flip-flops (MIN, MAX).
9 and 10, and each dummy flip-flop F / F
A test signal input from a test terminal A is connected to clock input terminals -1 to 10 and distributed from a clock driver 106 to data input terminals (D) of dummy flip-flops F / F-1 to 10. The clock signal to be supplied is wired and connected so as to have the same delay time as the clock signal supplied to the flip-flops (MIN, MAX) with the minimum delay and the maximum delay in each circuit block.

Then, at the time of designing the semiconductor integrated circuit device 100, the dummy flip-flop F /
The skew is adjusted for the test signals distributed to the clock input terminals F-1 to F-10. In one embodiment of the present invention, the number of dummy flip-flops is
Since the number of dummy flip-flops corresponding to the minimum delay and the maximum delay per circuit block is as small as two, the number of dummy flip-flops F / F-1
The skew adjustment of the test signal distributed to the clock input terminals 10 to 10 is easier than the skew adjustment of the clock supplied to the flip-flop of the real circuit, and the deviation (variation) of the skew of the test signal can be suppressed to be small. it can. One embodiment of the present invention (the same applies to a second embodiment described later)
In this configuration, the measurement accuracy of the clock skew is improved by such a configuration.

In testing the semiconductor integrated circuit device 100, the timing of the rising edge of the test signal A applied to the external test terminal A from the driver of the LSI tester is shifted by the minimum resolution of the timing of the LSI tester or a predetermined multiple thereof. As a result, the phase of each clock distributed to the data input terminals of the dummy flip-flops F / F-1 to 10 is supplied to the clock terminal of the flip-flop having the minimum delay and maximum delay of the circuit block. The measured clock skew can be measured.

More specifically, similar to the embodiment described with reference to FIG. 1, dummy flip-flop F /
In F-1 to F-10, the flip-flops F / F-1 to F-1 to F-10 at the rising edge of the test signal supplied to the clock input terminal (transition from low level to high level)
The logic value of the clock signal (supplied from the clock driver 106) supplied to the data input terminal is taken in.

That is, flip-flops F / F-1 to 1
When the clock signal is at the low level (“0”) at the rising edge of the test signal A supplied to the clock input terminal of “0” (before the setup time), the flip-flop takes in “0” and outputs the test signal. When the clock signal is transitioning to “1” at the rising edge of A (before the setup time), the flip-flop captures “1”. For each rising edge of the test signal A, a dummy flip-flop F
By reading the value of / F-1 to 10 on the LSI tester side, the timing of the rising edge of the clock signal distributed to the flip-flops F / F-1 to 10 is changed to the timing of changing the rising edge of the test signal A. It can be specified in step (time width) units.

As described above, the value of the dummy flip-flops F / F-1 to 10 read from the output terminal (not shown) is compared with, for example, an expected value "0" by the comparator of the LSI tester as described above. Error flag value that latches the comparison result (when the expected value is “0”, the error flag value is “0” when the output terminal is “0” and “1” when the output terminal is “1”) Is stored in the local memory, and each rising edge of the test signal A is swept from the start timing to the end timing. Then, by reading the content stored in the local memory, the rising edge of the test signal A is Read the status of each dummy flip-flop for each timing,
The transition edge of the clock supplied to the dummy flip-flop can be detected at the minimum timing resolution level of the LSI tester. Note that the capture of the output value of the device under test is not limited to the above method.
An optimal method is used according to an architecture specific to the SI tester.

FIG. 7 is a diagram showing the timing operation of one embodiment of the present invention. Referring to FIG. 7, A is a dummy
The test signals are input to the clock input terminals of the flip-flops F / F-1 to 10, and (1) to (10) are supplied to the data input terminals of the dummy flip-flops F / F-1 to 10. This is a clock signal. At the rising timing t1 of the test signal A, all of the dummy flip-flops F / F-1 to 10 capture "0", and at the rising timing t2 of the test signal A, the dummy flip-flops F / F-1 to 10 Captures "1".

As described with reference to FIG. 4, in one embodiment of the present invention, the dummy flip-flop F
/ F-1 to 10 form a shift register by serially connecting the output of the dummy flip-flop F / F-1 to the data input terminal of another dummy flip-flop at the time of data reading. The dummy flip-flops 1 to 10 may constitute one shift register, and data may be sequentially read from the output of the last-stage dummy flip-flop. When the number of dummy flip-flops is on the order of several tens or hundreds, an increase in the number of dedicated test terminals of the semiconductor integrated circuit device can be suppressed by employing a serial chain configuration.

The output terminal of the dummy flip-flop is not connected to the dedicated output terminal, but is shared with the normal data output terminal via a selector or the like, and the output of the dummy flip-flop is output in parallel. Of course, it is good.

In one embodiment of the present invention, after measuring the magnitude of the clock skew, the delay time may be adjusted by, for example, a variable delay circuit provided in the clock path of the clock driver to adjust the clock skew. An arbitrary circuit configuration is used as the clock skew adjustment circuit. Further, it is needless to say that a circuit for adjusting clock skew between circuit blocks may be provided.

Circuit block 101 in FIGS. 5 and 6
The adjustment of the clock skew of steps 105 to 105 is described below. When designing a semiconductor integrated circuit device, the adjustment of clock skew by a timing analysis tool is performed independently for each circuit block, and then the clock skew between circuit blocks is adjusted. Adjustment may be performed. In order for data transfer and the like to be correctly performed between circuit blocks, it is necessary to adjust clock skew also between circuit blocks. In this case, performing the timing analysis on all the circuit blocks 101 to 105 at once requires a large-scale analysis tool, which is not practical in terms of the amount of data to be processed, the amount of calculation, and the like. Therefore, the circuit is divided into a plurality of circuit blocks, and timing analysis is performed in circuit block units.

According to the present invention, when designing a semiconductor integrated circuit device, for a plurality of circuit blocks in which clock skew adjustment by a timing analysis tool is performed independently for each block, the minimum delay flip-flop (MIN) and the maximum The clock skew of the delay flip-flop (MAX) can be measured after the manufacture of the semiconductor integrated circuit device, so that the clock skew between circuit blocks can be corrected, It is possible to avoid a malfunction caused by clock skew at the time of data transfer between the devices.

Next, a second embodiment of the present invention will be described. The second embodiment of the present invention is the same as the second embodiment of the present invention described above.
This corresponds to the first embodiment. In the second embodiment of the present invention, the circuit arrangement shown in FIG.
As shown in the figure, in each of the circuit blocks 101 to 105 receiving the supply of the clock from the clock driver 106, the dummy flip-flops F / F-1 to F / F-1 to 1 are arranged beside the flip-flops having the minimum delay and the maximum delay, respectively.
10 and dummy flip-flops F / F-1 to 1
A test signal input from a test terminal A is connected to a data input terminal (D) of the dummy flip-flop F / F-1 to a clock input terminal of a dummy flip-flop F / F-1 to 10. The signals are wired so as to have the same delay time as the clock signal supplied to each of the minimum delay and maximum delay flip-flops.

In the second embodiment of the present invention, as in the previous embodiment, dummy flip-flops F / F-1 to F / F-1 are connected.
0, the edge of the test signal supplied to the data input terminal is shifted, and the dummy flip-flops F / F-1 to F / F-1 are shifted.
The clock signal input to the clock input terminal of 0 is used to read the state when the value of the data signal (test signal) at the data input terminal is captured. That is, the timing difference between the clock signal, the data signal (test signal) and the rising edge is changed, and the
By reading the state taken into the flip-flops F / F-1 to 10, the dummy flip-flops F / F-1 to
Timing of transition edge of clock signal supplied to F-1 to 10 (phase from reference clock of LSI tester)
Is to be detected. The timing operation of the second embodiment of the present invention is the same as that shown in FIG. In FIG. 7, (A) is a test signal, and (1) to (10) are clock signals supplied to the clock input terminals of the dummy flip-flops F / F-1 to 10. In the second embodiment of the present invention, the control operation in the LSI tester is the same as in the above embodiment, and the description is omitted.

In each of the above embodiments, the dummy flip-flop may be configured so as to be inactivated and not operated except at the time of the test, thereby reducing power consumption.

The clock driver 106 may be provided with a phase locked loop (PLL) circuit for generating an internal clock by synchronizing the phase with an external clock.
In FIG. 5 and the like, the clock signal is separately distributed from the clock driver 106 to each circuit block. However, the clock signal supplied from the clock driver may be branched from one trunk line to each circuit block. Good.

In each of the above embodiments, the dummy
The timing of the transition edge of the clock signal supplied to the flip-flop can be measured from the outside, and the present invention can also be applied to applications such as externally measuring the propagation delay time of the clock signal wiring in the semiconductor integrated circuit device.

The drawings and the like referred to in the description of the above embodiment are as follows.
For the purpose of describing and exemplifying embodiments of the present invention,
It is to be understood that the invention is not intended to limit the invention, but that the invention includes various changes and modifications that may be made by those skilled in the art without departing from the scope of the appended claims.

[0068]

As described above, according to the present invention,
A clock skew monitor latch circuit is provided beside a clock using circuit for verifying clock skew, and a clock supplied to each latch circuit is sequentially changed by changing a timing of a transition edge of a test signal supplied from an external test terminal. In this configuration, the internal clock skew can be accurately measured, and the magnitude of the clock skew can be ranked.

Further, according to the present invention, in a clock tree or a circuit block in which clock skew is equalized, a flip-flop is provided with a simple configuration in which a dummy flip-flop is provided beside a flip-flop having a maximum delay and a minimum delay. The skew between the clock signals supplied to the clock input terminals of the semiconductor integrated circuit device can be accurately observed from the outside, and there is no particular limitation on the design method of the semiconductor integrated circuit device. It has a remarkable effect that it can be applied to integrated circuits for general purposes, and its practical value is extremely high.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of another embodiment of the present invention.

FIG. 4 is a diagram showing a modification of the embodiment of the present invention.

FIG. 5 is a diagram for explaining one embodiment of the present invention.

FIG. 6 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 7 is a timing chart for explaining the operation of one embodiment of the present invention.

FIG. 8 is a diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 9 is a diagram showing a conventional circuit for monitoring clock skew.

FIG. 10 is a diagram showing a configuration of a conventional clock skew variation observation circuit.

[Explanation of symbols]

 1 to 4 clock 11, 12 flip-flop 13 exclusive OR circuit 14 skew variation observation circuit 16 load increase / decrease circuit 18 sequence maintaining circuit 22 buffer 24 NOR circuit 26 delay buffer 28 latch circuit 34 shift register 100 semiconductor integrated circuit device 101 to 105 Circuit block 106 Clock driver A External test terminal F / F-1 to F / F-10 Dummy flip-flop O1 to O1 Output terminal

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat ゛ (Reference) H01L 21/822 H01L 27/04 9A001 H03K 5/13 F term (Reference) 2G032 AA04 AC03 AD06 AE08 AE09 AE12 AG07 AH04 AK14 5B079 BC02 CC04 CC12 DD08 DD13 5F038 CD06 CD09 DF14 DT04 DT05 DT12 EZ20 5F064 AA01 BB01 BB31 BB33 EE47 EE54 5J001 BB00 BB02 BB05 BB14 BB23 CC00 DD04 9A001 BB05 KK37 LL05

Claims (15)

[Claims] 1. A semiconductor integrated circuit device comprising a plurality of clock using circuits receiving a clock signal from a clock supply source, wherein the plurality of clock using circuits correspond to a predetermined clock using circuit among the plurality of clock using circuits. A latch circuit for clock skew monitoring in the vicinity thereof, and a delay time of a clock signal supplied from the clock supply source to the clock using circuit corresponding to the latch circuit at a data input terminal of the latch circuit. A clock signal line for supplying a clock signal with a delay time equal to that of the latch circuit is connected to a clock input terminal of the latch circuit.
A test signal line for supplying a test signal input from an external test terminal as a latch timing clock of the latch circuit is connected, and a state of the latch circuit is readable from an external output terminal. A semiconductor integrated circuit device characterized by the above-mentioned. 2. A semiconductor integrated circuit device comprising a plurality of clock using circuits receiving a clock signal from a clock supply source, wherein the plurality of clock using circuits correspond to a predetermined clock using circuit among the plurality of clock using circuits. A latch circuit for clock skew monitoring is provided in the vicinity thereof, and a test signal line for supplying a test signal input from an external test terminal to the latch circuit is connected to a data input terminal of the latch circuit. A clock input terminal of the latch circuit for supplying a clock signal to the clock using circuit corresponding to the latch circuit with a delay time equal to a delay time of a clock signal supplied from the clock supply source. Clock signal wiring is connected, and the state of the latch circuit can be read from an external output terminal. It is, the semiconductor integrated circuit device, characterized in that. 3. The timing at which the test signal supplied from the external test terminal transitions is shifted at predetermined timing steps over a predetermined time range, and at each timing at which the test signal transitions. 3. The skew of a clock supplied to the predetermined clock using circuit can be determined by reading a logical value of the latch circuit from the external output terminal. Semiconductor integrated circuit device. 4. A semiconductor integrated circuit device having a plurality of flip-flops for receiving and supplying data from a clock supply circuit and holding and outputting data, wherein the flip-flop is supplied to a clock input terminal of the flip-flop among the plurality of flip-flops. Clock skew monitoring dummy flip-flops are provided in the vicinity of each of the plurality of flip-flops selected as those that need to verify the skew of the clock signal, and a data input terminal of each of the dummy flip-flops ,
The dummy flip-flops are wired so as to supply a clock signal with a delay time equal to a delay time of a clock signal supplied from the clock supply circuit to each of the flip-flops disposed in the vicinity. Clock signal wiring is connected, a common test signal from an external test terminal is connected to the clock input terminal of each of the dummy flip-flops,
2. The semiconductor integrated circuit device according to claim 1, wherein an output of said dummy flip-flop is readable from an external output terminal. 5. The timing at which the test signal supplied from the external test terminal transitions is shifted at predetermined timing steps over a predetermined time range, and the test signal is input as a clock signal. In each of the dummy flip-flops, at each timing of the transition edge of the test signal, a logical value taken in by each of the dummy flip-flops is read out from the external output terminal and supplied to the plurality of dummy flip-flops. Detecting the timing of the transition edge of each clock signal to determine the magnitude of the clock skew supplied to the plurality of flip-flops for which the skew of the clock signal needs to be verified. 5. The semiconductor integrated circuit device according to 4. 6. A semiconductor integrated circuit device having a plurality of flip-flops for receiving and supplying data from a clock supply circuit and holding and outputting data, wherein the flip-flop is supplied to a clock input terminal of the flip-flop among the plurality of flip-flops. A clock skew monitor dummy flip-flop is provided in the vicinity of each of the plurality of flip-flops selected as those that need to verify the skew of the clock signal, and a clock input terminal of each of the dummy flip-flops is provided. The dummy flip-flops are wired so as to supply a clock signal to each of the flip-flops arranged in the vicinity with a delay time equal to a delay time of a clock signal supplied from the clock supply circuit. Clock signal wiring is connected The data input terminal of each dummy flip-flop is connected to a common test signal from an external test terminal, and the output of the dummy flip-flop can be read from the external output terminal. A semiconductor integrated circuit device characterized by the above-mentioned. 7. The timing of transition of the test signal supplied from the external test terminal is shifted at predetermined timing steps over a predetermined time range, and each timing of a transition edge of the test signal is shifted. Reading the logical value taken into each of the dummy flip-flops from an external output terminal to detect the timing of the transition edge of each clock signal supplied to the plurality of dummy flip-flops, and to determine the skew of the clock signal. 7. The semiconductor integrated circuit device according to claim 6, wherein the magnitude of the clock skew supplied to the plurality of flip-flops that needs to be verified can be determined. 8. A plurality of flip-flops receiving a clock from a clock supply circuit that receives an external clock and generates an internal clock, wherein the plurality of flip-flops have equal clock skew in each circuit block. In a semiconductor integrated circuit device designed and implemented, in one or a plurality of circuit blocks, a skew monitor for skew monitoring is provided near a flip-flop located at a minimum delay and a maximum delay of a clock signal among the plurality of flip-flops. A test signal from an external test terminal is commonly connected to clock input terminals of the first and second dummy flip-flops of the circuit blocks; A data input terminal receives the clock signal from the clock supply circuit and outputs the data from the clock input circuit. The clock signal wirings connected so as to have a delay time equal to the delay time of the flip-flop located at each of the delay and the maximum delay are connected to each other, and a test signal supplied from the external test terminal changes during a test. The first and second dummy flip-flops of the one or more circuit blocks are shifted at predetermined timing steps at predetermined timing steps over a predetermined time range. The magnitude of the clock skew in the first and second dummy flip-flops of all of the one or a plurality of circuit blocks can be determined by reading a logical value taken into the flip-flop from an external output terminal. And a semiconductor integrated circuit device. 9. A plurality of flip-flops receiving a clock from a clock supply circuit that receives an external clock and generates an internal clock, wherein the plurality of flip-flops have equal clock skew in each circuit block. In a semiconductor integrated circuit device designed and implemented, in one or a plurality of circuit blocks, a skew monitor for skew monitoring is provided near a flip-flop located at a minimum delay and a maximum delay of a clock signal among the plurality of flip-flops. A test signal from an external test terminal is commonly connected to data input terminals of the first and second dummy flip-flops of each of the circuit blocks; A clock input terminal is connected to the clock supply circuit from the clock supply circuit. The clock signal wirings connected so as to have a delay time equal to the delay time of the flip-flop located at each of the delay and the maximum delay are connected to each other, and a test signal supplied from the external test terminal changes during a test. The timing of the test signal is shifted at predetermined timing steps over a predetermined time range, and at each timing when the test signal transitions, the first and second circuit blocks of the one or more circuit blocks are changed.
By reading the logical value taken into the dummy flip-flop from the external output terminal, the first and second circuit blocks of all of the one or more circuit blocks are read out.
Wherein the magnitude of the clock skew in the dummy flip-flop can be determined. 10. The output of each of the plurality of dummy flip-flops is connected to a plurality of external output terminals, respectively, and when the data of the plurality of dummy flip-flops is read, the value held by each of the dummy flip-flops is:
10. The semiconductor integrated circuit device according to claim 4, wherein said plurality of external output terminals are configured to output in parallel. 11. A data read from said plurality of dummy flip-flops, said plurality of dummy flip-flops are serially connected to form a shift register, and an output terminal of a last-stage dummy flip-flop of said shift register. Is connected to one external output terminal and supplies a shift clock to the plurality of dummy flip-flops, so that the one external output terminal outputs the dummy flip-flop from the last dummy flip-flop to the first dummy flip-flop. 10. The semiconductor integrated circuit device according to claim 4, wherein the values held by each of the dummy flip-flops are serially output in the order of the flip-flops. 12. The skew monitor dummy flip-flop provided in the circuit block is provided near a flip-flop located between a minimum delay and a maximum delay of a clock signal. Or the semiconductor integrated circuit device according to 9. 13. A clock-using circuit receiving a clock signal from a clock supply source, wherein at least a timing at which a clock input to a clock input terminal of the clock-using circuit transitions is determined to be externally observed. A latch circuit is provided in the vicinity of one clock using circuit, wherein the latch circuit includes a clock signal having a delay time equal to a delay time of a clock signal supplied from the clock supply source to the one clock using circuit. A test signal input from an external test terminal is supplied to a data input terminal and a clock input terminal of the latch circuit, or to a clock input terminal and a data input terminal of the latch circuit. A semiconductor integrated circuit device, wherein a state of a latch circuit is readable from an external output terminal. 14. A clock skew verification method for a semiconductor integrated circuit device comprising a plurality of clock using circuits receiving a clock signal from a clock supply source, wherein the clock skew needs to be verified among the plurality of clock using circuits. A latch circuit is provided in the vicinity of each of a plurality of clock using circuits selected as a certain one, and a delay of a clock signal supplied from the clock supply source to each of the clock using circuits for which clock skew needs to be verified. A clock signal having a delay time equal to the time is supplied to each data input terminal of each of the latch circuits corresponding to each of the clock using circuits, and an external test terminal is commonly used for a clock input terminal of each of the latch circuits. The test signal from the external test terminal is connected to the latch The timing at which the test signal supplied from the external test terminal transitions is shifted at predetermined timing steps over a predetermined time range, and is taken into each of the latch circuits at each timing at which the test signal transitions. By reading the logical value to be output from the external output terminal, the timing at which the clock signal input to each of the latch circuits transitions is detected, whereby the clock signal is supplied to the plurality of clock using circuits that need to verify the clock skew. A clock skew verifying method for determining the order of magnitude of clock skew of clock signals. 15. A clock skew verification method for a semiconductor integrated circuit device having a plurality of clock using circuits receiving a clock signal supplied from a clock supply source, wherein the clock skew needs to be verified among the plurality of clock using circuits. A latch circuit is provided in the vicinity of each of a plurality of clock using circuits selected as a certain one, and a delay of a clock signal supplied from the clock supply source to each of the clock using circuits for which clock skew needs to be verified. A clock signal having a delay time equal to the time is supplied as a latch timing clock to a clock input terminal of each of the latch circuits corresponding to each of the clock using circuits, and a data input terminal of each of the latch circuits is connected to an external test circuit. The terminals are connected in common and the external test terminals The timing at which the supplied test signal transitions is shifted at predetermined timing steps over a predetermined time range, and at each timing step at which the test signal transitions, the logical value taken in each latch circuit is output to an external output terminal. , The timing at which the clock signal input to each of the latch circuits transitions is detected, whereby the clock skew of the clock signal supplied to the plurality of clock using circuits whose clock skew needs to be verified is detected. A clock skew verification method characterized in that the order of magnitude can be determined.