JP3527161B2 - Semiconductor integrated circuit device and clock skew verification method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit device capable of observing a clock skew in the circuit in the semiconductor integrated circuit and a method of verifying the clock skew.

[0002]

2. Description of the Related Art Recently, with the progress of miniaturization technology of semiconductor devices, the circuit scale integrated on one chip has been increasing, and semiconductor integrated circuit devices having a circuit scale exceeding 1 million gates have been manufactured. -It has been sold, and the operating frequency of the circuit is also increasing. With the increase in the circuit scale of the semiconductor integrated circuit device, in the semiconductor integrated circuit device,
The number of circuits using clocks (typically including flip-flops, latches, counters, shift registers, etc., as well as arbitrary circuits driven by clocks, cells, macros) also increases, The wiring length of the clock signal wiring that supplies the clock signal becomes long, and the clock propagation delay time due to the clock signal wiring length also largely depends on the circuit layout, and as a result, it is distributed from the clock supply source to each clock using circuit. The fluctuation of the time lag of the clock signal is also large.

In order to cause a semiconductor integrated circuit device having a plurality of clock using circuits driven by a clock signal serving as a reference of operation timing to perform a desired operation, clock skew in the clock using circuit in the semiconductor integrated circuit device is required. It is necessary to suppress (the time difference that occurs between clock signals when transmitting clock signals in a plurality of transmission systems) within a specified value. For example, when a synchronous circuit driven by a clock signal is operated in the minimum cycle, if the clock skew exceeds a specified value due to variations in the clock skew or the like, malfunction will occur.

Therefore, conventionally, in the design stage of a semiconductor integrated circuit, in order to minimize the difference in clock signal propagation time, a buffer for equalizing delays is optimally inserted in the clock signal wiring network, Design by the clock tree synthesis (CTS) method of laying out in a tree shape and distributing the clock signal to each clock using circuit,
In addition, the clock skew is minimized by using a layout design or the like in consideration of timing conditions with a timing analysis tool or the like.

By the way, even if a mask pattern is formed so as to reduce the clock skew in the layout stage of the semiconductor integrated circuit as described above, the capacitance which cannot be predicted at the time of designing before manufacturing due to variations due to process variations in semiconductor manufacturing. In some cases, the clock skew in the semiconductor integrated circuit device after manufacturing may deviate from the design value before manufacturing and increase due to the resistance or the like.

In a semiconductor integrated circuit device driven at a high-speed operating frequency, the presence of a clock skew on the order of hundreds of picoseconds and tens of picoseconds increases the possibility that the circuit malfunctions. After manufacturing the circuit device, it is extremely important to verify the clock skew.

[0007]

Some semiconductor integrated circuit devices having a circuit configuration for measuring the clock signal skew of a semiconductor chip have been proposed in the past. Among them, for example, in Japanese Unexamined Patent Publication No. 8-15380, as shown in FIG. 9, a flip-flop 1 connected to a clock signal wiring and receiving a clock signal CLK at a clock input terminal is provided.
The external measurement signal DATA is input to the respective data input terminals of the flip-flops 11 and 12, and the delay time of the external measurement signal to the flip-flop 11 and the delay time to the flip-flop 12 are equalized.
The output terminal of the flip-flop 11 and the flip-flop 12
Is connected to the input of the exclusive OR circuit (XOR) 13, and the external measurement signal DATA is changed at the resolution of the LSI tester to detect the change point of the output level of the exclusive OR circuit 13. Has proposed a configuration for measuring the skew of a clock signal.

However, the above-mentioned Japanese Patent Laid-Open No. 15380/1996.
The test circuit described in the publication has the following problems.

The first problem is that the flip-flop 11,
This means that extra design is required to equalize the delay time from the output end of 12 to each input end of the exclusive OR circuit (XOR) 13. On the contrary, from the output terminals of the flip-flops 11 and 12, the exclusive OR circuit (XO
If the signal propagation delay time to the input end of R) 13 is not equal, accurate clock skew cannot be measured. That is, the skew between the output ends of the flip-flops 11 and 12 and the input end of the exclusive OR circuit (XOR) 13 is suppressed to a particularly small value as compared with the clock skew between the two flip-flops 11 and 12. It is only possible to measure the skew of the clock signal.

The second problem is that one exclusive OR circuit (XOR) is provided for the two flip-flops 11 and 12.
13 is used, which means that the chip area is increased. That is, the internal circuit of the semiconductor integrated circuit device includes a large number of flip-flops that need to take clock skew into consideration.
According to the configuration described in Japanese Patent Publication No.
If one exclusive OR circuit (XOR) is prepared for each, the area of the test circuit increases and the chip area increases.

The third problem is that when the clock skew between the two flip-flops 11 and 12 is small, no pulse signal is output from the output terminal OUT. That is, when the clock skew is small and the time difference between the transition edges of the output signals of the flip-flops 11 and 12 is small, the output of the exclusive OR circuit (XOR) 13 is not inverted but remains at the original value, and the clock skew is increased. Therefore, a signal having a pulse width corresponding to is unable to be output, and the pulse signal cannot be observed from the output terminal OUT.

The fourth problem is that the flip-flop 11,
When a pulse signal having a pulse width corresponding to the skew of the clock input to 12 is output from the output terminal OUT,
It only gives the time information of the clock skew,
From this pulse signal, it is not possible to know which of the clocks input to the flip-flops 11 and 12 is in advance of the phase or which of the clocks is behind.

That is, since the ranking cannot be performed based on the magnitude of the clock skew, it is not possible to obtain information for determining which clock timing should be adjusted, and which clock is deviated among a plurality of clocks. , The clock skew cannot be readjusted properly. Therefore, when adjusting the clock skew, the phase of the clock input to the flip-flops 11 and 12 is adjusted by trial and error until the pulse signal does not appear from the output terminal OUT.

Further, for example, in Japanese Patent Laid-Open No. 9-292723, as shown in FIG. 10, an external clock or an internal clock is distributed to a predetermined number of internal clocks, and the distributed internal clock is further divided into a predetermined number of clocks. A clock tree to be distributed, a skew variation observing circuit 14 provided in a predetermined internal clock to detect a variation in skew between the internal clocks, and a predetermined internal clock provided in the skew variation observing circuit 14.
The load increasing / decreasing circuit 16 for increasing the load of the internal clock whose phase is relatively advanced among the internal clocks, and the skew variation observing circuit 14 sequentially provided from the external clock or the internal clock close to the internal clock source. A configuration including a sequence maintaining circuit 18 that fixes the detection state and fixes the load of the internal clock by the load increasing / decreasing circuit 16 is disclosed. The skew variation observing circuit 14 includes a NOR circuit 24 to which the internal clocks output from the plurality of buffers 22 are input, and a plurality of latch circuits 28 to which the output of the NOR circuit 24 is input to the enable terminal G. The internal clock output from 22 is delayed by the delay buffer 26, input to the data input terminal of the latch 28, and when the internal clock having a relatively advanced phase among the internal clocks rises, the output of the NOR circuit 24 becomes low level. All of the latch circuits 28 whose output is input to the enable input terminal G are turned off, and among the internal clocks delayed by the delay buffer 28, the clock relatively advanced in phase is held at the high level by the latch. The clocks that are delayed relative to each other are kept low level in the latch and 18 has an output in the number corresponding to the number of stages of the buffer 22 of the clock tree,
Each output is configured to include a shift register 34 that is commonly input to the NOR circuit 24 of the same set of skew variation observation circuits at the same stage.

As described above, the above-mentioned Japanese Patent Laid-Open No. 9-292723.
In the configuration disclosed in the publication, the clock skew variation in the clock tree is automatically detected, and the clock with the advanced phase increases the load to increase the delay amount and equalize the clock skew. But
The configuration is such that a delay buffer and a load increase / decrease circuit are added to the signal wiring of the clock tree of the internal clock, and such a configuration (configuration in which various load circuits are connected to the signal wiring of the clock tree) distributes the clock signal. On the contrary, it is difficult to adjust the clock skew at the clock input end of the clock using circuit. In addition, the above-mentioned JP-A-9
The configuration disclosed in Japanese Patent Publication No. 292723 is not configured to monitor the clock skew at the clock input end of the clock using circuit which receives the clock signal at each end (leaf) of the clock tree, and the clock There is also no provision for observing the clock skew at the clock input of the circuit used.

Further, for example, in Japanese Patent Laid-Open No. 8-15380, a feedback path is provided corresponding to a path for supplying a clock signal, and the delay time can be increased or decreased in each of the feedback path and the supply path. Equipped with a variable delay circuit configured to detect the phase shift of the transmitted clock signal, and a control circuit that adjusts the signal delay time in the variable delay circuit based on the phase shift detection result. There is disclosed a configuration of a clock skew correction circuit that corrects a phase shift of a clock signal in a clock distribution system based on the signal waveform. However, in the configuration described in the above-mentioned Japanese Patent Laid-Open No. 8-15380,
There is a design constraint that the clock supply path is designed according to a special layout of wiring the feedback path, which limits the design flexibility and cannot directly apply the design method such as the clock tree synthesis method. Is.

As described above, none of the proposals made in the past meet the demand for observing the clock skew of a semiconductor integrated circuit device having a high integration and a high operating frequency. At present, no design method for a semiconductor integrated circuit device, which has a function of making the clock skew of an internal node of the circuit device correct and observable from the outside, is provided at present. Therefore, if the semiconductor integrated circuit device product malfunctions due to clock skew,
It is impossible to observe the clock skew of the internal circuit from the outside, adjust it, and repair it.

Therefore, the present invention has been made as a result of intensive research conducted by the present inventor who has recognized the above-mentioned problems, and has been devised as a completely new one. The main purpose of the present invention is to distribute to a plurality of clock use circuits which require clock supply. It is an object of the present invention to provide a semiconductor integrated circuit device and a clock skew verification method that enable external observation of the magnitude of the generated clock skew. Other objects, advantages, features, etc. of the present invention will be immediately apparent to those skilled in the art from the following description of the embodiments.

[0019]

According to the present invention to achieve the above object, in a semiconductor integrated circuit device having a plurality of clock using circuits supplied with a clock signal from a clock supply source, among the plurality of clock using circuits, A clock skew monitor latch circuit is provided in the vicinity of a predetermined clock using circuit, and the data input terminal of the latch circuit is connected to the clock using circuit corresponding to the latch circuit. A clock signal wiring for supplying a clock signal with a delay time equal to the delay time of the clock signal supplied from the clock supply source is connected, and a clock input terminal of the latch circuit is input from an external test terminal. The test signal wiring for supplying the test signal as the latch timing clock of the latch circuit is connected. And, the state of the latch circuit is capable read from the external output terminal.

In the present invention, a test signal wiring for supplying a test signal input from an external test terminal to the latch circuit is connected to the data input terminal of the latch circuit, and the clock of the latch circuit is connected. A clock signal wiring for supplying a clock signal with a delay time equal to the delay time of the clock signal supplied from the clock supply source to the clock using circuit corresponding to the latch circuit is connected to the input end. The state of the latch circuit may be read from the external output terminal.

In the present invention, the timing at which the test signal supplied from the external test terminal changes is
Using the predetermined clock by shifting from the external output terminal the logical value of the latch circuit at each timing at which the test signal transitions by shifting the value at predetermined timing steps over a predetermined time range. The skew of the clock supplied to the circuit can be discriminated.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below. In a preferred embodiment of the present invention, the clock skew of a plurality of clock using circuits (flip-flops, latches, other arbitrary circuits driven by clocks, macro cells, mega cells, etc.) may be used. A latch circuit is provided in the vicinity of a predetermined clock using circuit for verification, and the delay time of the clock signal supplied from the clock supply source to the clock using circuit for verifying the clock skew is provided at the data input terminal of this latch circuit. It is configured to connect the clock signal wiring that is wired so as to supply the clock signal with an equal delay time, and the test signal from the external test terminal is commonly connected to the input end of the latch timing clock. The state of the latch circuit is read from the external output terminal.

An embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a diagram showing a configuration of an embodiment of the present invention. Referring to FIG. 1, the semiconductor integrated circuit device 100 includes a clock supply circuit (not shown) in the vicinity (side) of each of a plurality of flip-flops F / F-α, β, θ, and δ for verifying clock skew. It includes dummy flip-flops F / F-1, 2, 3, and 4 for skew monitor which are supplied with the clock CLK from

A plurality of dummy flip-flops F / F-
The data input terminals D of 1, 2, 3, 4 have a clock signal CL with a delay time equal to the delay time of the clock signals supplied to the flip-flops F / F-α, β, θ, δ.
Clock signal wiring 1 wired to supply K,
2, 3 and 4 are respectively connected.

A plurality of dummy flip-flops F /
The test signals from the external test terminal A are commonly connected to the clock input terminals of F-1, 2, 3, and 4, and the output terminals of the plurality of dummy flip-flops F / F-1 to 4 are
The output terminals O1 to O4 are respectively connected.

Dummy flip-flop F / F-1,
2, 3, and 4 are preferably the same with respect to the capacitance at the input end, the input impedance, and the like. The dummy flip-flops F / F-1, 2, 3, and 4 may have the same configuration as the flip-flops F / F-α, β, θ, and δ, respectively. In FIG. 1, the flip-flop F / F
-Α, β, θ, δ are the rising edges of the clock,
Although it is shown as a D-type flip-flop configured to capture data, it goes without saying that the dummy flip-flop is not limited to the D-type flip-flop in the present invention.

In FIG. 1, 101 and 102 represent circuit blocks in the semiconductor integrated circuit device 100, and the clock skew in the clock tree of each circuit block 101 and 102 is set to a standard value in advance at the time of design. It is supposed to be laid out.

At the time of testing the semiconductor integrated circuit device 100,
The test signal A supplied from the LSI tester or the like to the external test terminal A is transited from the Low level to the High level within a certain test cycle, and the timing of the transition edge is determined from a reference clock defining the test cycle at a predetermined timing step. It shifts in sequence for each.

The setting of the signal waveform of the test signal A and the timing of the rising edge (A in FIG.
The setting and change of (see) are performed by the formatter of the LSI tester, by the test program executed on the LSI tester.
And the known method of programming the timing generator.

At the rising edge of the test signal A, in the dummy flip-flops F / F-1, 2, 3, 4 which latch the clock signal input to the data input terminal,
By reading the logical value taken in at each timing step of the test signal A from the external terminals O1, O2, O3, and O4 to the LSI tester, each dummy flip-flop F
/ F-1, 2, 3 and 4, the phase advance (or delay) of each clock signal of the clock signals respectively supplied is detected, and the magnitude of the clock skew can be discriminated.

An example of the clock skew verification method according to the embodiment of the present invention will be described below.
In the semiconductor integrated circuit device according to the present invention, the flip-flop F / F-α,
β, θ, δ, dummy flip-flop F / F-1,
The skews of all the clock signals distributed to 2, 3, and 4 are adjusted (at designing, the skew is within a specified value).

When laying out the semiconductor integrated circuit device 100, a plurality of flip-flops that need to be supplied with a clock signal are identified in each tree, for example, the one having the smallest delay time and the one having the largest delay time. Every two flip-flops F / F-α with minimum delay and maximum delay,
Dummy flip-flops F / F-1 and 3 are arranged in the vicinity of β, and two dummy flip-flops F / F-θ and F-F-2 in the vicinity of δ are provided. Place 4 respectively.

The skew of the test signal distributed from the test terminal A to the dummy flip-flops F / F-1, 2, 3, and 4 is also adjusted at the time of design. That is, from the test terminal A to the dummy flip-flop F /
The skew in each signal wiring tree from the input terminals of F-1 to F-4 is adjusted so as to be within the standard value.

After manufacturing the semiconductor integrated circuit device 100, LS is performed.
An external clock is supplied from the driver of the I tester to the semiconductor integrated circuit device 100 to be tested, and the timing of the rising edge of the test signal supplied to the test terminal A is set to a predetermined timing step (for example, a predetermined timing range). The minimum resolution of the timing generator or its integral multiple).

From a driver of the LSI tester to the semiconductor integrated circuit device 100, in a certain test cycle, a test signal rising at a predetermined timing from a reference clock (reference clock inside the LSI tester) defining the test cycle is externally output. Supply to test terminal A,
In the test cycle or the subsequent test cycles, the dummy flip-flops F / F-1, 2, 3 are held while the test signal is kept at the high level (it may be dropped to the low level but not brought back to the high level). Four
The values of the external terminals O1 to O4 to which the output terminals of
Read to LSI tester. That is, the external terminals O1 to O
The value of 4 is compared with, for example, an expected value “0” by the comparator of the LSI tester, and the comparison result of the comparator is stored in a local memory or the like that stores the test vector via an error logic (error flag) that receives the output of the comparator. The well-known method is used.

Next, the semiconductor integrated circuit device 1 to be tested.
A test signal having a rising edge deviated by a predetermined timing step from the previous timing is input to the test terminal A of 00 with respect to the reference clock defining the test cycle. The dummy flip-flops F / F-1, 2, 3, 4 are also applied to the application of the test signal.
Read out the state (value) from the external output terminals O1 to O4,
It is stored in the local memory of the LSI tester. For example, if the output value of the external terminal (pin 1) is "0", the LSI
The value of the error flag that latches the comparison result of the comparator of the tester (compared with the expected value “0”) is “0”, and the value of the error flag is “1” when the output value of the external terminal is “1”. The value of the flag is stored in the local memory at each timing step that changes the transition edge of the test signal.

The rising edge of each clock distributed to the data input terminals of the dummy flip-flops F / F-1 to 4 from the time series data of the values of the external output terminals O1 to O4 stored in the local memory of the LSI tester. Can be detected at the minimum resolution level of the timing generator of the LSI tester.

FIG. 2 is a diagram for explaining the timing operation of the embodiment of the present invention, in which A is a test signal supplied from the LSI tester to the external test terminal A, (1).
To (4) are dummy flip-flops F / F-1 to 4
FIG. 6 is a diagram showing signal waveforms of clock signals (clock signal wirings 1 to 4) supplied to the data input terminal of FIG. At the time point before the setup time of the rising edge of the test signal A supplied to the clock input terminals of the dummy flip-flops F / F-1 to 4, the clock signal supplied to the clock input terminal is "0" (Low level). ), The value fetched by the dummy flip-flop is “0”, and when the clock signal is transited to “1” (High level) before the setup time before the rising edge of the test signal A, the dummy flip-flop is The flip-flop takes in the value "1".

In FIG. 2, in the timing when the rising edge of the test signal A supplied to the clock input terminals of the dummy flip-flops F / F-1 to 4 is t1, all the dummy flip-flops take in "0", At timing when the rising edge of the test signal A is t2, the dummy flip-flops F / F-1 and 3 are "1".
, And the dummy flip-flop F / F- at the timing when the rising edge of the test signal A is t3.
1, 2, 3, and 4 take in "1". In this way, by setting the step of changing the timing of the rising edge of the test signal A to the minimum resolution of the timing generator of the LSI tester, the dummy flip-flop F /
The transition edge (change point from "0" to "1") of the clock signals supplied to F-1 to F-4 can be detected.

Next, a modification of the embodiment of the present invention will be described. As shown in FIG. 4, in one embodiment of the present invention, the dummy flip-flop F / F-1,
When reading data, the reference numerals 2, 3 and 4 serially connect the output of the dummy flip-flop F / F-1 to the serial input terminal (SIN) of another dummy flip-flop F / F-3. And the output of the dummy flip-flop F / F-3 is serially connected to the serial input terminal (SIN) of another dummy flip-flop F / F-2. F / F-1 to 4 are serially connected to form one shift register, the output terminal of the final stage dummy flip-flop F / F-4 is connected to the output terminal O1, and the dummy flip-flop F / F-4 is connected. For example, in the example shown in FIG. 4, the data fetched in F-1 to F-4 is output from the output terminal O1 to the dummy flip-flops F / F-4, 2, 3, 1, 1.
The configuration may be such that serial reading is performed in this order.

In this case, the test signal from the test terminal A can be used as the shift clock supplied to the shift register (dummy flip-flops F / F-1 to 4) at the time of data reading. The dummy flip-flops F / F-1 to 4 are provided with a selector that selects either the signal from the data input terminal or the signal from the serial input terminal.
The signal selected by the selector is latched and output. The selection signal (serial mode control signal) in the selector is supplied from the external control terminal and is L
Set from SI tester.

FIG. 3 is a diagram showing the configuration of the second embodiment of the present invention. In a preferred second embodiment of the present invention, referring to FIG. 3, among a plurality of flip-flops, a plurality of flip-flops F / F-α, β, θ, which need to verify the skew of a clock signal, Dummy flip-flops F / F-1, 2, 3 and 4 for skew monitoring, which are supplied with a clock CLK from a clock supply circuit (not shown), are provided in the vicinity of δ respectively. Flip-flops F / F-α, β, θ, δ are provided at the clock input terminals of 1, 2, 3, and 4.
To the data input terminals of the dummy flip-flops F / F-1, 2, 3, and 4, and the test signal from the external test terminal A is commonly connected. The transition edge of the test signal (data signal) supplied from the tester or the like to the external test terminal A is shifted by a predetermined timing step, and the dummy flip-flops F / F-1, 2, 3, Dummy flip-flop F / F-
It is possible to determine the magnitude of the clock skew in 1, 2, 3, and 4.

In the above embodiment, the clock signal from the clock supply circuit is provided at the data input terminal and the clock input terminal of the dummy flip-flops F / F-1, 2, 3, and 4.
Although the test signals from the external test terminals A are respectively connected, in the second embodiment of the present invention, dummy
The test signal from the external test terminal A and the clock signal from the clock supply circuit are connected to the data input terminals and the clock input terminals of the flip-flops F / F-1, 2, 3, and 4, respectively. Other configurations are the same as those in the above embodiment.

In the second embodiment of the present invention, the transition timing of the test signal supplied to the data input terminals of the dummy flip-flops F / F-1, 2, 3 and 4 is shifted and the dummy・ Flip-flop F / F-
It is a clock signal input to the clock input terminals 1, 2, 3, 4 and reads out the state when the signal (test signal) at the data input terminal is taken in. The clock signal and the data signal (test signal) are read. The timing difference of the transition edge of the clock signal (timing from the reference clock of the LSI tester) is detected for each of the dummy flip-flops F / F-1, 2, 3, 4 by sequentially changing the timing difference of the transition edge of the clock signal. It is a thing.

The timing operation of the second embodiment of the present invention is the same as that shown in FIG. Figure 2 (A)
Is a dummy flip-flop F / F-1, 2, 3, 4
The test signals, which are supplied as data signals to the data input terminals of the above, (1) to (4) in FIG. 2, are supplied to the clock input terminals of the dummy flip-flops F / F-1, 2, 3, and 4, respectively. It is a clock signal (clock signal of the clock signal wirings 1 to 4). Control operation and clock skew in an LSI tester such as control of timing of a test signal supplied to the external test terminal A and reading of logical values of the dummy flip-flops F / F-1, 2, 3, and 4 from output terminals. The verification method of is basically the same as that of the above-mentioned embodiment.

In the first and second embodiments of the present invention described with reference to FIGS. 1 and 3, the output terminals of the dummy flip-flops are connected to the dedicated output terminals O1 to O4. However, the present invention is not limited to such a configuration. For example, it goes without saying that the output of the dummy flip-flop may be shared with the output terminal for normal data instead of being output from the test-dedicated terminal. That is, the output buffer circuit connected to the normal data output terminal has a selector that switches between the normal data output from the internal circuit and the output of the dummy flip-flop, and selects the output of the dummy flip-flop in the test mode. Then, the output of the dummy flip-flop may be read from the normal output terminal.

[0047]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to describe the above-described embodiment of the present invention in more detail, an embodiment in which the present invention is applied to a specific circuit will be described with reference to the drawings.

FIG. 5 is a diagram for explaining one embodiment of the present invention and is a diagram showing an example of a circuit arrangement (layout) before the dummy flip-flop according to the present invention is arranged.

Referring to FIG. 5, the clock driver 1
Circuit block 101 to which the clock is supplied from 06
In each circuit block 105, a flip-flop (MIN) having the minimum delay time of the clock signal and a flip-flop (MAX) having the maximum delay time of the clock signal are specified from the route information of the clock signal wiring. In the example described below, the minimum delay flip-flop (MIN) and the maximum delay flip-flop (MAX) are used as the flip-flops for verifying the clock skew.
A flip-flop at a position corresponding to a predetermined delay time between the minimum and maximum delays, for example, an intermediate delay time may be used for verifying the clock skew.

In one embodiment of the present invention, referring to FIG. 6, each circuit block 1 of the semiconductor integrated circuit device 100 is shown.
In 01 to 105, dummy flip-flops F / F-1, F / F-2, ..., F / F- are provided beside the minimum delay and maximum delay flip-flops (MIN, MAX), respectively.
9 and 10 are arranged and each dummy flip-flop F / F
The test signal input from the test terminal A is connected to the clock input terminals of -1 to 10, and the clock driver 106 distributes the data input terminals (D) of the dummy flip-flops F / F-1 to 10. The clock signals are connected to each circuit block so that the delay times of the clock signals are the same as those of the clock signals supplied to the flip-flops (MIN, MAX) having the minimum delay and the maximum delay, respectively.

Then, when designing the semiconductor integrated circuit device 100, the dummy flip-flop F /
The skew of the test signal distributed to the clock input terminals of F-1 to 10 is adjusted. In the embodiment of the present invention, the number of dummy flip-flops is
Since the number of dummy flip-flops corresponding to the minimum delay and the maximum delay is one circuit block, which is a small number, from the test terminal A to the dummy flip-flop F / F-1.
The skew adjustment of the test signal distributed to the clock input terminals of 10 to 10 is easier than the skew adjustment of the clock supplied to the flip-flop of the actual circuit, and the deviation (variation) of the skew of the test signal can be suppressed to be small. it can. One embodiment of the present invention (same for the second embodiment described later)
In the above configuration, the clock skew measurement accuracy is improved by such a configuration.

When testing the semiconductor integrated circuit device 100, the timing of the rising edge of the test signal A applied to the external test terminal A from the driver of the LSI tester is shifted by the minimum resolution of the timing of the LSI tester or a predetermined multiple thereof. As a result, the phase advance of each clock distributed to the data input terminals of the dummy flip-flops F / F-1 to 10 is supplied to the clock terminal of the flip-flop having the minimum delay and the maximum delay of the circuit block. The clock skew can be measured.

More specifically, the dummy flip-flop F / is similar to the embodiment described with reference to FIG.
In F-1 to 10, flip-flops F / F-1 to 10 are used at the rising edge (transition from Low level to High level) of the test signal supplied to the clock input terminal.
The logical value of the clock signal (supplied from the clock driver 106) supplied to the data input terminal of the is acquired.

That is, the flip-flops F / F-1 to 1
When the clock signal is at the low level (“0”) at the time of the rising edge of the test signal A supplied to the clock input terminal of 0 (before the setup time), the flip-flop fetches “0” and outputs the test signal. When the clock signal transitions to "1" at the time of the rising edge of A (before the setup time), the flip-flop takes in "1". For each rising edge of test signal A, a dummy flip-flop F
By reading the values of / F-1 to 10 to the LSI tester side, the timing of the rising edge of the clock signal distributed to the flip-flops F / F-1 to 10 is changed to the timing of changing the rising edge of the test signal A. It can be specified in units of steps (time width).

The values of the dummy flip-flops F / F-1 to 10 read out from the output terminal (not shown) are compared with, for example, the expected value "0" by the comparator of the LSI tester, as described above, and the value of the comparator. Value of the error flag that latches the comparison result (when the expected value is "0", the value of the error flag is "0" when the output terminal is "0", and "1" when the output terminal is "1") Is stored in the local memory, each rising edge of the test signal A is swept from the start timing to the end timing, and then the contents stored in the local memory are read out to detect the rising edge of the test signal A. Read the state of each dummy flip-flop for each timing,
The transition timing of the clock supplied to the dummy flip-flop can be detected at the minimum timing resolution level of the LSI tester. Note that the acquisition of the output value of the device under test is not limited to the above method, and L
An optimum method is used according to the architecture unique to the SI tester.

FIG. 7 is a diagram showing a timing operation of an embodiment of the present invention. Referring to FIG. 7, A is a dummy
The test signals (1) to (10) are supplied to the clock input terminals of the flip-flops F / F-1 to 10, and (1) to (10) are supplied to the data input terminals of the dummy flip-flops F / F-1 to 10. It is a clock signal. At the rising timing t1 of the test signal A, all of the dummy flip-flops F / F-1 to 10 fetch "0", and at the rising timing t2 of the test signal A, the dummy flip-flops F / F-1 to 10. Takes in "1".

As described with reference to FIG. 4, in one embodiment of the present invention, the dummy flip-flop F
/ F-1 to 10 connect serially the output of the dummy flip-flop F / F-1 to the data input terminal of another dummy flip-flop at the time of data reading to form a shift register. Alternatively, the dummy flip-flops 1 to 10 may constitute one shift register, and the data may be sequentially read from the output of the dummy flip-flop at the final stage. When the number of dummy flip-flops is on the order of tens or hundreds, the serial chain configuration can prevent an increase in the number of dedicated test terminals of the semiconductor integrated circuit device.

The output terminal of the dummy flip-flop is not connected to the dedicated output terminal but is shared with the output terminal of the normal data through a selector or the like, and the output of the dummy flip-flop is output in parallel. Of course, it is also good.

In one embodiment of the present invention, the clock skew may be adjusted by measuring the magnitude of the clock skew and then adjusting the delay time with a variable delay circuit provided in the clock path of the clock driver, for example. An arbitrary circuit configuration is used as the clock skew adjustment circuit. Further, it goes without saying that a circuit for adjusting the clock skew between the circuit blocks may be provided.

Circuit block 101 in FIGS. 5 and 6
To explain the clock skew adjustments of to 105, when designing the semiconductor integrated circuit device, the clock skew adjustment is independently performed for each circuit block by the timing analysis tool, and then the clock skew between the circuit blocks is adjusted. Adjustment may be performed. In order for data transfer and the like to be properly performed between the circuit blocks, it is necessary to adjust the clock skew between the circuit blocks. In this case, performing the timing analysis on all the circuit blocks 101 to 105 at once requires a large-scale analysis tool, which is not practical in terms of the amount of data to be processed, the amount of calculation, and the like. Therefore, the circuit is divided into a plurality of circuit blocks and the timing analysis is performed for each circuit block.

According to the present invention, a minimum delay flip-flop (MIN) and a maximum delay in a circuit block are set for a plurality of circuit blocks in which clock skew adjustment is independently performed for each block by a timing analysis tool when designing a semiconductor integrated circuit device. It is possible to measure the clock skew of the delay flip-flop (MAX) after manufacturing the semiconductor integrated circuit device. Therefore, it is possible to correct the clock skew between the circuit blocks. It is possible to avoid a malfunction caused by clock skew when data is exchanged between them.

Next, a second embodiment of the present invention will be described. The second embodiment of the present invention is the second embodiment of the present invention described above.
It corresponds to the embodiment of. In the second embodiment of the present invention, the circuit arrangement shown in FIG.
As shown in FIG. 5, in each circuit block of the circuit blocks 101 to 105 to which a clock is supplied from the clock driver 106, dummy flip-flops F / F-1 to F / F-1 to
10 are arranged and the dummy flip-flops F / F-1 to
The data input terminal (D) of 10 is connected to the test signal input from the test terminal A, and the clock input terminals of the dummy flip-flops F / F-1 to 10 are clocks distributed from the clock driver 106. The signals are wired so that the delay times are the same as those of the clock signals supplied to the flip-flops having the minimum delay and the maximum delay, respectively.

Also in the second embodiment of the present invention, the dummy flip-flops F / F-1 to 1 are used as in the above-mentioned embodiments.
The edge of the test signal supplied to the data input terminal of 0 is shifted, and the dummy flip-flops F / F-1 to 1
With a clock signal input to the clock input terminal of 0, the state when the value of the data signal (test signal) at the data input terminal is captured is read. That is, the timing difference between the clock signal and the data signal (test signal) and the rising edge is changed to change the dummy signal at each timing.
By reading the state stored in the flip-flops F / F-1 to 10, the dummy flip-flop F / F /
Timing of transition edge of clock signal supplied to F-1 to 10 (phase from reference clock of LSI tester)
Is to detect. The timing operation of the second embodiment of the present invention is the same as that shown in FIG. In FIG. 7, (A) is a test signal, and (1) to (10) are clock signals supplied to clock input terminals of the dummy flip-flops F / F-1 to 10. In the second embodiment of the present invention, the control operation in the LSI tester is the same as that of the above-mentioned embodiment, and the description thereof will be omitted.

In each of the above embodiments, the dummy flip-flop may be configured to be inactivated and not operated except during the test so as to reduce the power consumption.

Further, the clock driver 106 may be provided with a phase-locked loop (PLL) circuit for generating an internal clock in phase synchronization with an external clock.
In FIG. 5 and the like, the clock signal is separately distributed from the clock driver 106 to each circuit block, but the clock signal supplied from the clock driver may be branched from one trunk line to each circuit block. Good.

In each of the above embodiments, the dummy
The timing of the transition edge of the clock signal supplied to the flip-flop can be externally measured, and the present invention can be applied to the purpose of externally measuring the propagation delay time of the clock signal wiring in the semiconductor integrated circuit device.

The drawings and the like referred to in the description of the above embodiments are
For the purpose of explaining and illustrating the embodiment of the present invention,
It should be understood that the present invention is not intended to limit the present invention and includes various variations and modifications which can be made by those skilled in the art within the scope of the principles of the claims.

[0068]

As described above, according to the present invention,
A clock skew monitoring latch circuit is provided next to the clock using circuit that verifies the clock skew, and the clock supplied to each latch circuit is changed by sequentially changing the timing of the transition edge of the test signal supplied from the external test terminal. With the configuration for detecting the phase of, the internal clock skew can be accurately measured, and the magnitude of the clock skew can be ranked.

Further, according to the present invention, in the clock tree or the circuit block in which the clock skews are equalized, the flip-flops are provided by the simple structure that the dummy flip-flops are provided beside the flip-flops having the maximum delay and the minimum delay. In addition to the effect that the skew between the clock signals supplied to the clock input terminals of the semiconductor integrated circuit device can be accurately observed from the outside, the semiconductor integrated circuit device design method is not restricted by a special constraint. It has a remarkable effect that it can be applied to an integrated circuit in a versatile manner, and its practical value is extremely high.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a timing diagram showing the operation of the embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of another embodiment of the present invention.

FIG. 4 is a diagram showing a modification of the embodiment of the present invention.

FIG. 5 is a diagram for explaining an example of the present invention.

FIG. 6 is a diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 7 is a timing diagram illustrating the operation of the embodiment of the present invention.

FIG. 8 is a diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 9 is a diagram showing a circuit for monitoring a conventional clock skew.

FIG. 10 is a diagram showing a configuration of a conventional clock skew variation observing circuit.

[Explanation of symbols]

1 to 4 clocks 11,12 flip-flops 13 Exclusive OR circuit 14 Skew variation observation circuit 16 load change circuit 18 Sequence maintenance circuit 22 buffers 24 NOR circuit 26 delay buffer 28 Latch circuit 34 shift register 100 semiconductor integrated circuit device 101-105 circuit block 106 clock driver A External test terminal F / F-1 to F / F-10 Dummy flip-flop O1 to O1 output terminals

Claims (15)

(57) [Claims] 1. A semiconductor integrated circuit device comprising a plurality of clock using circuits which receive a clock signal from a clock supply source, wherein the plurality of clock using circuits are made to correspond to predetermined clock using circuits. A latch circuit for clock skew monitor is provided in the vicinity thereof, and a delay time of a clock signal supplied from the clock supply source to the clock using circuit corresponding to the latch circuit is provided at a data input terminal of the latch circuit. And a clock signal wiring for supplying a clock signal with a delay time equal to that of the latch signal is connected to the clock input terminal of the latch circuit.
A test signal wiring for supplying a test signal input from an external test terminal as a latch timing clock of the latch circuit is connected, and the state of the latch circuit can be read from an external output terminal. A characteristic semiconductor integrated circuit device. 2. A semiconductor integrated circuit device comprising a plurality of clock using circuits supplied with a clock signal from a clock supply source, wherein a plurality of clock using circuits are made to correspond to a predetermined predetermined clock using circuit. A latch circuit for clock skew monitor is provided in the vicinity thereof, and a test signal wiring for supplying a test signal input from an external test terminal to the latch circuit is connected to a data input terminal of the latch circuit. A clock input terminal of the latch circuit for supplying a clock signal to the clock using circuit corresponding to the latch circuit with a delay time equal to the delay time of the clock signal supplied from the clock supply source. The clock signal wiring is connected and the state of the latch circuit can be read from the external output terminal. It is, the semiconductor integrated circuit device, characterized in that. 3. The transition timing of the test signal supplied from the external test terminal is shifted for each predetermined timing step over a predetermined predetermined time range, and at each timing of the transition of the test signal. The skew value of the clock supplied to the predetermined clock using circuit can be determined by reading the logical value of the latch circuit from the external output terminal. Semiconductor integrated circuit device. 4. A semiconductor integrated circuit device comprising a plurality of flip-flops which receives a clock from a clock supply circuit and holds and outputs data, wherein the flip-flop is supplied to a clock input terminal of the plurality of flip-flops. A dummy flip-flop for clock skew monitoring is provided in the vicinity of each of the plurality of flip-flops that are selected as required to verify the skew of the clock signal. , The dummy flip-flops are arranged so as to supply a clock signal to each of the flip-flops arranged in the vicinity with a delay time equal to the delay time of the clock signal supplied from the clock supply circuit. The clock signal wiring consisting of The clock input terminal of the dummy flip-flop, a common test signal from the external test terminal are wired connected, the output of the dummy flip-flop is capable read from the external output terminal,
A semiconductor integrated circuit device characterized by the above. 5. The transition timing of the test signal supplied from the external test terminal is shifted at predetermined timing steps over a predetermined time range, and the test signal is input as a clock signal. In each of the dummy flip-flops, the logical value captured in each of the dummy flip-flops at each timing of the transition edge of the test signal is read from the external output terminal and is supplied to the plurality of dummy flip-flops. The timing of the transition edge of each clock signal is detected, and the magnitude of the clock skew supplied to the plurality of flip-flops for which it is necessary to verify the skew of the clock signal can be determined. 4. The semiconductor integrated circuit device according to 4. 6. A semiconductor integrated circuit device comprising a plurality of flip-flops which receives a clock from a clock supply circuit and holds and outputs data, wherein the flip-flop is supplied to a clock input terminal of the plurality of flip-flops. A dummy flip-flop for clock skew monitoring is provided in the vicinity of each of the plurality of flip-flops selected as those that need to verify the skew of the clock signal. , The dummy flip-flops are arranged so as to supply a clock signal to each of the flip-flops arranged in the vicinity with a delay time equal to the delay time of the clock signal supplied from the clock supply circuit. The clock signal wiring is The common test signal from the external test terminal is connected to the data input terminal of each dummy flip-flop by wiring, and the output of the dummy flip-flop can be read from the external output terminal. A characteristic semiconductor integrated circuit device. 7. The timing of transition of the test signal supplied from the external test terminal is shifted at predetermined timing steps over a predetermined time range, and each timing of transition edges of the test signal is changed. In, the logical value taken in by each dummy flip-flop is read from the external output terminal to detect the timing of the transition edge of each clock signal supplied to the plurality of dummy flip-flops, and the skew of the clock signal is detected. 7. The semiconductor integrated circuit device according to claim 6, wherein the magnitude of the clock skew supplied to the plurality of flip-flops that needs to be verified can be determined. 8. A plurality of flip-flops, which are supplied with a clock from a clock supply circuit for inputting an external clock and generating an internal clock, wherein the plurality of flip-flops are capable of equalizing clock skew in each circuit block. In one or a plurality of circuit blocks, a semiconductor integrated circuit device configured by performing a skew monitor for skew monitoring is provided in the vicinity of a flip-flop located at a minimum delay and a maximum delay of a clock signal among the plurality of flip-flops. Test signals from an external test terminal are commonly connected to clock input terminals of the first and second dummy flip-flops of the circuit blocks, respectively. At the data input end, the clock supply circuit is connected to the terminal of the circuit block. The clock signal wirings are wired so that the delay time is equal to the delay time of the flip-flops located at the delay and the maximum delay, respectively, and the test signal supplied from the external test terminal changes during the test. The timings of the first and second dummy flip-flops of the one or the plurality of circuit blocks are shifted at each timing when the test signal transitions. By reading the logical value captured in the external output terminal from the external output terminal, the magnitude of the clock skew in the first and second dummy flip-flops of all the circuit blocks of the one or the plurality of circuit blocks can be determined. A semiconductor integrated circuit device characterized by the above. 9. A plurality of flip-flops, which are supplied with a clock from a clock supply circuit for inputting an external clock to generate an internal clock, wherein the plurality of flip-flops are capable of equalizing clock skew in each circuit block. In one or a plurality of circuit blocks, a semiconductor integrated circuit device configured by performing a skew monitor for skew monitoring is provided in the vicinity of a flip-flop located at a minimum delay and a maximum delay of a clock signal among the plurality of flip-flops. A first dummy flip-flop and a second dummy flip-flop, respectively, and a test signal from an external test terminal is commonly connected to the data input terminals of the first and second dummy flip-flops of each circuit block, The clock input terminal is connected to the clock input terminal from the clock supply circuit. The clock signal wirings are wired so that the delay time is equal to the delay time of the flip-flops located at the delay and the maximum delay, respectively, and the test signal supplied from the external test terminal changes during the test. The timing to perform is shifted for each predetermined timing step over a predetermined predetermined time range, and at each timing when the test signal transitions, the first and second circuit blocks of the one or more circuit blocks are
By reading out the logical value taken in by the dummy flip-flop of the above from the external output terminal, the first and second circuit blocks of all the circuit blocks of the one or the plurality of circuit blocks are read.
The semiconductor integrated circuit device, wherein the size of the clock skew in the dummy flip-flop can be determined. 10. Outputs of the plurality of dummy flip-flops are respectively connected to a plurality of external output terminals, and when the data is read from the plurality of dummy flip-flops, the values held by the respective dummy flip-flops are:
10. The semiconductor integrated circuit device according to claim 4, wherein the semiconductor integrated circuit device is configured to output in parallel from the plurality of external output terminals. 11. When reading data from the plurality of dummy flip-flops, the plurality of dummy flip-flops are serially connected to form a shift register, and the output terminal of the dummy flip-flop at the final stage of the shift register. Are connected to one external output terminal, and a shift clock is supplied to the plurality of dummy flip-flops, so that the one external output terminal is connected to the dummy flip-flop of the final stage to the dummy of the first stage. 10. The semiconductor integrated circuit device according to claim 4, wherein the values held by the dummy flip-flops are serially output in the order of the flip-flops. 12. A clock signal having a minimum delay and a maximum delay.
The first flip-flop provided near the flip-flop to be placed,
10. In addition to the second dummy flip-flop, a third dummy flip-flop is provided near the flip-flop located between the minimum delay and the maximum delay of the clock signal. Semiconductor integrated circuit device. 13. A clock using circuit which receives a clock signal from a clock supply source, and at least it is determined to externally observe a transition timing of a clock input to a clock input terminal of the clock using circuit. A latch circuit is provided in the vicinity of one clock using circuit, and the latch circuit has a clock signal having a delay time equal to the delay time of the clock signal supplied from the clock supply source to the one clock using circuit. A test signal input from an external test terminal is supplied to a data input terminal and a clock input terminal of the latch circuit or a clock input terminal and a data input terminal of the latch circuit. A semiconductor integrated circuit device, wherein the state of a latch circuit can be read from an external output terminal. 14. A clock skew verification method for a semiconductor integrated circuit device comprising a plurality of clock use circuits supplied with a clock signal from a clock supply source, wherein the clock skew is required to be verified among the plurality of clock use circuits. A latch circuit is provided in the vicinity of each of the plurality of clock using circuits selected as a certain one, and the delay of the clock signal supplied from the clock supply source to each of the clock using circuits for which the clock skew needs to be verified. A clock signal having a delay time equal to the time is supplied to each data input terminal of each latch circuit corresponding to each clock using circuit, and an external test terminal is commonly provided to the clock input terminal of each latch circuit. The test signal from the external test terminal is connected to the latch timing Clock signal supplied from the external test terminal, the timing at which the test signal transitions from the external test terminal transitions is shifted at each predetermined timing step over a predetermined time range, and is captured by each latch circuit at each timing at which the test signal transitions. The logic value to be read is read from the external output terminal to detect the transition timing of the clock signal input to each of the latch circuits, and thereby the clock signal is supplied to the plurality of clock using circuits that need to be verified. A method for verifying clock skew, characterized in that it is possible to determine the order of magnitude of clock skew of a clock signal. 15. A clock skew verification method for a semiconductor integrated circuit device comprising a plurality of clock use circuits supplied with a clock signal from a clock supply source, wherein the clock skew among the plurality of clock use circuits is required to be verified. A latch circuit is provided in the vicinity of each of the plurality of clock using circuits selected as a certain one, and the delay of the clock signal supplied from the clock supply source to each of the clock using circuits for which the clock skew needs to be verified. A clock signal having a delay time equal to the time is supplied as a latch timing clock to a clock input terminal of each latch circuit corresponding to each clock using circuit, and an external test is supplied to a data input terminal of each latch circuit. The terminals are commonly connected, and the The timing at which the supplied test signal transitions is shifted for each predetermined timing step over a predetermined time range, and at each timing step at which the test signal transitions, the logical value captured in each latch circuit is output to an external output terminal. From the clock skews of the clock signals supplied to the plurality of clock using circuits that need to verify the clock skew by detecting the transition timing of the clock signal input to each latch circuit. A clock skew verification method characterized in that the order of sizes can be discriminated.