JPH0434703B2 - - Google Patents

Description

[Detailed Description of the Invention] (Field of the Invention) The present invention relates to a logic circuit testing device for testing logic circuits such as semiconductor integrated circuits, and particularly to a logic circuit testing device for testing logic circuits such as semiconductor integrated circuits. The present invention relates to a logic circuit testing device for testing these simultaneously.

(Background of the Invention) When performing a functional test of a logic circuit, a test pattern and an expected value pattern are generated from a pattern generator in a logic circuit testing device, and the test patterns are applied to the logic circuit under test. The quality of the logic circuit under test is determined by comparing the data output from the logic circuit under test with the expected value pattern.

As logic circuits become more complex and sophisticated, logic circuit testing equipment for testing them also needs to be complex and high-performance, and therefore extremely expensive. When testing logic circuits using such expensive test equipment, it is necessary to improve test efficiency and reduce test costs as much as possible. Therefore, it is desired that, for example, a plurality of logic circuits can be tested simultaneously with one logic circuit testing device.

FIG. 1 shows an example of a possible configuration when testing a plurality of random logic circuits using a conventional logic circuit testing device. The figure shows a case where two logic circuits are tested for simplicity.
Timing generator 1 provides a common clock signal to logic circuits 6 and 7 under test. The logic circuits under test 6 and 7 are thereby brought into operation. The pattern generator 2 generates a test pattern and an expected value pattern at a period determined by the timing generator 1. The test pattern is waveform-shaped by the formatter 3, outputted at a timing determined by the timing generator 1, and commonly applied to the logic circuits under test 6, 7. The output signals of the logic circuits under test 6 and 7 are applied to comparison circuits 4 and 5, respectively. Comparison circuits 4 and 5 are commonly given the expected value pattern from the pattern generator 2, and when the strobe signal is given from the timing generator 1, the output signal of the logic circuit under test is compared with the expected value pattern. , output the comparison result. In this way, if a plurality of logic circuits under test have the same characteristics, they can be tested simultaneously.

However, some actual logic circuits, such as microprocessors, have different internal operation start timings even if they belong to the same type. In other words, as shown in Figure 2, the delay time from the clock signal commonly applied to two microprocessors A and B to the address latch enable (ALE) signal output from each microprocessor is Ta，Tb
As in, they are different. In a microprocessor, various timing characteristics are defined using such a self-output signal, for example, ALE, as a reference clock. Therefore, the second
In the figure, when testing microprocessor A, the ALE rising time ta is used as a reference.
It is necessary to provide a test pattern that has a predetermined phase relationship from this reference time point. Furthermore, when testing microprocessor B, it is necessary to add a test pattern using time tb as a reference point.

In this way, when using a microprocessor or the like as a logic circuit under test, it is necessary to give a test pattern with a different phase to each logic circuit under test.
It is difficult to test multiple logic circuits under test at the same time. In other words, according to conventional logic circuit test equipment, in such a case, it is necessary to generate test patterns with different phases corresponding to the logic circuit under test, which requires the addition of complex hardware and the time required to execute the test. This required modification of the program and was therefore difficult to conduct in practice.

(Object of the Invention) The object of the invention is to correct the phase of the reference clock in a plurality of logic circuits under test so that they are the same, so that the plurality of logic circuits under test can be tested simultaneously using the same test pattern. The purpose of the present invention is to provide a logic circuit testing device.

(Summary of the Invention) According to the present invention, the same clock signal is commonly applied from a timing generator to a plurality of logic circuits under test, and the reference clock of the logic circuit under test is set in response to the clock signal. (For example, the above ALE
etc.) is thus measured for the logic circuit under test. Using the delay time of one logic circuit under test as a reference, the difference between the delay times of other logic circuits under test is determined, and a correction value obtained based on the difference is stored as a delay time correction value. The phase of the clock signal from the timing generator is delayed by the variable delay circuit based on this delay time correction value, and then applied to the corresponding logic circuit under test. By doing this, the reference clocks of a plurality of logic circuits under test are set to the same phase, and the internal states operate at the same timing. Therefore, it is possible to commonly apply the same test pattern to all logic circuits under test from the logic circuit testing apparatus and test them simultaneously.

(Embodiment of the Invention) FIG. 3 shows an example of a logic circuit testing device according to the present invention, and parts corresponding to those in FIG. 1 are given the same reference numerals. Although not shown, the entire logic circuit testing apparatus is controlled by a CPU. In this invention, the timing generator 1
The clock signal output from the variable delay circuit 8,
9 to the logic circuit under test 7.6. The delay times of variable delay circuits 8 and 9 are set by delay time correction values given by registers 10 and 11, respectively.

When testing a plurality of logic circuits 6 and 7 under test using this logic circuit testing apparatus, first the delay time of the reference clock of each logic circuit under test with respect to the clock signal output from the timing generator 1 is measured. In this measurement, the clock signal output from the timing generator 1 is applied to the logic circuit under test in the same phase by setting the variable delay circuits 8 and 9 to the same delay time, or by not passing through them. Then, the generation timing of the reference clock output as a result is monitored by comparison circuits 4 and 5. For example, the logic circuit under test 6, 7
are microprocessors A and B with the characteristics shown in FIG.
The clock signals shown in the figure are applied to microprocessors A and B at the same timing. Comparison circuit 4,
5, a strobe pulse from the timing generator 1 is applied repeatedly at high speed, and the microprocessors A and B are programmed at the timing of the strobe pulse.
monitors the ALE signal from and detects the point in time when the ALE signal switches from 0 to 1. In this way, the delay times Ta and Tb shown in FIG. 2 are measured.

The difference between the delay times based on the delay times Ta and Tb
Get Ts. It is clear that if the timing of the clock signal is corrected so that this time difference Ts becomes zero, the internal operation timings of the logic circuits under test 6 and 7 can be matched. Therefore, in this case, for example, the delay time correction value Ts is stored in the register 11. For this reason, as shown in FIG.
A clock signal delayed by Ts is applied. In this case, the correction value stored in the register 10 is 0, and the clock signal is not delayed by the variable delay circuit 8. However, the setting of the correction value by this logic circuit testing device is not limited to this, and in short, the setting of the correction value by the logic circuit testing device is not limited to this. Delay times may be set in both registers to compensate for the difference in delay time of the test logic circuit.

By correcting the phase of the clock signal output from the timing generator 1 in accordance with the characteristics of each logic circuit under test, for example, the fourth
As shown in the figure, the phases of the ALE signals output from microprocessors A and B are synchronized. Therefore, in this example, various test patterns can be commonly applied to the microprocessors A and B with the ALE rising time tb as a reference, and tests can be performed simultaneously.

In the above explanation, for simplicity, we have shown the case where two logic circuits under test are measured at the same time, but even when testing three or more logic circuits, they can be tested simultaneously based on the same idea. It is clear that it can be done. That is, a necessary number of variable delay circuits may be provided corresponding to the number of logic circuits under test, and necessary delay time correction values may be set for these variable delay circuits.

(Effects of the Invention) As described above, according to the present invention, various timing characteristics are defined by the reference clock output from the logic circuit under test itself, and the start timing of this reference clock differs depending on the logic circuit under test. Even in the worst case, a plurality of these can be tested at the same time, and therefore the testing efficiency can be significantly improved.

[Brief explanation of drawings]

Figure 1 is a block diagram showing the configuration when testing multiple logic circuits under test using a conventional logic circuit tester, and Figure 2 is a timing chart for explaining the operation of the logic circuit tester shown in Figure 1. Chaat, 3rd
The figure is a block diagram showing the configuration of the logic circuit testing apparatus according to the present invention, and FIG. 4 is a timing chart for explaining the operation of the logic circuit testing apparatus shown in FIG. 3. 1: Timing generator, 2: Pattern generator,
3: Formatsuta, 4, 5: Comparison circuit, 6, 7:
Logic circuit under test, 8, 9: Variable delay circuit, 10,
11: Register.

Claims (1)

[Claims] 1. A test pattern and an expected value pattern are generated from a pattern generator at a timing determined by a timing generator, and the test pattern is commonly applied to a plurality of logic circuits under test to In a logic circuit testing device that simultaneously tests the acceptability of multiple logic circuits under test by comparing the data output from the circuit with an expected value pattern, A. A measurement means for measuring the delay time of a reference clock generated from the logic circuit under test with respect to the clock signal by commonly applying the clock signal to the plurality of logic circuits under test; a storage means for storing a delay time correction value corresponding to each logic circuit under test set based on the measured value, and C a delay corresponding to each logic circuit under test determined by the delay time correction value from the storage means; Time,
A logic circuit testing device comprising: a plurality of variable delay circuits that additionally delay a clock signal provided by the timing generator and provide the delayed clock signal to each logic circuit under test.