KR100336907B1 - Memory testing apparatus - Google Patents

Abstract

A memory test apparatus for testing setup time (Tds) and hold time (Tdh) of a semiconductor memory is provided.

The pattern generator 2 is provided with two pattern data generators 22 for generating two test pattern data in one operation period, and the two timing clock generators 33 for generating two timing clocks in one operation cycle. Two NRZ waveforms are generated in the timing generator 3 and generated by the two test pattern data provided from the pattern generator and the two timing clocks provided from the timing generator, and applied to the MUT 9. The 2NRZ waveform generator 44 is provided in the waveform shaper 4. Two NRZ waveforms are alternately applied to the MUT, and the read response signal and the expected pattern signal are logically compared, and the setup time and hold time of the MUT are measured alternately.

Description

Memory test device {MEMORY TESTING APPARATUS}

The present invention relates, for example, to a memory (IC memory) constituted by a semiconductor integrated circuit (IC) or a memory test apparatus for testing various other semiconductor memories. Memory test that can accurately measure not only setup time (hereinafter referred to as "Tds") and hold time (hereinafter referred to as "Tdh") but also setup time and hold time of a high-speed semiconductor memory Relates to a device.

First, the basic configuration of a conventional memory test apparatus for testing various semiconductor memories will be described with reference to FIG. As shown, the memory test apparatus basically includes a tester processor 1, a pattern generator 2, a timing generator 3, a waveform shaper 4, a driver 5, and an analog level comparator 6 ), A pattern comparator 7 and a poor analysis memory 8.

The tester processor 1 is comprised by the computer system, and controls the whole test apparatus according to the test program which the user (programmer) made.

For example, a control signal (command) is given to each unit (device or circuit) of the test apparatus via the tester bus BUS. The pattern generator 2 starts generation of a pattern in response to a control signal (in this case, a test start command) provided from the tester processor 1, and the semiconductor memory under test (generally called a DUT or MUT) 9 A test signal (test pattern data) PTND, an address signal and a control signal of a predetermined pattern to be applied to the predetermined pattern, or an expected value signal (expected value pattern signal) EXP of a predetermined pattern applied to the pattern comparator 7 are generated. . Generally, ALPG (Algorithmic Pattern Generator) is used for this pattern generator 2. The ALPG is a pattern generator that generates a test pattern applied to a semiconductor memory (for example, an IC memory) by a calculation using a register having an internal arithmetic function.

The timing generator 3 generates a timing signal (pulse) in accordance with the timing information provided from the pattern generator 2 in order to take the test timing of the entire test apparatus, and the waveform shaper 4, the level comparator 6, To a pattern comparator (7). The waveform shaper 4 generates the test pattern signal PTN having the actual waveform by the test pattern data PTND provided from the pattern generator 2 and the timing signal provided from the timing generator 3, and generates a driver ( Through 5), the test pattern signal PTN is applied to the semiconductor memory under test (hereinafter referred to as MUT) 9.

8 shows a state (test cycle input cycle) of applying the test pattern signal PTN to the MUT 9. As shown in the figure, when inputting a test pattern signal to the MUT 9, the input / read (R / W) terminal of the MUT 9 is placed in the input state W and the driver 5 is output enabled ( Output enable) (output enable signal '/ OE' is applied) and the switch SW1 inserted at the output side is turned on, and the switch SW2 at the input side of the level comparator 6 is turned off. . In this state, the test pattern signal is input to the MUT 9 via the driver 5. In the present specification, a signal inverted in polarity is indicated with a forward slash symbol '/'. For example, the output enable signal '/ OE' indicates a signal inverting the polarity of the signal 'OE'.

After the input of the test pattern signal to the memory cells in the predetermined test range is finished, when the test pattern signal input to the MUT 9 is read (in a read cycle of the test pattern), the switch on the output side of the driver 5 ( SW1) is turned off (output disabled), the R / W terminal of the MUT 9 is set to read (R), and the level comparator 6 is input enabled (input enabled). Able signal '/ IE' is applied.) The switch SW2 on its input side is turned on. In this state, the test pattern signal input to the MUT 9 is read.

The test pattern signal (hereinafter referred to as a response signal) read out from the MUT 9 is provided with a signal level (usually a voltage level) in an analog level comparator 6, which is provided from a comparative reference voltage source (not shown). Compared with the reference voltage, it is determined whether or not it has a predetermined voltage level. This reference voltage is used when the reference voltage V0H (H logic reference voltage) used when the response signal from the MUT 9 is logic "1" and when the response signal from the MUT 9 is logic "0". There are two reference voltages V0L (L logic reference voltages) to be used. In either of the circuit examples shown, the logic "1" signal is passed when the level comparator 6 passes, and the logic "0" is bad. Signal is output.

The logic signal output from the level comparator 6 that is determined to have a predetermined voltage level is applied to the pattern comparator 7. The pattern comparator 7 performs a logical comparison between the logic signal in the level comparator 6 and the expected value pattern signal EXP provided from the pattern generator 2 to detect whether the two signals coincide. If the two comparators do not match, the pattern comparator 7 determines that the memory cell at the address of the MUT 9 read by the logic signal (response signal) is defective, and generates a defective (FAlL) signal indicating it. This failure signal is represented by a logic '1' signal and stored in the failure analysis memory 8. In general, a bad signal is stored at an address of a bad analysis memory 8 such as an address of a bad memory cell of the MUT 9.

On the other hand, when the logic signal and the expected pattern signal match, the pattern comparator 7 determines that the memory cell at the address of the MUT 9 read by the logic signal is normal, and generates a pass signal indicating the same. Occurs. This passing signal is represented by a logic '0' signal, and is usually not stored in the bad analysis memory 8.

At the end of the test, the bad signal stored in the bad analysis memory 8 is read, and it is determined whether or not the bad memory cell of the tested semiconductor memory can be repaired, for example.

In order to generate various control signals for performing the above-described operation, in the illustrated example, the pattern generator 2, the timing generator 3 and the waveform shaper 4 are referred to in this technical field as a table memory (hereinafter referred to as a table). 2A, 3A, and 4A, and required data are stored in advance from the tester processor 1 in these tables 2A, 3A, and 4A.

The user (programmer) considers the test pattern according to the performance specifications of the semiconductor memory to be tested and prepares a test program. At this time, the user has described in this example the data to be stored in advance in the tables 2A, 3A and 4A of the pattern generator 2, the timing generator 3 and the waveform shaper 4 in this test program. The data is preloaded into these tables 2A, 3A and 4A in the tester processor 1 before starting the test of the semiconductor memory.

The table 3A of the timing generator 3 is composed of a rate setting table memory and a clock setting table memory, and data relating to a test rate or test cycle is stored in the rate setting table memory. The clock setting table memory stores various timing data about the driver waveform (waveform of the test pattern signal PTN applied to the driver 5 from the waveform shaper 4). These timing data are organized to form a plurality of timing data groups, such as TS1 group, TS2 group,... The TSn group is prepared, the required group is read, and timing pulses of the set signal and the reset signal are generated.

In this example, ALPG is also used for the pattern generator 2, and in the table 2A, test pattern data to be applied to each pin from pin 1 of the MUT 9 to pin n (n is a positive integer). Is stored. In the table 4A of the waveform shaper 4, data relating to waveform setting such as waveform mode is stored, and the set generated from the test pattern data PTND generated from the pattern generator 2 and the timing generator 3, and The test pattern signal PTN having a predetermined waveform and timing is generated using the reset timing pulse and supplied to the driver 5.

Next, a description will be given of a method of checking whether or not an appropriate value is measured by measuring the setup time or hold time of a semiconductor memory, for example, an IC memory, by the memory test apparatus having the above-described configuration.

For example, various timing signals used when testing a static RAM (Static Random Access Mcmofy, hereinafter referred to as SRAM) of an IC memory are determined with respect to a reference clock as shown in FIG. 5A shows one input cycle (one write cycle) time Twc for the SRAM, the timing of its start time and end time determined by the reference clock, and the start time of the write cycle. The address signal ADR is sent to the SRAM under test. During this write cycle time Twc, the chip select signal / CS shown in Fig. 5B is given to the SRAM under test at a predetermined timing, and after the chip select signal is sent out, the write enable signal shown in Fig. 5C at a predetermined timing. (/ WE) is given to the SRAM under test. After the write enable signal is sent out, as shown in Fig. 5D at a predetermined timing, the input data Din is input to the SRAM under test.

The time duration of the valid data Valid part (Dvd) that is actually input to the SRAM under input data (Din) includes the setup time (Tds) of the input data and the hold time (Tdh) of the input data. And the timing thereof is defined for the write enable signal. In the development stage of the IC memory, it is checked whether or not these Tds or Tdh have been developed according to the design standard.

Conventionally, when measuring this Tds or Tdh, as shown in FIG. 6, the XOR waveform (Exclusive OR waveform) produced | generated using three timing clocks A, B, and C was used. The XOR waveform refers to a waveform in which waveforms on both sides of logic '1' are necessarily logic '0' or waveforms on both sides of logic '0' are logical '1' in one test cycle (one operation cycle).

More specifically with reference to FIG. 6. Fig. 6A shows an operation period (in this example, several operation cycles in a write cycle) when measuring Tds or Tdh, and one operation period is indicated by RATE. In accordance with this operation period (synchronized), the test pattern data PTND (P1, P2, P3, ...) shown in FIG. 6B is output from the pattern generator 2. 6C, 6D, and 6E show the three timing clocks A, B, and C described above, respectively, and timing clock A in FIG. 6C is generated by time Ta later than the start of each operation cycle RATE, and the timing in FIG. 6D. The clock B is generated by a time Tb later than the start of each operation period, and the timing clock C of FIG. 6E is generated by a time Tc later than the start of each operation period. Here, the relationship between these delay times is Ta < Tb < Tc and Tc < RATE. In this example, Tb-Ta = Tc-Tb = Ta + (RATE)-Tc = (RATE) / 3 is set.

The test pattern data P1, P2, P3,... Of each operation period of FIG. 6B to be applied to the MUT 9 by these three timing clocks A, B, and C. FIG. 6F, respectively, and as shown in FIG. 6F, inverted signals of the valid data portion Dvd signal exist immediately before and immediately after a signal of the valid data portion Dvd actually input to the MUT 9. A test pattern signal PTN is generated. FIG. 6G shows the waveform PTNWF of the test pattern signal PTN generated as described above in the case of the test pattern data P1 = 0, P2 = 1, and P3 = 1 shown in FIG. 6B. As can be easily understood in Fig. 6G, a logic '1' signal is generated before and after the signal P1 = 0 of the valid data portion Dvd actually input to the MUT 9, respectively, and before and after the signal P2 = 1, respectively. '0' signals are generated respectively, and logic '0' signals are generated before and after the signal P3 = 1, respectively. That is, an XOR waveform is generated. Use this XOR waveform to measure the Tds or Tdh of the DUT9.

In addition, the XOR waveform produced | generated by these three timing clocks A, B, and C is called an XORABC waveform in this specification.

The measurement of the setup time Tds slows down the timing of generation of the timing clock B in FIG. 6D, that is, increases the delay time Tb and narrows the time width Tds + Tdh of the valid data portion Dvd. Then, the valid data portion Dvd having this narrowed time width is input to the MUT 9. Next, it is read out from the MUT 9 and logically compared with the expected pattern signal EXP, and the boundary line between the defect (mismatch of both signals) and the passage (correspondence of both signals) (for example, the logic comparison result changes from defective to pass). (Tds) is measured from the value of the delay time Tb of the boundary line).

On the other hand, the measurement of the hold time Tdh speeds up the timing of generation of the timing clock C in Fig. 6E, that is, decreases the delay time Tc and narrows the time width of the valid data portion Dvd in a similar manner. Then, the effective data portion Dvd having a narrow time width is input to the MUT 9. Next, it is read out from the MUT 9 and logically compared with the expected value pattern signal EXP, or from the value of the delay time Tc of the boundary between passage and failure (e.g., the boundary where the logic comparison result changes from passage to failure). Tdh) is measured.

In recent years, the development of semiconductor memory has been surprisingly fast. For this reason, the write cycle time Twc becomes faster, i.e., shorter, so that the XORABC waveform cannot be used depending on the performance of the memory test apparatus. The reason for this is explained.

The minimum of the logical signal Pi or / Pi (i is an integer, i = 1, 2, 3, ... in this example) of the valid data portion Dvd in the test pattern signal applied to the MUT 9 shown in Fig. 6F. If the time width, i.e., the minimum pulse width that can be generated by the memory test apparatus is Tp, the write cycle time Twc when generating the XORABC waveform requires about 3 Tp. That is, the relation between the write cycle time Twc and the minimum pulse width Tp must be Twc &gt; 3Tp. Therefore, when Twc <3Tp, the XORABC waveform cannot be used.

For example, in the case of a memory test apparatus in which each operation period RATE of FIG. 6A is 9 ns (about 1/111 MHz), since the minimum pulse width Tp is about 3 ns, the setup of the IC memory, for example, SRAM, shown in the specification sheet If the sum of the time and hold time (Tds + Tdh) (same as the time width of the signal Pi in the valid data portion (Dvd)) is not more than about 3 ns of SRAM, use the XORABC waveform to measure the setup time and hold time of the SRAM. Can't.

By the way, the timing clock A of FIG. 6C used to generate the XORABC waveform is omitted, and the test pattern data PTND of FIG. 6B is applied to the MUT 9 by the two timing clocks B and C of FIGS. 6D and 6E. A change point is made in the test pattern data PTND of FIG. 6B to be made, and as shown in FIG. 7E, the logic signals Pi of the valid data portion Dvd actually input to the MUT 9 (P1, P2, in this example). Immediately after P3), using the waveform generated by the inverted signal / Pi of the logic signal Pi of this valid data portion Dvd, the hold time of the IC memory can be measured even when Twc &lt; 3Tp. In this specification, since this waveform does not use the timing clock A, it is called an XORBC waveform.

The method of generating this XORBC waveform is shown in Fig. 7, and the MUT 9 is constructed by two timing clocks B and C (substantially the same as the two timing clocks B and C in Figs. 6D and 6E) of Figs. 7C and 7D. A change point is created in the test pattern data (PTND) of Fig. 7B (substantially the same as the test pattern data of Fig. 6B) to be applied to Fig. 7B, and the valid data portion actually input to the MUT 9 as shown in Fig. 7E. Immediately after the signal Pi of (Dvd), the inversion signal / Pi of the valid data portion (Dvd) signal Pi is generated.

FIG. 7F shows the waveform PTNWF of the test pattern signal PTN generated as described above in the case of the test pattern data P1 = 0, P2 = 1, P3 = 1 in FIG. 7B. As can be easily understood in FIG. 7F, a logic '1' signal is generated after the signal P1 = 0 of the valid data portion Dvd actually applied to the MUT 9, and a logic '0' signal is applied after the signal P2 = 1. And a logic '0' signal is generated after the signal P3 = 1.

In this way, when the hold time of the MUT 9 is measured using this XORBC waveform, the relationship between the input cycle time Twc and the minimum pulse width Tp can be measured up to Twc ≧ 2Tp. That is, the hold time of the SRAM can be measured using the XORBC waveform until the sum (Tds + Tdh) of the setup time and hold time of the IC memory, e.g., the SRAM indicated in the specification, is about 1/2 or more of the input cycle time Twc. Can be.

However, since the measurement using the XORBC waveform cannot generate the inverted signal / Pi of the valid data portion Dvd signal Pi immediately before the logical signal pi of the valid data portion Dvd, the hold time of the IC memory is reduced. Although it can be measured, there is a significant drawback that the setup time (Tds) of the IC memory cannot be measured. In other words, as long as the inversion signal / Pi of the logic signal Pi of the valid data portion Dvd does not exist immediately before the logic signal Pi of the valid data portion Dvd, Even if the time Tb is changed, since the starting point of the logic signal Pi of the valid data portion Dvd is not determined (because there is no boundary in which logic is reversed), the pattern comparator 7 correctly matches or disagrees the logic. Can not be judged.

One object of this invention is a memory test apparatus in which the relationship between the write cycle time Twc and the minimum pulse width Tp can measure both the setup time and the hold time of various semiconductor memories up to Twc? 2Tp. To provide.

Another object of the present invention is to provide a memory test apparatus capable of accurately measuring both the setup time and the hold time of a high-speed semiconductor memory using a non-return to zero (NRZ) waveform.

In order to achieve the above object, in one aspect of the present invention, a predetermined test pattern signal is applied to the semiconductor memory under test, and the response signal read out from the semiconductor memory under test is compared with the expected pattern signal to perform a logical comparison of the semiconductor memory under test. A memory test apparatus for testing a setup time and a hold time, comprising: pattern generating means for generating at least two test signal data with a predetermined pattern in one operation period, and timing generating means for generating at least two timing clocks in one operation period And waveform generation means for generating two NRZ waveforms by applying at least two test signal data provided from said pattern generating means and at least two timing clocks provided from said timing generating means, and applying them to the semiconductor device under test. A memory test apparatus is provided, which is provided.

The pattern generating means outputs two test signal data whose logic is inverted in each operation period.

In one preferred embodiment, the pattern generating means, when testing the setup time of the semiconductor memory under test, includes the first and second two test signal data whose logic is inverted in each operation period. And test the hold time of the semiconductor memory under test, outputting the third and fourth test signal data in which the logic states of the first and second test signal data are inverted, respectively.

The waveform generating means makes a change point in one of the two test signal data provided from the pattern generating means by one of the two timing clocks provided from the timing generating means, and the other by the other timing clock. A change point is made in the test signal data of the A, and one NRZ waveform is generated.

In one preferred embodiment, the waveform generating means assigns a change point to the first and fourth test signal data provided from the pattern generating means, respectively, by one of the two timing clocks provided by the timing generating means. A change point is made in the second and third test signal data by the other timing clock, and two NRZ waveforms are generated.

In one variation, the waveform generating means includes two test signals provided from the pattern generating means by one of two timing clocks provided from the timing generating means when testing the setup time of the semiconductor memory under test. When a change point is made on one side of the data, and a change point is made on the other test signal data by the other timing clock, one NRZ waveform is generated, and the hold time of the semiconductor memory under test is tested. The timing clock makes a change point in the other test signal data, and the other timing clock makes a change point in the one test signal data to generate another NRZ waveform.

The generation timing of at least two timing clocks generated from the timing generating means is variable.

According to another aspect of the present invention, there is provided a pattern generating means for outputting test signal data of a predetermined pattern, a timing generating means for generating a required timing signal, a timing signal provided from the timing generating means, and the pattern generating means. Waveform generation means for generating a test pattern signal having a real waveform from the test signal data, a driver for applying a test pattern signal output from the waveform generation means to the semiconductor memory under test, and a response read from the semiconductor memory under test A memory test apparatus having a pattern comparator for performing a logical comparison between a signal and an expected pattern signal provided from the pattern generating means, and determining whether the semiconductor memory under test is good or not, wherein a predetermined pattern is provided within one operation period provided in the pattern generating means. Number of pattern data generated to generate at least two test signal data And timing clock generating means for generating at least two timing clocks in one operation period provided in said timing generating means, at least two test signal data provided from said pattern data generating means provided in said waveform generating means, Provided is a memory test apparatus having NRZ waveform generating means for generating two NRZ waveforms by at least two timing clocks provided from said timing clock generating means, and also capable of testing setup time and hold time of a semiconductor memory under test. do.

The pattern data generating means outputs two test signal data whose logic is inverted in each operation period.

In a preferred embodiment, the pattern data generating means includes two first and second test signal data whose logic is inverted in each operation period when testing the setup time of the semiconductor memory under test. And test the hold time of the semiconductor memory under test, outputting the third and fourth test signal data in which the logic states of the first and second two test signal data are inverted.

The NRZ waveform generating means makes a change point on one of the two test signal data provided from the pattern data generating means by one of the two timing clocks provided from the timing clock generating means, and makes a change point on the other timing clock. This creates a change point in the other test signal data and generates one NRZ waveform.

In one preferred embodiment, the NRZ waveform generating means is respectively applied to the first and fourth test signal data provided from the pattern data generating means by one of two timing clocks provided from the timing clock generating means. A change point is made, and a change point is made in said 2nd and 3rd test signal data by the other timing clock, respectively, and two NRZ waveforms are produced | generated.

In one variation, the NRZ waveform generating means is provided by the pattern data generating means by one of two timing clocks provided by the timing clock generating means, when the setup time of the semiconductor memory under test is tested. When a change point is made on one test signal data, a change point is made on the other test signal data by the other timing clock, and one NRZ waveform is generated, and the hold time of the semiconductor memory under test is tested. One timing clock makes a change point in the other test signal data, and the other timing clock makes a change point in the one test signal data to generate another NRZ waveform.

The generation timing of at least two timing clocks generated from the timing clock generating means is variable.

1 is a block diagram showing the basic configuration of an embodiment of a memory test apparatus according to the present invention.

2 is a timing chart for explaining a method of generating an NRZBC waveform used in the present invention.

FIG. 3 is a timing chart for explaining a method of generating an NRZBC waveform used when measuring the setup time of the IC memory by the memory test apparatus shown in FIG. 1.

FIG. 4 is a timing chart for explaining a method of generating an NRZBC waveform used when measuring the hold time of the IC memory by the memory test apparatus shown in FIG. 1.

Fig. 5 is a timing chart for explaining the operation of inputting data into the IC memory under test in the conventional memory test apparatus.

Fig. 6 is a timing chart for explaining a method of generating an XORABC waveform used when measuring the setup time and hold time of an IC memory by a conventional memory test apparatus.

FIG. 7 is a timing chart for explaining a method of generating an XORBC waveform used when measuring a hold time of a high speed IC memory by a conventional memory test apparatus.

8 is a block diagram showing a basic configuration of an example of a conventional memory test apparatus.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 1 to 4. In these drawings, those corresponding to the parts, waveforms, and elements shown in FIGS. 6 to 8 are denoted by the same reference numerals, and description thereof is omitted unless necessary.

Fig. 1 is a block diagram showing the basic configuration of an embodiment of a memory test apparatus according to the present invention, and Fig. 2 is a timing chart for explaining the method for generating an NRZBC waveform used in the present invention. A non-return to zero (NRZ) waveform is a waveform that does not return to its original state once the state changes within one operation cycle.

Like the conventional memory test apparatus shown in Fig. 8, the memory test apparatus shown in Fig. 1 is basically a tester processor (not shown), a pattern generator 2, a timing generator 3, and a waveform shaper 4, respectively. And a driver 5, an analog level comparator 6, a pattern comparator 7, and a poor analysis memory (not shown).

In the present invention, the pattern generator 2 includes two pattern data generators 22 for outputting two test pattern data PTND1 and PTND2 to the waveform shaper 4 within one operation period RATE. The timing generator 3 includes a two timing clock generator 33 for outputting two timing clocks B and C to the waveform shaper 4 in one operation period RATE. The waveform shaper 4 also includes a 2NRZ waveform generator 44 for generating two NRZ waveforms.

The waveform shaper 4 generates the 2NRZ waveform by the two test pattern data PTND1 and PTND2 provided from the pattern generator 2 and the two timing clocks B and C provided from the timing generator 3. The unit 44 can generate two NRZ waveforms.

Referring to FIG. 2, a process of generating two NRZ waveforms in the 2NRZ waveform generator 44 of the waveform shaper 4 will be described.

Fig. 2A shows an operating cycle (RATE) when measuring Tds or Tdh, and in accordance with this operating cycle, the test pattern data PTND1 (Pl b, P2b, P3b, ...) and PTND2 (Plc) shown in Figs. 2B and 2C. , P2c, P3c, ... are output from the pattern generator 2. Figures 2D and 2E show two timing clocks B and C for generating an NRZ waveform, respectively, and the timing clock B of Figure 2D The timing clock C in Fig. 2E is generated late by the time Tb at the start of each operation period, and the timing clock C in Fig. 2E is generated late by the time Tc at the start of each operation period, where the relationship between these delay times is Tb. <Tc and Tc <RATE.

The change points in the test pattern data (Plb, P2b, P3b, ... and Plc, P2c, P3c, ...) of Figs. 2B and 2C in the respective operation cycles RATE by these two timing clocks B and C, respectively. 2F, the test pattern to be applied to the MUT 9 in which the test pattern data Plb, P2b, P3b, ... and the test pattern data Plc, P2c, P3c, ... are alternately arranged. Generate the signal PTN. FIG. 2G shows that the test pattern data PTND1 shown in FIG. 2B is Plb = 0, P2b = 1, P3b = 1, and the test pattern data PTND2 shown in FIG. 2C is Plc = 1, P2c = 0, P3c = 0. Shows a waveform PTNWF of the test pattern signal PTN generated as described above.

As can be easily understood from Fig. 2, in this example, in each operation period RATE, the test pattern data PTND1 is set by the timing clock B, the test pattern data PTND2 is reset, and the timing clock is set. By (C), the test pattern data PTND1 is reset and the test pattern data PTND2 is set to generate the test pattern signal PTN to be applied to the MUT 9. As a result, as shown in Fig. 2F, the test pattern signal PTN is the test pattern in the same operation period after the data of the time width corresponding to 1/2 cycle of the test pattern data PTND1 in one operation period. Data of a time width corresponding to one-half cycle of the data PTND2 is a continuous signal. That is, the test pattern data PTND1 having a time width corresponding to 1/2 cycle and the test pattern data PTND2 having a time width corresponding to 1/2 cycle become signals arranged alternately for the same operation period.

From the above results, the test of the pattern data generator 22 of the pattern generator 2 is performed as the logic of the test pattern data PTND1 and the logic of the test pattern data PTND2 are inverted from each other in each operation period RATE. When the pattern data is generated and supplied to the waveform shaper 4, as shown in FIG. 2G, immediately after the data Plb, P2b, P3b, ... in each operation period of one test pattern data PTND1. Since the data is the data Plc, P2c, P3c, ... in each operation cycle of the other test pattern data PTND2, the two data in each operation cycle are necessarily data inverted in logic. Therefore, in the two pattern data generation sections 22 of the pattern generator 2, the logic of the test pattern data PTND1 and the test pattern data PTND2 that are inverted from each other are reversed (test pattern data PTND1). And two test pattern data in which the logic of the test pattern data PTND2 is inverted respectively), two NRZ waveforms can be generated in each operation period. For example, in the example of FIG. 2, since the test pattern data Plb = 0, Plc = 1, P2b = 1, P2c = 0, P3b = 1, and P3c = 0, the test pattern signal waveform PTNWF is' 0 '→' 1. '→' 1 '→' 0 '→' 1 '→ "0', and a first NRZ waveform is generated. Next, the logic is reversed, where Plb = 1, Plc = 0, P2b = 0, and P2c = When 1, P3b = 0, and P3c = 1, the test pattern signal waveform PTNWF becomes '1' → '0' → '0' → '1' → '0' → '1' and the second NRZ The waveform is generated, thus allowing two NRZ waveforms to be generated in each operating period.

In this specification, two NRZ waveforms generated within one operation period RATE using two test pattern data PTND1 and PTND2 and two timing clocks B and C will be referred to as NRZBC waveforms. In addition, since the timing clock A is not used, the timing clocks B and C are described as in the case of FIG. 7, but the timing clocks may be named timing clocks A and B or timing clocks D and E. The name of the test pattern data may be arbitrary. The important thing is to use two timing clocks and two test pattern data to achieve the same operation. In addition, any test pattern data may be used as the signal of the valid data portion Dvd actually input to the MUT 9.

Next, an operation of measuring the setup time Tds and the hold time Tdh of the semiconductor memory (for example, SRAM) using the NRZBC waveform will be described in detail.

Fig. 3 is a timing chart for explaining the operation in the case of measuring the setup time of the SRAM, and Fig. 3A shows the operation cycle (some operation cycles in the write cycle in this example), and one operation cycle is represented by RATE. When measuring Tds, as mentioned above, the signal which reversed the logic of this Dvd signal needs to exist just before the logic signal of the effective data part Dvd actually input to MUT9. Therefore, in this case, the two pattern data generators 22 of the pattern generator 2 generate the test pattern data PTND1 and PTND2 in which the two logics shown in FIGS. 3B and 3C are inverted.

Specifically, if the test pattern data applied to the MUT 9 is the test pattern data PTND2 (P1, P2, P3) of FIG. 3C, the test pattern data PTND2 of FIG. 3C is the test pattern data PTND1 of FIG. 3B. Data (/ P1, / P2, / P3) inverting the logic of &lt; RTI ID = 0.0 &gt;), &lt; / RTI &gt; and output these test pattern data PTND1 and PTND2 from the pattern generator 2 in synchronization with the operation cycle (RATE). The waveform is transmitted to the waveform shaper 4. The 2NRZ waveform generator 44 of the waveform shaper 4 sets the test pattern data PTND1 by the timing clock B of FIG. 3D generated by being delayed by the time Tb at the start of each operation period. A change point is made in the test pattern data P1, P2, and P3 of each operation period, and the test pattern data is generated by the timing clock C of FIG. 3E which is generated later by the time Tc at the start of each operation period. Set (PTND2) to make a change point in the test pattern data (/ P1, / P2, / P3) of each operation cycle. As a result, as shown in Fig. 3F, a test pattern signal PTN is generated, in which data of a time period of 1/2 cycle is composed of signals arranged in order of / P1, P1, / P2, P2, / P3, and P3. And is applied to the MUT 9. That is, the data immediately before the valid data portion (Dvd (data P1, P2, P3 of 1/2 cycle time width) actually inputted to MUT 9 is logically inverted data (data of 1/2 cycle time width / P1, / A test pattern signal PTN of P2, / P3) is generated. The waveform of this test pattern signal PTN is one waveform in two NRZ waveforms (NRZBC waveform), as shown in FIG. 3G. In this example, the time width obtained by subtracting the delay time Tb from the delay time Tc is set to a time corresponding to 1/2 of one operation period RATE.

The measurement of the setup time Tds delays the timing of generation of the timing clock B in FIG. 3D as in the case of the conventional example, that is, increases the delay time Tb, and thus the time width of the valid data portion Dvd. (Tds + Tdh) is narrowed, and the valid data portion Dvd having this narrowed time width is input to the MUT 9. Next, the MUT 9 reads it out and logically compares it with the expected value pattern signal EXP provided from the pattern generator 2, so as to establish a boundary line (e.g., logic) between bad (unmatched state of both signals) and passing (matched state of both signals). The value of the delay time Tb of the boundary line where the comparison result changes from defective to passing) is measured, and Tds is measured from this measured value.

On the other hand, in the case of measuring the hold time (Tdh) MF of the SRAM, as described above, the signal inverting the logic of the Dvd signal immediately after the signal of the valid data portion Dvd actually input to the MUT 9 It needs to exist. Fig. 4 is a timing chart for explaining the operation in the case of measuring the Tdh of the SRAM, Fig. 4A shows the operation cycle (some operation cycles in the write cycle in this example) (RATE), and Figs. 4B and 4C The two test logic data PTND1 and PTND2 are in the inverted state, respectively.

In the measurement of Tds described above, the valid data portions Dv d actually input to the MUT 9 are P1, P2, P3,... For this reason, even when measuring Tdh, the valid data portion Dvd of the test pattern data actually input to the MUT 9 must be the same data (P1, P2, P3, ...). Therefore, in this case, the two pattern data generation sections 22 of the pattern generator 2 generate the test pattern data PTND1 and PTND2 in which the two logics shown in Figs. 4B and 4C are inverted. That is, P1, P2, P3,... As the test pattern data PTND1 of FIG. 4B. To generate the data / P1, / P2, / P3, ..., which inverts the logic of the test pattern data PTND1 of FIG. 4B as the test pattern data PTND2 of FIG. Create

These test pattern data PTND1 and PTND2 are outputted from the pattern generator 2 in accordance with the operation period RATE (synchronized), and transmitted to the waveform shaper 4. The 2NRZ waveform generator 44 of the waveform shaper 4 sets the test pattern data PTND1 by the timing clock B of Fig. 4D, which is generated later by the time Tb at the start of each operation period. A change point is made in the test pattern data P1, P2, and P3 of the operation cycle, and the test pattern data (see FIG. 4E) is generated only by the timing clock C of FIG. 4E which is generated only later in time Tc at the start of each operation cycle. PTND2) is set to make a change point in the test pattern data (/ P1, / P2, / P3) of each operation period. As a result, as shown in Fig. 4F, a test pattern signal PTN is generated, in which data of a time period of 1/2 cycle consists of signals arranged in the order of P1, / P1, P2, / P2, P3, and / P3. And is applied to the MUT 9. That is, data immediately after the effective data portion (Dvd (data of P1, P2, P3 of 1/2 period of time width) actually inputted to the MUT 9 is logically inverted (data of 1/2 period of time width). A test pattern signal PTN of / p1, / p2 and / p3) is generated. The waveform of this test pattern signal PTN is the other waveform in two NRZ waveforms (NRZBC waveform), as shown to FIG. 4G. Also in this example, the time width obtained by subtracting the delay time Tb from the delay time Tc is set to a time corresponding to 1/2 of one operation period RATE.

In the measurement of Tdh, as in the conventional example, the timing of generation of the timing clock C in FIG. 4E is increased, that is, the delay time Tc is reduced, and the time width of the valid data portion Dvd is narrowed. The valid data portion Dvd having a narrower time width is input to the MUT 9. Next, it is read from the MUT 9 and logically compared with the expected pattern signal EXP to measure the value of the delay time Tc of the boundary between passage and failure (e.g., the boundary where the logic comparison result changes from passage to failure). Then, (Tdh) is measured from this measured value.

In this manner, when the NRZBC waveform is used, the setup time and hold time of the MUT 9 can be measured when the relationship between the input cycle time Twc and the minimum pulse width Tp is Twc ≧ 2Tp. That is, according to the present invention, the setup time and hold time of the sum of the setup time and hold time (Tds + Tdh) of the semiconductor memory shown in the specification are about 1/2 or more of the input cycle time Twc, respectively. It can be measured accurately. Therefore, since Twc can be shortened to 2Tp, the Tds and Tdh can be accurately measured up to a high speed semiconductor memory in the range of 3Tp ≥ Twc ≥ 2Tp, which could not be measured in the conventional memory test apparatus.

In the above embodiment, the two pattern data generators 22 of the pattern generator 2 reverse the logic of the test pattern data PTND1 and the test pattern data PTND2 that are inverted from each other. Although the waveform is configured to be generated, it is not limited to this method. For example, the timing of the 2NRZ waveform generator 44 of the waveform shaper 4 is not reversed in the two pattern data generator 22 without the logic of the test pattern data PTND1 and the logic of the test pattern data PTND2 reversed. Even if the test pattern data PTND1 is set by the clock C Tc and the test pattern data PTND2 is set by the timing clock B Tb, the other NRZ waveform can be generated. Specifically, in Fig. 3, when the test pattern data PTND1 is set by the timing clock C and the test pattern data PTND2 is set by the timing clock B, the same results as in Fig. 4 are obtained. Two NRZ waveforms can be generated from. In other words, two NRZ waveforms can be generated in each operation period by reversing the test pattern data set / reset (giving a change point) by the two timing clocks.

It goes without saying that the memory test apparatus according to the present invention can be similarly used for the measurement of setup time and hold time of various semiconductor memories other than IC memory (for example, SRAM).

As apparent from the above description, the memory test apparatus according to the present invention includes an NRZ waveform which generates an inverted signal of the valid data portion within each operation period, just before the valid data portion actually input to the semiconductor memory under test, Immediately after the valid data portion, two types of NRZ waveforms can be generated from the NRZ waveform which generates the inverted signal of the valid data portion. Therefore, by using these two types of NRZ waveforms, the setup time and hold time of various semiconductor memories can be accurately measured until the relationship between the write cycle time Twc and the minimum pulse width Tp is Twc? 2Tp.

Thus, since Twc can be shortened to 2Tp, a remarkable advantage is obtained that the Tds and Tdh can be accurately measured up to a high speed semiconductor memory in the range of 3Tp ≥ Twc ≥ 2Tp, which could not be measured in the conventional memory test apparatus. Lose.

In recent years, the speed-up of semiconductor memory has developed remarkably, and the effect obtained by this invention contributes to practical use, and is very large.

As mentioned above, although preferred embodiment which showed this invention was described, it is clear for those skilled in the art that various changes, changes, and improvement can be made with respect to the above-mentioned embodiment, without deviating from the mind and range of this invention. will be. Accordingly, the invention is not limited to the exemplary embodiments, but includes all such variations, modifications, and improvements that fall within the scope of the invention as determined by the claims.

Claims (14)

A memory test apparatus for testing a setup time and a hold time of a semiconductor memory under test by applying a predetermined test pattern signal to the semiconductor memory under test, comparing the response signal read from the semiconductor memory under test with a expected pattern signal. , Pattern generating means for generating at least two test signal data of a predetermined pattern in one operation period; Timing generating means for generating at least two timing clocks in one operation period; And Waveform generation means for generating two NRZ waveforms by applying at least two test signal data provided from said pattern generating means and at least two timing clocks provided from said timing generating means and applying them to the semiconductor device under test; Memory test apparatus, characterized in that. 2. The memory test apparatus according to claim 1, wherein the pattern generating means outputs two test signal data whose logic is inverted in each operation period. 2. The pattern generating means according to claim 1, wherein the pattern generating means, when testing the setup time of the semiconductor memory under test, performs the first and second two test signal data whose logic is inverted in each operation period. Outputting the third and fourth test signal data in which the logic states of the first and second test signal data are inverted, respectively, when the hold time of the semiconductor memory under test is tested. Memory test device. 3. The waveform generating means according to claim 2, wherein the waveform generating means makes a change point on one side of the two test signal data provided from the pattern generating means by one of the two timing clocks provided from the timing generating means. A memory test apparatus, characterized by generating a change point in the other test signal data by a timing clock and generating one NRZ waveform. 4. The waveform generating means according to claim 3, wherein the waveform generating means makes a change point in the first and fourth test signal data provided from the pattern generating means by one of two timing clocks provided from the timing generating means. And two NRZ waveforms are generated by making change points in the second and third test signal data, respectively, by the other timing clock. 3. The waveform generating means according to claim 2, wherein the waveform generating means is provided with two test signals provided from the pattern generating means by one of two timing clocks provided from the timing generating means when the setup time of the semiconductor memory under test is tested. When a change point is made on one side of the data, a change point is made on the other test signal data by the other timing clock, one NRZ waveform is generated, and the hold time of the semiconductor memory under test is tested. A change point is made in the other test signal data by the timing clock of the other, and a change point is made in the test signal data of the one by the other timing clock to generate one more NRZ waveform. Memory test device. The memory test apparatus according to claim 1, wherein the generation timing of at least two timing clocks generated from said timing generating means is variable. In the pattern generating means for outputting the test signal data of a predetermined pattern, the timing generating means for generating the required timing signal, the timing signal given from the timing generating means, and the test signal data given from the pattern generating means, Waveform generation means for generating a test pattern signal having a waveform, a driver for applying a test pattern signal output from the waveform generation means to a semiconductor memory under test, a response signal read from the semiconductor memory under test and the pattern generation means A memory test apparatus comprising a pattern comparator for logically comparing an expected expected pattern signal to determine whether or not the semiconductor memory under test is Pattern data generating means provided in the pattern generating means for generating at least two test signal data with a predetermined pattern within one operation period; Timing clock generating means provided in said timing generating means for generating at least two timing clocks in one operation period; NRZ waveform generating means for generating two NRZ waveforms by at least two test signal data provided from said pattern data generating means and at least two timing clocks provided from said timing clock generating means, provided in said waveform generating means; With A memory test apparatus, wherein the setup time and hold time of a semiconductor memory under test can be tested. 9. The memory test apparatus according to claim 8, wherein the pattern data generating means outputs two test signal data whose logic is inverted in each operation period. 9. The pattern data generating means according to claim 8, wherein the pattern data generating means, when testing the setup time of the semiconductor memory under test, includes the first and second two test signal data whose logic is inverted in each operation period. Outputting the second test signal data in which the logic states of the first and second test signal data are reversed, respectively, when the hold time of the semiconductor memory under test is tested. Memory test device characterized in that. 10. The method of claim 9, wherein the NRZ waveform generating means makes a change point on one side of two test signal data applied by the pattern data generating means by one of two timing clocks provided from the timing clock generating means, A memory test apparatus, wherein a NRZ waveform is generated by making a change point in the other test signal data by the other timing clock. 11. The apparatus according to claim 10, wherein the NRZ waveform generating means changes to the first and fourth test signal data provided by the pattern data generating means, respectively, by one of two timing clocks provided from the timing clock generating means. And a point of change, and a change point in the second and third test signal data, respectively, by means of the other timing clock to generate two NRZ waveforms. 10. The apparatus according to claim 9, wherein said NRZ waveform generating means is provided from said pattern data generating means by one of two timing clocks provided from said timing clock generating means when testing the setup time of the semiconductor memory under test. When one change point is made on one test signal data, the change point is made on the other test signal data by the timing clock on the other, one NRZ waveform is generated, and the hold time of the semiconductor memory under test is tested. Generating a change point in the test signal data of the other by the timing clock of one side and generating a change point in the test signal data of the other by the timing clock of the other side to generate one more NRZ waveform. Memory test device characterized in that. 9. The memory test apparatus according to claim 8, wherein the generation timing of at least two timing clocks generated from said timing clock generating means is variable.