JPS61133872A - Ic tester - Google Patents

Abstract

PURPOSE:To enable parallel measurement of a plurality of devices simultaneously with one tester, by providing variable delay circuits in a clock input terminal system of ICs to be measured one each IC to adjust the delay value thereof. CONSTITUTION:When clock signals Clk1 and Clk2 are inputted into ICs 12a and 12b to be measured respectively, synchronous output signals ALE1 and ALE2 are outputted from the ICs 12a and 12b to be inputted into a control circuit 14 of an IC tester 11. Given a deviation in the phase between synchronous output signals ALE1 and ALE2, the control circuit 14 control variable delay circuits 16a and 16b to make the synchronous signals ALE1 and ALE2 synchronize each other so that the ICs 12a and 12b will synchronously operate completely. Thereafter, a test data generation and propriety judging circuit 15 inputs a test data TD into the ICs 12a and 12b to determine whether the output data OD1 and OD2 outputted as a result coincide with the expected values thereby judging the propriety of the ICs 12a and 12b parallelly.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an integrated circuit (IC) testing device, more specifically, a variable delay circuit is provided for each IC under test to a clock input terminal system of the IC under test. The present invention relates to a device that enables parallel measurement of multiple ICs by adjusting this delay line.

[Conventional technology]

When testing a memory device, it is possible to test multiple memory devices at the same time by inputting a human signal to the device, specifying an address, and retrieving data.

However, the type of L that tests by specifying the input/output timing according to the timing of the synchronous output signal of the device under test.
In a C (for example, an IC such as a microprocessor with a built-in oscillator circuit, clock frequency divider circuit, etc.), the delay time (t
d) changes depending on device variations and bias conditions, so only one (11) devices can be measured at a time.

Referring to Figure 3 (al), 31 is a clock generator, 32 is an IC to be measured, 33 is a clock divider circuit built into IC 32, 34 is an input terminal, and 3S is an output terminal. In the diagram, A is clock input terminal 3
4, B indicates the synchronous output of IC32. Ls indicates standard timing, IC3
The timing of the input terminal 34 and output terminal 35 of No. 2 is defined based on the timing of Ls. In FIG. 3 (bl), td indicates the delay time, but since this td varies depending on device variations and bias conditions, only one fc of this type is measured at a time.

FIG. 4 is a block diagram showing a conventional test device.
A signal is input from the signal generator 43 to C41, and IC4
1, the illustrated ALE is sent to the tester 42 via line 44. The tester 42 sends data and address signals to the IC 41 through lines 45 and 46, respectively, and then the I
The output from C41 is sent over line 47 to tester 42 for testing.

[Problem that the invention seeks to solve]

In order to increase the effectiveness of mass production of designed ICs, it is desirable to be able to simultaneously measure a plurality of ICs with one tester. However, as described above, since the delay time of each device varies, it is not possible to simultaneously measure a plurality of devices with one tester.

When attempting to simultaneously measure a plurality of devices as shown in FIG. 3 (al) using an IC tester, it is necessary to provide independent timing to each device.

Therefore, if an independent timing system is provided for each device, there is a problem that the IC tester becomes extremely expensive.

Means for Solving Problem C] The present invention provides an IC testing device that solves the above problems, and the means includes a clock generation circuit and a plurality of a variable delay circuit, a plurality of output terminals for applying the output of each variable delay circuit to a plurality of integrated circuits under test, and receiving a signal output from each integrated circuit under test in response to the clock signal;
This is accomplished by an integrated circuit testing apparatus characterized in that the delay amount of each variable delay circuit is controlled so that each signal is synchronized.

[Effect]

In the above device, the timing of input and output signals can be shared by all devices by adjusting each delay line so that the synchronous output signals of each device are in the same phase.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 (al is a block diagram of an IC tester which is an embodiment of the present invention. FIG. 1 To) is a timing diagram for explaining the operation of FIG. 1 (al). IC
Tester 12a, 12b is a microprocessor or other IC to be measured 113 is a clock generator, 14 is a control circuit, 15 is a test data generation and quality determination circuit, 16
a, 16b are variable delay circuits,
, CIJ (t is a clock signal, CNT+, CNT2 is a control signal, Al, El.

ALE2 is a synchronized output signal output in response to a clock input, TD is a test address and test manual data, and 001 and 002 are output data.

The operation of the IC tester according to the present invention will be explained below. At the start of the test, the delay amounts of the variable delay circuits 16a and 16b are each set to zero. Therefore, the clock signals CIJz4 and Cff1Jct are completely the same signal.

The clock signals CQ and C1Ax are respectively connected to the IC under test.
12a.

When input to 12b, synchronous output signals ALEI, ALE2
is output from the ICs under test 12a and 12b. These synchronous output signals ALEI and ALE2 are respectively output from IC tester 1.
The signal is input to the control circuit 14 of No. 1.

The control circuit 14 controls the variable delay circuits 16a and 16b as follows when the synchronous output signals ALE1 and ALE2 have a phase shift td as shown in FIG. Detect which phase of ALI, + and ALE2 is leading.In this case, since the phase of one synchronous output signal ALE+ is leading,
The control circuit 14 outputs a control signal CNT+ so as to increase the delay amount of the variable delay circuit 16a, gradually increases the delay amount of the variable delay circuit 16a, and outputs the clock signal ci6.
, delay the phase of . By delaying the phase of the clock signal cllk<, the phase of the synchronous output signal ALE1 is also delayed. When the control circuit 14 detects that the phases of the synchronized output signals ALE+ and ALE2 match as shown by the broken line in the top of FIG. 1, the setting of the delay amount of the variable delay circuits 16a and 16b is completed. In this way, the synchronous output signal ALE1゜ALE2
If they can be synchronized, the circuits of the devices to be measured 1c 12a and 12b will operate in perfect synchronization, so that the test data TD can be applied to both devices at the same time. Therefore, the test data generation and pass/fail judgment circuit 15 transfers the test data TD to the IC under test 12a after the setting is completed.
, 12b, and the resulting output data 0
It is determined whether 01 and 002 match the expected values, and the quality of the ICs to be measured 12a and 12b is determined in parallel. As described above, in the C tester of the present invention, after synchronizing the operations of a plurality of ICs, a test is performed in parallel to determine the quality of each IC. In the above embodiment, there are two ICs, but by increasing the number of variable delay circuits 16a and 16b to two or more, two or more ICs can be measured in parallel.

Note that the delay circuits 16a and 16b can be configured as shown in FIG. 2, for example. In FIG. 2(a), 21a,
21b, , , 21h are each, for example, 1 ns,
2ns, 4ns.

8 nst Ions, 20ns, 40ns, 8
0ns delay cables 22a, 22b, . , 22
Indicates a tap with h. Delay cables 22a, 22
b, . . . , 22h are pair cables of different lengths.

In the measurement, check the ts with the delay cables not connected for the ICLs 2a and 12b under test, and if there is a td in any of the fcs to be measured, switch (
(indicated by the arrow in the figure) and pass the signal through the corresponding cable.
The signal is delayed by td so that synchronous output signals can be obtained from both ICs at the same time.

Note that the number of taps and therefore the number of cables are appropriately selected depending on the type of IC to be measured.

FIG. 2 cb+ is a detailed view of the tap 21a in the same figure (al), and includes 3F fixed switches SW1, SWz,
The relationship between the S scale 3 and the control signal CNT is shown. Control signal C
NT and CNT' are complementary signals. When delay cable 22a is used, switches SW1 and SWz are on and 5III3 is off; when delay cable 22a is not used, switches SW+ and SWz are off and 5IW
3 is turned on. Each switch is controlled by a control signal CNT.

Note that the taps 21b other than the tap 21a...
,.

22h is similarly configured.

[Effects of the Invention] As explained above, according to the present invention, by providing a low-cost variable delay circuit, a plurality of devices can be
It is now possible to perform parallel measurements simultaneously with RC testers.
It has the effect of improving mass production efficiency.

[Brief explanation of the drawing]

FIG. 1 (al and width) is a block diagram of an embodiment of the present invention and a diagram showing the principle of the present invention, FIG. 2 fa) is a diagram showing the configuration of a variable delay circuit, and FIG. Fig. 3(b) is a diagram showing the clock input and device synchronization output in the test of the same Fig. is a professional diagram showing a conventional test device. In the figure, 11 is a tester, and 12a and 12b are ICs to be measured.
13a+13b are signal generators, 14a, 14b,
L7a, 17b are signal lines, 15 is a clock generator, 16a, 151) is a variable delay circuit, 21a, 22
b, , , 22h is a tap, 22a, 22b, ,
22h indicates a bare wire cable. Ji1 Figure 1C1k C1k+ “ 1 ” ’C [k2 (b) Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] A clock generation circuit, a plurality of variable delay circuits receiving clock signals from the clock generation circuit, a plurality of output terminals for providing outputs of each variable delay circuit to a plurality of integrated circuits under test, and a plurality of output terminals responsive to the clock signals. An integrated circuit testing device characterized in that the device receives signals output from each integrated circuit under test and controls the amount of delay of each variable delay circuit so that each signal is synchronized.