JPH09218246A - Method for verifying high speed operation of logic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To test a logic circuit while receiving a test pattern and monitoring an output signal sequentially using a logic circuit test equipment having relatively low operating speed and available relatively easily. SOLUTION: An I/O flip-flop on the input side of a synchronization block for which normal operation is verified is operated with a system clock signal SCK while an I/O flip-flop on the output side of synchronization block is operated with a test clock signal TCK. Even in case of system clock signal SCK and test clock signal TCK having period of 50ns, the time interval between the rising of a pulse S1 and the falling of pulse T2 is 40ns and it can be seen as if a test is performed at a higher frequency. Consequently, normal operation can be verified at a higher operating speed using a logic circuit test equipment having relatively low operating speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention sequentially monitors a signal output from a logic circuit to be inspected while sequentially inputting a test pattern to a logic circuit to be inspected which operates at an operating speed assuming an actual use state. The present invention relates to a high-speed operation verification method for a logic circuit, in which a normal operation of the logic circuit to be inspected at a required operation speed is verified by using a logic circuit test apparatus capable of performing the operation. While suppressing the operating speed of the input of the test pattern and the operating speed of the monitor by the logic circuit test device of the signal output by the test target logic circuit, the test target logic circuit that operates at the operating speed verified by the logic circuit test device or higher By making it possible to verify normal operation, it is possible to verify the normal operation of the logic circuit under test with a logic circuit tester that is relatively easy to obtain. Or relates to a high-speed operation verification method of a logic circuit it is possible to enable cost reduction and the like required for logic circuit testing device.

[0002]

2. Description of the Related Art In recent years, ASIC (application spec.
The logic functions of the integrated circuits, including custom integrated circuits called semi-integrated circuits, semi-custom integrated circuits, etc., have been verified by simulation as to their normal operation as software. In addition, even when such a simulation is performed, it is general to perform a real machine test using an actual integrated circuit chip.

A logic circuit tester (tester) used in this actual machine test operates at an operating speed assuming an actual use state while contacting a pad of an integrated circuit chip or a terminal of an integrated circuit package with a probe. While sequentially inputting test patterns to the internal test target logic circuit, the signals output from the test target logic circuit are sequentially monitored. Therefore, in the actual test of the integrated circuit, the normal operation of the built-in logic function is verified based on the monitoring result of the logic circuit test apparatus.

FIG. 1 is a circuit diagram showing an example of a conventional logic circuit to be inspected.

In FIG. 1, the synchronous operation block B1
I / O flip-flops FF10 to FF18 are provided at the respective inputs and outputs of 0 and B11.
These I / O flip-flops FF10 to FF18
Operate according to the clock signal input to the respective clock signal input, that is, in this FIG. 1, the system clock signal SCK input to the respective clock signal input.
Work according to. Also, the synchronous operation blocks B10 and B
11 is 1 of the system clock signal SCK.
It is a logic circuit composed of a combination circuit, the operation of which is completed within the period of one cycle.

Therefore, in each of the synchronous operation blocks B10 and B11, when the operation of the built-in logic function does not end within the period of one cycle of the system clock signal SCK, the operation timing is defective. Will occur. Therefore, in order to find out such a defect, a software-like normal operation verification by simulation and an actual machine test by a logic circuit test device using an actual inspection target logic circuit (such as an integrated circuit chip) are performed. .

[0007]

Here, in the logic circuit test apparatus, the test pattern is input and the signal output from the logic circuit to be inspected is monitored in synchronization with the clock signal. Therefore, the operating speed of such a test pattern input and output signal monitor depends on the frequency of such a clock signal. That is, the higher the frequency of the clock signal, the faster the operating speed of the test pattern input and output signal monitor.

In the logic circuit test apparatus, the higher the frequency of the clock signal that determines the operation speed of the test pattern input and the monitor, the higher the cost of the equipment.
Further, when such an operating speed becomes high and the frequency of the clock signal becomes high, it becomes impossible to realize the logic circuit test apparatus, or even if it can be realized, the cost of the equipment becomes very high. There is a problem that it becomes expensive.

Further, as a matter of course, when the operation speed in the actual machine test using the logic circuit test device becomes slower than the operation speed in the actual use state, the verification of the logic function and the operation timing of the logic circuit to be inspected is insufficient. turn into.

FIG. 2 shows a conventional test for simulating a logic circuit to be inspected and a logic circuit test apparatus (tester).
6 is a time chart for comparing with an actual machine test using.

Here, it is assumed that the logic circuit to be inspected operates by the system clock signal SCK as an internal clock signal. Also, in the actual use condition, and in the simulation, this system clock signal SCK is 25M.
Hz. On the other hand, in the actual machine test using the logic circuit test device, this system clock signal SCK is 20
It is assumed to be in MHz.

Then, in actual operation or simulation,
Since the system clock signal SCK is 25 MHz,
The period of one cycle of the system clock signal SCK is
It becomes 40 ns as shown in the figure. On the other hand, in the actual test by the logic circuit test device, the system clock signal SC
Since K is 20 MHz, the system clock signal S
The period of one cycle of CK is 50 ns as shown in the figure.
Becomes

As described above, when the cycle of the system clock signal SCK in the actual machine test becomes long, even if normal operation is obtained in the actual machine test, the logic circuit to be inspected must operate in a shorter time in the actual usage state. Must
Since a higher speed operation is required, it becomes impossible to guarantee the normal operation in such an actual usage state.

The present invention has been made to solve the above-mentioned conventional problems, and monitors the operation speed of the input of the test pattern by the logic circuit test device and the signal output from the logic circuit to be inspected by the logic circuit test device. It is possible to verify the normal operation of the logic circuit to be inspected, which operates at a speed higher than the operation speed verified by the logic circuit test device, while suppressing the operation speed of the logic circuit test device. It is an object of the present invention to provide a high-speed operation verification method for a logic circuit, which can verify the normal operation of the logic circuit to be inspected and can reduce the cost required for the logic circuit test apparatus.

[0015]

According to the present invention, a signal output from a logic circuit to be inspected is input while a test pattern is sequentially input to a logic circuit to be inspected which operates at an operating speed assuming an actual use state. In a high-speed operation verification method for a logic circuit, which is configured to verify the normal operation of the logic circuit to be inspected at a required operation speed by using a logic circuit test device that can be sequentially monitored, A synchronous operation block including an I / O flip-flop that operates according to a clock signal input to a clock signal input, and a combinational circuit configured to end the operation within a period of one cycle of the clock signal In addition, the inspection target logic circuit is divided into a normal operation mode for normal operation and a high-speed operation verification mode for high-speed operation verification. The operation mode external setting terminal for inputting an operation mode setting signal for externally setting the deviation, the normal clock signal wiring for supplying the normal clock signal of the frequency F0, and the actual use state of the frequency F0 are described. In order to facilitate verification of normal operation of the logic circuit to be inspected in the high-speed operation verification mode using the logic circuit test device with respect to the assumed frequency FX, the frequency FX which is the frequency F0 is used. The frequency F1 whose frequency is suppressed to a low level is determined, and for the frequency FX and the frequency F1 or the period T1 (= 1 / F1) of the frequency F1, the phase difference time t that becomes (FX = 1 / (T1-tp))
and a test clock signal line for supplying a test clock signal of the frequency F0 whose phase is earlier than the normal clock signal by the phase difference time tp, is provided in the logic circuit to be inspected, and the synchronous operation block is provided. In the normal operation mode, the normal clock signal is input to the clock signal input of each of the I / O flip-flops provided in the output in which the operation timing becomes a problem. In this case, the test clock signal is input, and the normal clock signal is input to the clock signal input of each of the I / O flip-flops other than these, and the high-speed operation verification mode using the logic circuit test apparatus is performed. At the time of verifying the normal operation of the logic circuit to be inspected, the frequency F0 is suppressed to the frequency F1 for the convenience of verification. While seeking, as if the frequency F1
A normal operation of the logic circuit to be inspected can be verified in a state where a clock signal of the higher frequency FX is artificially input to the clock signal input of each I / O flip-flop. By
This has solved the above-mentioned problem.

In the high speed operation verification method of the logic circuit, in the high speed operation verification mode, the signal of the output of the I / O flip-flop provided at the output of the synchronous operation block is converted into the phase difference time tp. By providing a test operation timing adjustment delay circuit that delays only the above, the operation timing condition of each part inside the logic circuit to be inspected in the high-speed operation verification mode operating at the frequency F0 is assumed to be the actual use state. In addition to solving the above-mentioned problems by taking into consideration that the conditions of the operation timing of the normal operation mode operating at the frequency FX are matched, the actual device test using the logic circuit test device is performed more rigorously for actual use. The verification can be performed according to the state.

The operation of the present invention will be briefly described below.

The test target logic circuit targeted by the present invention is:
It is divided into a plurality of synchronous operation blocks. This synchronous operation block is provided with an I / O flip-flop at each input and output. These I / O flip-flops operate according to the clock signal input to the clock signal input. When a clock signal is input to the clock signal input of the I / O flip-flop provided at the input of the synchronous operation block, the signal is input to the synchronous operation block at this timing. On the other hand, when a clock signal is input to the clock signal input of the I / O flip-flop provided at the output of the synchronous operation block, the signal output from the synchronous operation block is input to the I / O flip-flop at the timing of this input. Captured and retained.

Here, the frequency of the system clock signal SCK, which is also the internal clock signal of the logic circuit to be inspected, is assumed to be frequency F0. Here, the frequency F0 assuming the actual usage state is referred to as a frequency FX. Then, in the present invention, in order to facilitate the verification of the normal operation of the logic circuit to be inspected in the high-speed operation verification mode using the logic circuit test apparatus, for example, the logic is inexpensive but the operation speed is relatively slow. For the convenience of using a circuit tester, the frequency F1 is defined as the frequency F0, which is lower than the frequency FX.
Further, for these frequency FX and frequency F1 or the period T1 (= 1 / F1) of the frequency F1, (FX = 1 / (T1
-Tp)) is defined.

For example, the frequency FX is 25 MHz and the frequency F1 is 20 MHz. Then, the phase difference time tp becomes 10 ns. Then, in such a case in which the verification target logic circuit is verified with the frequency F0 as the frequency F1, the system clock signal SCK and the test clock signal TCK of the present invention are as shown in FIG. Here, in the present invention, the input / output flip-flop of the synchronous operation block is operated at the rising edge of the system clock signal SCK, and the output I / O flip-flop of the synchronous operation block is operated at the rising edge of the test clock signal TCK. And the operation of the synchronous operation block is 40n
s need to be done. For example, it takes 40 ns from the rise of the pulse S1 of the system clock signal SCK to the rise of the pulse T2 of the test clock signal TCK in FIG.

Therefore, when the system clock signal SCK and the test clock signal TCK are used in this way, if the operation in the synchronous operation block takes 40 ns or more, the I / O on the output side of the synchronous operation block will be used.
The O flip-flop holds a different logic state than expected. Therefore, if the logic state held in the I / O flip-flop is confirmed, the cycle (= T1)
Assuming that the frequency is 50 ns and a frequency F1 of 20 MHz, it is verified that the synchronous operation block is normally operating at 40 ns, that is, normally operating at a frequency FX of 25 MHz (cycle 40 ns), for convenience of verification. be able to.

Therefore, in the present invention, when verifying the normal operation of the logic circuit to be inspected in the high-speed operation verification mode using the logic circuit testing device, the frequency F0 is suppressed to the frequency F1 to facilitate the verification. Thus, for example, the cost of the logic circuit test apparatus used can be suppressed. In addition, it is possible to verify the normal operation of the logic circuit to be inspected with the frequency F0 as if it were the frequency FX, while facilitating the verification in this way. As described above, according to the present invention, the operation speed of the input of the test pattern by the logic circuit test device and the operation speed of the monitor of the signal output from the logic circuit to be inspected by the logic circuit test device are suppressed while the logic circuit test device is being operated. By making it possible to verify the normal operation of the logic circuit to be inspected, which operates at a speed higher than the operation speed to be verified, it is possible to verify the normal operation of the logic circuit to be inspected with a logic circuit test device that is relatively easily available. It is also possible to obtain the excellent effect that the cost required for the logic circuit testing device can be reduced.

In the high speed operation verification mode, the test clock signal of the present invention is input to the clock signal input of the I / O flip-flop which is the output of the synchronous operation block. However, the test clock signal is provided at the output of the synchronous operation block for all I / Os.
There is no need to input to the clock signal input of the flip-flop. For example, the test clock signal may be input to the clock signal input of only the I / O flip-flop that inputs the output of the critical path in the synchronous operation block. If the test clock signal is input only to some I / O flip-flops of the I / O flip-flops of the output of the synchronous operation block, the high-speed operation of all of the synchronous operation blocks can be achieved by considering in this way. It is possible to verify and guarantee operation.

When the test clock signal whose phase is advanced by the phase difference time tp with respect to the normal clock signal is used for the I / O flip-flop of the output of the synchronous operation block, the I / O flip-flop outputs it. There is a risk that the signal timing will be advanced by the phase difference time tp, and will partly be inconsistent with the operation timing condition in the actual use state. In this regard, some delay circuit may be provided on the output side of the I / O flip-flop,
For example, inverters I20 and I21 used as delay circuits in the first embodiment described later, and I / O flip-flops FF32 and FF35 used as delay circuits in the second embodiment.
Can be dealt with as described above, and there is no particular problem. Here, such a delay circuit is referred to as a test operation timing adjustment delay circuit in the present invention.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings.

First, FIG. 4 is a circuit diagram of a test target logic circuit of the first embodiment to which the present invention is applied.

In FIG. 4, the synchronous operation block B2
Both 0 and B21 correspond to the synchronous operation block of the present invention. These synchronous operation blocks B20 and B21
Is a logic circuit composed of a combination circuit, the operation of which is completed within one period of the clock signal, that is, the system clock signal SCK or the test clock signal TCK. Further, I / O flip-flops FF20 to FF28 are provided at the inputs and outputs of the synchronous operation blocks B20 and B21, respectively. These I / O flip-flops FF20
The FFs 28 operate according to the clock signals input to the respective clock signals, that is, the system clock signal SCK or the test clock signal TCK.

In addition, in the logic circuit to be inspected in FIG. 4, the normal clock signal wiring for supplying the system clock signal SCK and the test clock signal TCK are used.
And a test clock signal wiring for supplying the operation mode setting signal TMD, and an operation mode setting signal wiring for supplying the operation mode setting signal TMD. The logic circuit to be inspected according to the present embodiment is built in a semiconductor integrated circuit, and an operation mode external setting terminal, that is, an operation mode setting signal TMD not shown in FIG. A terminal for inputting is provided.

Here, the multiplexer M20 inputs the clock signal of the I / O flip-flop FF24 provided at the output of the synchronous operation block B20 to the system clock signal SC according to the operation mode setting signal TMD.
Either K or the test clock signal TCK can be selectively input. That is, if the operation mode setting signal TMD is in the L state, it means that the normal operation mode for performing the normal operation is set from the outside. on the other hand,
When the operation mode setting signal TMD is in the H state, it means that the high-speed operation verification mode for performing the high-speed operation verification is set from the outside. Therefore, if the normal operation mode is set in the I / O flip-flop FF24 by the selection of the multiplexer M20, the system clock signal S
CK is input, and if the high-speed operation verification mode is set, the test clock signal TCK is input.

Next, the system clock signal SCK or the test clock signal TCK is input to the clock signal input of the I / O flip-flop FF28 provided at the output of the synchronous operation block B21 by the multiplexer M22 which operates according to the operation mode setting signal TMD. Is selectively input. That is, the I / O flip-flop FF28
To the clock signal input of 1, the system clock signal SCK is input when the normal operation mode is set by the operation mode setting signal TMD, and the test clock signal TCK is input when the high-speed operation verification mode is set.

The system clock signal SCK and the test clock signal TCK in this embodiment and the second embodiment to be described later are as described above with reference to FIG.
That is, the frequency FX in the actual use state is 25 MHz
(The cycle is 40 ns). In addition, the frequency F1 when verifying the normal operation using the logic circuit test device is 20 MH
z (the cycle is 50 ns). Further, the phase difference time tp in these embodiments is set to 10 ns.
Therefore, (FX = 1 / (T1-tp)) is established for the frequency FX, the frequency F1, and the phase difference time tp. However, T1 is the period of the frequency F1.

Therefore, in the present embodiment, first, the node N which becomes the critical path of the synchronous operation block B20.
I / O flip-flop FF2 provided at the output of 20
The present invention can be applied to No. 4. or,
The present invention can be applied to the I / O flip-flop FF28 provided at the output of the node N21 which is the critical path in the synchronous operation block B21. Therefore, the normal operation of these nodes N20 and N21 on the critical path can be verified while applying the present invention. Therefore, according to this embodiment, the operation speed of the test pattern input by the logic circuit test device and the monitor operation speed of the signal output from the logic circuit to be inspected by the logic circuit test device are suppressed while the logic circuit test device is used. By making it possible to verify the normal operation of the logic circuit to be inspected, which operates at a speed higher than the operation speed to be verified, it is possible to verify the normal operation of the logic circuit to be inspected with a logic circuit test device that is relatively easily available. It is also possible to obtain the excellent effect that the cost required for the logic circuit testing device can be reduced.

The output of the I / O flip-flop FF24 is provided with a buffer gate I20 having a delay time equal to the above-mentioned phase difference time tp and a multiplexer M21. When the high-speed operation verification mode is set by the operation mode setting signal TMD, the multiplexer M2
1 selects the output of the buffer gate I20. here,
In the high-speed operation verification mode, the system clock signal SCK
The I / O flip-flop FF24 operates according to the test clock signal TCK whose phase is earlier than
Although the output timing of the / O flip-flop FF24 is advanced, the output of the buffer gate I20 having the delay time tp is selected in the multiplexer M21.
The output of the I / O flip-flop FF24 is always input to the node N21 of the synchronous operation block B21 with the timing of the same condition regardless of whether it is in the high-speed operation verification mode.

Similarly, the I / O flip-flop FF28
A buffer gate I21 having a delay time equal to the above-mentioned phase difference time tp and a multiplexer M23 are provided at the output of the. As for the buffer gate I21 and the multiplexer M23, the buffer gate I2 described above is also used.
0 and the multiplexer M21 are used to correct that the timing of the signal output from the I / O flip-flop FF28 in the high-speed operation verification mode is advanced. Therefore, the condition of the operation timing of the signal output from the multiplexer M23 is always constant in both the normal operation mode and the high speed operation verification mode.

FIG. 5 is a circuit diagram of a second embodiment to which the present invention is applied.

The parts of the I / O flip-flops FF30 to FF32 and the multiplexer M30 of the second embodiment are the same as the I / O flip-flop FF of the first embodiment.
24, multiplexers M20, M21, and a buffer gate I20. Further, the portion composed of the I / O flip-flops FF33 to FF35 and the multiplexer M31 of the present embodiment is composed of the I / O flip-flop FF28, the multiplexers M22 and M23 and the buffer gate I21 of the first embodiment described above. It corresponds to the part.

In the normal operation mode, the multiplexer M30 which performs the selection operation according to the operation mode setting signal TMD selects the output of the I / O flip-flop FF30 which inputs the system clock signal SCK to the clock signal input, and the high speed operation verification mode. If so, the output of the I / O flip-flop FF31 and the I / O flip-flop FF32 for inputting the test clock signal TCK to the clock signal input is selected. Therefore, as for the output of the node N20 of the critical path of the synchronous operation block B20, the I / O flip-flop FF3 for inputting the system clock signal SCK (normal clock signal) in the normal operation mode.
0 is used, and I / O for inputting the test clock signal TCK (test clock signal) in the high-speed operation verification mode
The O flip-flop FF31 is used, and the present invention is applied to the output portion of the critical path, in which the normal operation needs to be verified.

Next, the multiplexer M31 operating according to the operation mode setting signal TMD selects the output of the I / O flip-flop FF33 which inputs the system clock signal SCK to the clock signal input in the normal operation mode, and in the high speed operation verification mode. Test clock signal T
The I / O flip-flop FF34 and the I / O flip-flop FF35 which input CK to the clock signal input are selected. Therefore, the present invention is applied to the node N21 of the critical path of the synchronous operation block B21,
As the I / O flip-flop provided at the output of the node N21, the one to which the system clock signal SCK (normal clock signal) is input is used in the normal operation mode, and the test clock is used in the high speed operation verification mode. A signal to which a signal TCK (test clock signal) is input is used, and the present invention is applied. As described above, the present invention is also applied to the present embodiment, and while suppressing the operation speed of the test pattern input by the logic circuit test device and the monitor operation speed of the signal output from the logic circuit to be inspected by the logic circuit test device, By making it possible to verify the normal operation of the test target logic circuit that operates at a speed higher than the operation speed verified by the circuit test device, the normal operation of the test target logic circuit can be relatively easily obtained by the logic circuit test device. Can be verified and the cost required for the logic circuit test device can be reduced, and so on.

The output of the I / O flip-flop FF31 used in the high speed operation verification mode of this embodiment is
Since the phase of the test clock signal TCK is earlier than the system clock signal SCK, the I / O flip-flop FF3
The signal output timing of 1 is advanced. In the present embodiment, the I / O flip-flop FF32 is arranged to absorb such an advance in signal output timing. The I / O flip-flop F
F32 operates according to the system clock signal SCK.

Similarly, the I / O flip-flop FF34 used in the high-speed operation verification mode also operates in accordance with the test clock signal TCK whose phase is earlier than that of the system clock signal SCK. The output timing has been advanced. In the present embodiment, the fact that the output timing is advanced in this way means that the I / O flip-flop F
By arranging F35, it absorbs. The I
The / O flip-flop FF35 operates according to the system clock signal SCK.

Comparing the first embodiment with the second embodiment, if the phase difference time tp is short, the first embodiment can reduce the number of elements such as transistors.
However, if the phase difference time tp is long, the number of elements such as transistors required for the inverters I20 and I21 used as the test operation timing adjustment delay circuit increases, and the number of elements decreases in the second embodiment. . Further, as compared with the first embodiment, the second embodiment has a shorter path of the system clock signal SCK and the test clock signal TCK to the clock signal inputs of the I / O flip-flops FF30 to FF35, and the timing is more improved. It can be set strictly. In the first embodiment, the multiplexers M20 and M22 are interposed in the paths to the clock signal inputs of the I / O flip-flops FF24 and FF25, which is disadvantageous in that the timing is set strictly.

[0042]

As described above, according to the present invention, the operation speed of the test pattern input by the logic circuit test device and the monitor operation speed of the signal output by the logic circuit test device by the logic circuit test device are suppressed. However, by making it possible to verify the normal operation of the test target logic circuit that operates at a speed equal to or higher than the operation speed verified by the logic circuit test device, this allows the test target logic circuit to be relatively easily obtained. It is possible to obtain the excellent effects that it is possible to verify the normal operation of (1) and to reduce the cost required for the logic circuit test device.

As a logic circuit testing device, for example, an ASIC
The tester has a fixed maximum operating frequency that can be verified by its performance. However, the operating speed of ASICs in recent years has become higher, and it is required to operate at higher speed on the board in the actual usage state than the maximum operating frequency that can be verified. It has become difficult to guarantee by verification using an ASIC tester. According to the present invention, it is possible to guarantee the normal operation at the actual higher operating frequency while verifying the normal operation by the ASIC tester at the operating frequency lower than the actual use state.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an example of a test target logic circuit that is a verification target of a conventional high-speed operation verification method for a logic circuit.

FIG. 2 is a time chart showing problems regarding normal operation verification of a test target logic circuit using a conventional logic circuit test apparatus.

FIG. 3 is a time chart showing the operating principle of the present invention.

FIG. 4 is a circuit diagram of a logic circuit to be inspected according to the first embodiment to which the present invention is applied.

FIG. 5 is a circuit diagram of a test target logic circuit of a second embodiment to which the present invention is applied.

[Explanation of symbols]

FF10-18, FF20-FF28, FF30-FF
35 ... I / O flip-flop B10, B11, B20, B21 ... Synchronous operation block N10, N11 ... Node I20, I21 ... Buffer gate M20-M23, M30, M31 ... Multiplexer SCK ... System clock signal TCK ... Test clock signal TMD ... Operation mode setting signals F0, F1, FX ... Frequency tp ... Phase difference time

Claims (2)

[Claims] 1. A logic circuit capable of sequentially monitoring a signal output from a logic circuit to be inspected while sequentially inputting a test pattern to the logic circuit to be inspected which operates at an operating speed assuming an actual use state. In a high-speed operation verification method for a logic circuit that verifies the normal operation of the logic circuit to be inspected at a required operation speed by using a test apparatus, the clock signal input is input to each input and output. The logic circuit to be inspected is provided in a synchronous operation block including an I / O flip-flop that operates according to a clock signal, the synchronous operation block including a combinational circuit configured to end the operation within a period of one cycle of the clock signal. External setting of normal operation mode for normal operation or high-speed operation verification mode for high-speed operation verification For setting the operation mode external setting terminal for inputting the operation mode setting signal, the normal clock signal wiring for supplying the normal clock signal of the frequency F0, and the frequency FX assuming the actual use state of the frequency F0. In order to verify the normal operation of the logic circuit to be inspected in the high-speed operation verification mode using the logic circuit test apparatus, a frequency whose frequency is suppressed to be lower than the frequency FX which is the frequency F0. F1 is defined, and these frequency FX and frequency F1 or the frequency F1
Of the cycle T1 (= 1 / F1) of (FX = 1 / (T
1-tp)), the test clock signal wiring for supplying the test clock signal of the frequency F0 whose phase is advanced by the phase difference time tp from the normal clock signal. A clock signal input to each of the I / O flip-flops provided in the output of the synchronous operation block that is provided in the target logic circuit and has an operation timing problem, and the normal clock in the normal operation mode A signal is input, the test clock signal is input in the high-speed operation verification mode, and the normal clock signal is input to the clock signal input of each of the I / O flip-flops other than these signals. When verifying the normal operation of the inspection target logic circuit in the high-speed operation verification mode using a test apparatus,
While suppressing the frequency F0 to the frequency F1 for convenience of verification, a clock signal of the frequency FX higher than the frequency F1 is pseudo-input to the clock signal input of each I / O flip-flop. A high-speed operation verification method for a logic circuit, wherein normal operation of the logic circuit to be inspected can be verified in a state. 2. The test operation according to claim 1, wherein, in the high-speed operation verification mode, a signal output from the I / O flip-flop provided at the output of the synchronous operation block is delayed by the phase difference time tp. By providing the timing adjustment delay circuit, the operation timing condition of each unit inside the inspection target logic circuit in the high-speed operation verification mode operating at the frequency F0 is set to the frequency FX assuming the actual use state. A method for verifying high-speed operation of a logic circuit, characterized in that the operation timing is matched according to the operation timing condition of the normal operation mode.