JPH1073642A - Integrated circuit with delay evaluation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable testing of delay time evaluation without giving a high speed clock from outside, by producing high speed clock signal with a ring oscillation circuit and controlling an oscillation period. SOLUTION: In a time setting circuit 1, the output of a ring oscillation circuit 11 connects to an external oscillation period monitor pin 13 via a scanning circuit for evaluation tests and the oscillation period is monitored with an external measuring system 4. Based on this oscillation period, the frequency division number of a variable frequency divider 12 is controlled from a setting input pin 14 by way of a frequency division number setting part 15, and a clock 16 for internal evaluation of period proper for delay time evaluation is produced with high accuracy. With the rise of this clock 16, the input data is latched 21 to input in a circuit to be measured 3, in the next rise of the clock 16, the output data is latched 21 to read out of the scanning circuit 23 with an external tester to check whether an expected output data is detected or not. Then, by changing the setting of frequency division number and changing the period of the clock 16, an exact delay time of the circuit to be measured 3 can be recognized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an integrated circuit capable of evaluating a delay time of an internal circuit of a high-speed semiconductor integrated circuit device or the like at a wafer test stage.

[0002]

2. Description of the Related Art With the recent increase in the speed of computers, the speed of LSIs used therein has been remarkably increased. However, with the speeding up of the LSI, the speed of the test equipment has
There is a problem that the signal propagation delay time (delay time) inside I cannot be accurately evaluated.

The delay time is a time from when input data is supplied to an internal combinational circuit to when output data corresponding to the input data comes out. This is performed by giving input data to a combinational circuit by giving a clock and determining whether or not output data has changed to expected data at the next clock. By changing the speed of this clock, the delay time until output data comes out can be detected. Moreover, the delay times for all the paths can be detected from the combination of the input and the output.

[0004] Also, due to the demand for multi-chip, a plurality of LSI chips are mounted on one module, and accurate delay time evaluation must be performed at the wafer stage before mounting on a module. It is not possible to solve the problem of defects caused by problems such as consistency with other chips.

[0005]

However, in order to perform an evaluation test of the delay time required at the wafer stage, it is necessary to supply a high-speed clock from outside through a contact means such as a probe. It is very difficult.

First, the accuracy of the external tester is not so high, and it is not possible to generate a high-accuracy high-speed clock corresponding to a short delay time inside the LSI. For example, if the LSI has a 200 MHz clock frequency, the clock cycle is as short as 5 nsec, and a current external tester can generate a clock with an accuracy of about ± 0.5 nsec at most. Therefore, it is not suitable for evaluating the delay time.

Second, with the increase in the number of pins of an LSI, it is difficult to use a probe that can accurately contact a large number of small input / output pads and has good high-frequency characteristics.

Therefore, as a conventional example, it has been proposed to form a closed loop inside an LSI by applying a control signal and to detect the speed of output data that changes due to the closed loop (for example, JP
57-197478). However, in such a method, the path in the circuit for measuring the delay time is fixed, and the delay time cannot be evaluated for all paths. Furthermore,
It is not always easy to form a closed loop in a complicated logic circuit, and it is necessary to perform a closed loop operation every time one path is measured, which increases the measurement time.

SUMMARY OF THE INVENTION An object of the present invention is to provide an integrated circuit that can solve the above-mentioned problems and perform a highly accurate delay time evaluation test at the wafer stage.

Another object of the present invention is to provide an integrated circuit capable of performing a highly accurate delay time evaluation test at the wafer stage without requiring a clock from an external tester.

Another object of the present invention is to provide an integrated circuit capable of performing a highly accurate delay time evaluation test without requiring a clock from an external tester.

[0012]

SUMMARY OF THE INVENTION According to the present invention, there is provided a delay evaluation circuit for evaluating a delay time from when input data is supplied to an internal circuit to be measured until the output data is generated. A delay setting circuit having an oscillation circuit, a variable frequency dividing circuit for variably dividing the output of the oscillation circuit, and a means for externally setting the frequency dividing number; and A latch circuit is provided at an input stage and an output stage of the circuit under test and latches at a timing of an internal clock from a variable frequency dividing circuit of the time setting circuit, and means for outputting latch data of the latch circuit is provided. This is achieved by providing an integrated circuit as follows.

Further, the integrated circuit of the present invention has a plurality of the circuits to be measured, and the latch circuits are arranged at an input stage and an output stage of each of the circuits to be measured, and supply of the internal clock to the latch circuits. Is performed in accordance with an external address signal, and the output of the latch data of the latch circuit is performed in accordance with an external address signal.

With such a configuration, the integrated circuit can generate an internal clock having a desired and accurate cycle by itself, so that an internal high-speed measurement can be performed without receiving a high-speed clock from an external tester. The delay time of the circuit can be measured. In addition, since the internal clock can be set to an arbitrary period from the outside, more accurate measurement of the delay time can be performed.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, such embodiments do not limit the technical scope of the present invention.

FIG. 1 is a schematic block diagram of an integrated circuit according to an embodiment of the present invention. In the figure, reference numeral 3 denotes an internal circuit to be measured such as a combinational circuit. Normally, the latch circuit 21 captures input data in synchronization with the clock 31, supplies the input data to the combination circuit 3, and captures the result in the latch circuit 21 on the output side. Then, data is transferred to the next stage in synchronization with a clock supplied to the latch circuit 21 on the output side.

In the example of FIG. 1, as a circuit for delay time evaluation, the latch circuit 21 is first modified so that data can be read from the scan circuit 23 during an evaluation test. An address setting circuit 22 for generating an address set by the setting input pin 14
Thus, the address is given to each latch circuit 21 and the like, and the data of the selected latch circuit is
Output. Up to this point, it has also been realized with a normal integrated circuit.

In the example of FIG. 1, a time setting circuit 1 for generating a high-speed internal clock 16 during an evaluation test is provided. In this time setting circuit 1, a ring oscillation circuit 11,
A variable frequency divider 12 and a frequency division number setting unit 15 are provided. By having the time setting circuit 1 inside itself, there is no need to provide a high-speed clock for evaluation from an external tester.

In addition, the time setting circuit 1 can generate a clock signal with extremely high accuracy. That is, the output of the ring oscillation circuit 11 is used as the scan circuit 23 for the evaluation test.
Is connected to an external oscillation cycle monitor output pin 13 and the oscillation cycle is monitored by an external measuring instrument. Usually, characteristics such as internal transistors and resistors vary due to an LSI manufacturing process or the like, and the oscillation cycle of the ring oscillation circuit also varies. Therefore, the frequency division number of the variable frequency divider 12 is adjusted from the setting input pin 14 via the frequency division number setting unit 15 based on the oscillation cycle monitored and detected externally. As a result, it is possible to generate the internal clock 16 having a cycle suitable for delay time evaluation with high accuracy. In addition, it is possible to generate the clock 16 having an arbitrary oscillation cycle for delay time evaluation.

In this way, as described above, the input data is latched by the internal clock 16 having an accurate period in the delay evaluation latch circuit 21 at the rising edge of the clock 16 and input to the circuit under test 3, Next clock 16
The data of the latch circuit 21 on the output side at the time of the rising edge is read out from the scan circuit 23, and it is checked by an external tester whether or not the expected output data is detected. Then, by changing the setting of the frequency division number to the time measuring circuit and changing the period of the internal clock 16, it is possible to know the exact delay time of the circuit under test. Also, by focusing on a specific input terminal and a specific output terminal, the delay time of a specific path can be measured.

FIG. 2 is a detailed block diagram of the delay evaluation latch circuit 21. The latch circuit 211 has, in addition to the latch function used during normal operation, a function for a scan circuit so that its output can be supplied to the scan circuit 23 during a test. Therefore, the clock signal is supplied from the external clock 31 during the normal operation and from the internal clock 16 during the delay evaluation test. These clocks are switched by the switch 212. Moreover,
The switch circuit 212 is switched by the output of the decoder 214 for decoding the address signal from the address setting circuit 22. Further, a set reset signal S / R is applied to the latch circuit 211.

FIG. 3 is a circuit diagram of another example of the embodiment of the present invention. This example is the same as FIG. 1 in that the time setting circuit 1 is adjusted from the setting input pin 14 so that an accurate internal clock signal 16 can be generated. This example is different in that there are a plurality of circuits to be evaluated, 3A and 3B, and each of the circuits to be evaluated 3A and 3B can be individually subjected to delay evaluation. Accordingly, the delay evaluation latch circuit 21 is provided on the input side and the output side of the circuit under test 3A and the input side and the output side of the circuit under test 3B, and supplies the input data and detects the output data at the timing of the internal clock 16. Is performed. Latch circuit 21 selected by address
, The internal clock 16 can be given, and the delay time of each circuit to be measured can be measured individually. The scan circuit 23 is configured to scan the outputs of all the latch circuits.

Further, the high-speed internal clock 16 can be applied only to the latch circuit 21 selected by the address, and the internal clock 16 having a desired speed can be applied to each circuit to be measured. The accuracy of the internal clock 16 can be kept high by monitoring the oscillation cycle of the ring oscillation circuit externally during the evaluation.

FIG. 4 shows a latch circuit 21 for delay evaluation.
2 is a circuit layout diagram in which LSIs are fixedly arranged in an LSI chip 100. FIG. A delay evaluation latch circuit group 21 is fixedly formed in an area between the circuits 3 to be measured arranged separately in four blocks and in a peripheral portion of the chip 100. In addition, an I / O circuit 5 is also provided on the periphery of the chip 100.

With the fixed formation, the power supply to the dedicated power supply line of the latch circuit group 21 is turned off in order to reduce the power consumption after the evaluation test is completed. Becomes possible.

FIG. 5 shows a latch circuit 2 for delay evaluation.
FIG. 1 is a circuit layout diagram in which 1 is arranged only on the periphery of an LSI chip 100. In this example, since the latch circuit 21 for delay evaluation is provided only on the peripheral portion, the circuit under test 3 can be relatively freely arranged in the chip.

[0027]

As described above, according to the present invention, a high-speed clock signal for a delay time evaluation test can be generated by an internal ring oscillation circuit, and the oscillation cycle can be adjusted. The delay time evaluation test can be performed without supplying a high-speed clock from an external tester or the like. Therefore, a highly accurate delay evaluation test can be performed at the wafer stage, and the yield of the multi-chip module can be increased.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of an integrated circuit according to an embodiment of the present invention.

FIG. 2 is a detailed block diagram of a delay evaluation latch circuit 21;

FIG. 3 is a circuit diagram of another example of the embodiment of the present invention.

4 is a circuit layout diagram in which a delay evaluation latch circuit 21 is fixedly arranged in an LSI chip 100. FIG.

FIG. 5 is a circuit layout diagram in which a delay evaluation latch circuit 21 is arranged only at a peripheral edge of an LSI chip 100.

[Explanation of symbols]

 Reference Signs List 1 time setting circuit 3 circuit under test 11 oscillation circuit 12 variable frequency divider 13 frequency division number setting section 14 setting input pin 16 internal clock 21 latch circuit 22 address setting circuit 23 scan circuit

Claims (2)

[Claims] An integrated circuit provided with a delay evaluation circuit for evaluating a delay time from when input data is supplied to an internal circuit to be measured to when the output data is generated, wherein the delay evaluation circuit includes an oscillation circuit. A variable frequency dividing circuit for variably dividing the output of the oscillation circuit, a time setting circuit having means for externally setting the frequency division number, and a time setting circuit disposed at an input stage and an output stage of the circuit under test; An integrated circuit, comprising: a latch circuit for latching at a timing of an internal clock from a variable frequency dividing circuit of the time setting circuit; and means for outputting latch data of the latch circuit. 2. The integrated circuit according to claim 1, further comprising a plurality of said circuits under test, wherein said latch circuits are arranged at an input stage and an output stage of each of said circuits under test, and said internal clock to said latch circuit is provided. Is supplied in accordance with an external address signal, and the latch circuit outputs latch data in accordance with an external address signal.