JP2008209201A - Current measuring method and semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique which enables current measurement for each functional block, after chip manufacturing. <P>SOLUTION: Supply of a clock signal to functional blocks other than a functional block being an object of current measurement out of a plurality of functional blocks (2A-2D) is stopped, and a built-in self test circuit and a scan circuit are operated in the functional block which is the object of current measurement. Under this condition, current flowing in a power source terminal (11) of a semiconductor integrated circuit chip is measured. Since the supply of the clock signal, here, to the other functional blocks excluding the functional block being the object of current measurement is stopped, current measurement for each functional block becomes possible. Moreover, since the current measurement for each functional block is made possible by measuring the current flowing through the power source terminal of the semiconductor chip (1), current measurement, after the manufacture of the chip, becomes possible. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a current consumption evaluation technique in a semiconductor integrated circuit.

  With the progress of miniaturization, the degree of integration of LSI is improved, and a plurality of functional blocks are mounted on a chip, thereby forming a SoC (System on Chip). The functional blocks include circuit blocks formed to perform predetermined functions such as a microcomputer and its peripheral circuits. Battery-powered digital devices such as mobile phones and PDAs also have a built-in SoC and execute various application software. These battery-driven digital devices are strongly required to have low power consumption, and fine power control is performed by hardware on the SoC and software operated on the SoC. Evaluation of power consumption is indispensable in reducing SoC power consumption. In general, it is evaluated which part of the SoC consumes how much power before and after the SoC chip is manufactured. Then, if necessary, a policy for reducing power consumption is established, and the effect of reducing power consumption is investigated.

  In power evaluation at a stage before chip manufacture, gate simulation using a specific short function test pattern signal has been conventionally performed. The power values of all gates are accumulated from the inversion numbers (called toggles) of 0 and 1 of the output nets of all gates. According to this gate simulation, although the accuracy is high, (a) the execution speed is slow because of the gate simulation, (b) the pattern signal is for a short function test, and the pattern signal at the actual application level cannot be executed in real time. There are points to be improved, such as (c) a large number of man-hours for developing test pattern signals, (d) it is necessary to prepare a test pattern signal for each functional block in order to evaluate the power of each functional block.

  Regarding the above (a) and (b), power evaluation using an FPGA in which a toggle counting circuit is embedded has been proposed (for example, see Patent Document 1). Regarding the above (c) and (d), automation of a test pattern signal by ATPG has been proposed (for example, see Patent Document 2).

  After chip manufacture, test pattern signal current measurement by a tester or test pattern signal current measurement by a mounting board is performed. After actual application software is developed, power is measured by the mounting board. The current is measured by inserting an ammeter in series with a jumper external to the SoC or using a current probe.

  However, a single functional block cannot be measured with the test pattern signal. Current measurement is performed in a state where a plurality of functional blocks such as a clock signal control unit, a bus, and a microprocessor are operating. Conventionally, the differential current is measured by turning on and off the clock signal by the clock signal control register. However, the function block having no control register bit cannot be measured by the differential current.

JP 2002-288257 A JP 2003-85233 A

  According to Patent Document 1, the toggle count can be speeded up by embedding a toggle count circuit in an FPGA (Field Programmable Gate Array). The toggle counting circuit is a function that is not mounted on an actual product but is mounted only on the FPGA. The toggle counting circuit includes a flip-flop circuit, an EOR (exclusive OR) gate, and an adder, and is inserted into the output of each gate excluding the inverter and the buffer. The toggle result is output by the scan chain. According to the study of the present inventor, the toggle counting circuit in this case has a large logical scale because it includes a single FF (flip-flop circuit) and an adder, and there are many target portions because it is inserted into each gate, It has been found that the overall circuit scale of the toggle counting circuit is very large.

  The technique described in Patent Document 2 is power evaluation based on simulation, and does not support measurement with an actual chip.

  Then, after the chip is manufactured, the difference current is measured by turning on and off the clock signal by the clock signal control register for the measurement of the single functional block in the test pattern signal as described above. For functional blocks that do not have control register bits, measurement using the differential current is not possible. Further, in order to be able to measure a single functional block on an actual chip, the circuit must be operated independently so that only a single functional block is operated.

  However, there is no description or suggestion in the above-mentioned patent document about performing current measurement of a single functional block in an actual chip.

  An object of the present invention is to provide a technique that enables current measurement for each functional block in an actual chip after chip manufacture.

  Another object of the present invention is to provide a semiconductor integrated circuit capable of operating a circuit independently to enable current measurement of a single functional block on an actual chip.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  A representative one of the inventions disclosed in the present application will be briefly described as follows.

  That is, the supply of the clock signal is stopped for the other functional blocks excluding the functional block that is the current measurement target among the plurality of functional blocks, and the built-in self-test circuit in the functional block that is the current measurement target; The scan circuit is operated. In this state, the current flowing through the power supply terminal of the semiconductor integrated circuit chip is measured.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, it is possible to provide a technique that enables current measurement for each functional block in an actual chip after chip manufacture.

1. Representative Embodiment First, an outline of a typical embodiment of the invention disclosed in the present application will be described. The reference numerals in the drawings referred to with parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

  [1] A current measurement method according to a representative embodiment of the present invention stops the supply of the clock signal for the other functional blocks excluding the functional block that is the current measurement target among the plurality of functional blocks, and Then, the current flowing through the power supply terminal of the semiconductor integrated circuit chip is measured in a state where the built-in self-test circuit and the scan circuit in the functional block that is the current measurement target are operated.

  According to the above configuration, the current flowing through the power supply terminal of the semiconductor integrated circuit chip is measured in a state where the built-in self-test circuit and the scan circuit in the functional block that is a current measurement target are operated. At this time, the supply of the clock signal is stopped for the other functional blocks excluding the functional block that is the current measurement target, so that the current measurement for each functional block is possible. Moreover, since the current measurement for each functional block is made possible by measuring the current flowing through the power supply terminal of the semiconductor integrated circuit chip, it is also possible to measure the current for each functional block in the actual chip.

  [2] At this time, supply of the clock signal is stopped for the other functional blocks excluding the functional block that is the current measurement target among the plurality of functional blocks, and the functional block that is the current measurement target The semiconductor integrated circuit in a state in which supply of the clock signal is stopped for all of the plurality of functional blocks and the current flowing through the power supply terminal of the semiconductor integrated circuit chip in a state where the built-in self-test circuit and the scan circuit are operated By obtaining the difference from the current flowing in the power supply terminal of the chip, the actual operating current for each functional block can be obtained.

  [3] According to another aspect of the present invention, a clock signal is selected for a plurality of functional blocks (2A, 2B, 2C, 2D) and a functional block to be measured for current among the plurality of functional blocks. And a control circuit (4) that can be supplied in an integrated manner to constitute a semiconductor integrated circuit. At this time, the functional block is generated by the built-in self-test circuit (6) capable of generating a pattern signal for self-diagnosis based on the clock signal supplied by the control of the control circuit, and the built-in self-test circuit. The pattern signal is configured to include a scan circuit (SCN-CHN) that can scan in synchronization with the clock signal supplied by the control of the control circuit.

  According to said structure, since supply of the said clock signal can be stopped about other functional blocks except the functional block used as electric current measurement object, the electric current measurement for every functional block is attained. In addition, since the current measurement for each functional block is made possible by measuring the current flowing through the power supply terminal of the semiconductor integrated circuit chip, the current measurement in the actual chip is possible.

  [4] The functional block includes a logic gate (13) that can control the supply of the clock signal to the built-in self-test circuit and the scan circuit in accordance with an enable signal supplied from the control circuit. it can.

  [5] The function block may be provided with a randomly accessible memory (8). In that case, the built-in self-test circuit is written in the first built-in self-test circuit (6A) capable of generating a pattern signal supplied to the scan circuit for self-diagnosis and the memory for self-diagnosis. And a second built-in self-test circuit (6B) capable of generating a pattern signal.

  [6] The functional block includes a plurality of flip-flop circuits (22) capable of scanning in and scanning out the pattern signal generated by the built-in self-test circuit in synchronization with the clock signal, and an output in the flip-flop circuit A logic power information detection unit (30) capable of detecting the power of the logic unit including the flip-flop circuit based on the number of logic toggles; and a memory power information detection unit (31) capable of detecting the power of the memory. Can be configured.

  [7] The functional block may include a gate circuit (32) that obtains an exclusive OR of data input to the flip-flop circuit and data output from the flip-flop circuit. In that case, the logic power information detection unit accumulates the number of toggles of the flip-flop circuit by counting the output of the gate circuit during a measurement cycle, and the power of the logic unit is based on the accumulation result. It can be configured to perform detection.

  [8] The memory power information detection unit can be configured to use a signal weighted by a predetermined coefficient with respect to an enable signal that can select the memory unit as information for calculating a current value of the memory unit. .

2. Next, the embodiment will be described in more detail.

  FIG. 1 shows a system on chip (SoC) 1 to which a first embodiment of a semiconductor integrated circuit according to the present invention is applied. The system-on-chip 1 is not particularly limited, but is formed on one semiconductor substrate such as a single crystal silicon substrate by a semiconductor integrated circuit technology for forming a known CMOS (complementary MOS transistor), bipolar transistor, or the like. .

  The system-on-chip 1 includes function blocks (FB) 2A, 2B, 2C, and 2D that realize predetermined functions, a PLL (phase-locked loop) 3 that forms a clock signal, a control unit (CTL) 4, and a function block An internal bus 9 and an internal bus control unit (BC) 5 are used to connect each other. Although not particularly limited, the internal bus 9 is a crossbar type, and the internal bus control unit 5 performs switch control of the internal bus 9. Power supply terminals 11 and 12 are provided, and power supply voltages VDD and VSS are taken in via the power supply terminals 11 and 12.

  The PLL 3 outputs a user clock signal usr_ck and a test clock signal tst_ck. The input clock signal ck at the time of testing the functional blocks 2A, 2B, 2C, and 2D is different between the testing of the functional blocks 2A, 2B, 2C, and 2D and the operation other than the test (normal operation). That is, during the test, the test clock signal tst_ck is selectively transmitted to the functional blocks 2A, 2B, 2C, and 2D and the control unit 4 by the selector SEL. During normal operation, the selector SEL selectively transmits the user clock signal usr_ck to the functional blocks 2A, 2B, 2C, 2D and the control unit 4. Operation control of the selector SEL is performed by the control unit 4. The controller 4 outputs an operation control signal cnt for the selector SEL, a clock enable signal cken indicating the validity of the clock signal, and a test related signal tet_sig. The clock enable signal cken and the test related signal tet_sig are supplied to the functional blocks 2A, 2B, 2C, and 2D.

  FIG. 2 shows a configuration example of the functional block 2A.

  The functional block 2 </ b> A includes a BIST (built-in self test) circuit 6, a logic (LGC) unit 7, a memory (MEM) unit 8, and a two-input AND gate 13. The logic unit 7 includes combinational circuits 29A, 29B, 29C, and 29D, and a plurality of flip-flop circuits 22 with scan terminals connected to the combinational circuits 29A, 29B, 29C, and 29D by a scan chain SCN-CHN. The flip-flop circuit 22 with a scan terminal includes a scan-in terminal SI, a data terminal D, a clock terminal, a scan-out terminal SO, and a test terminal TST. The scan-out terminal SO of the flip-flop circuit 22 with scan terminal is coupled to the scan-in terminal SI of another flip-flop circuit 22 with scan terminal, thereby forming a scan chain SCN-CHN.

  The memory unit 8 includes a plurality of SRAMs (Static Random Access Memory) 23 coupled to the logic unit 7. The SRAM 23 receives a clock signal clk, a clock enable signal cen, and a test enable signal ten. The clock signal clk and the clock enable signal cen are generated by the logic unit 7. The test enable signal ten is generated by the control unit 4.

  The BIST circuit 6 includes a logic BIST unit 6A corresponding to the logic unit 7 and a memory BIST unit 6B corresponding to the memory unit 8. The logic BIST unit 6A includes a logic random pattern generation unit (LRPG) 20 that generates a random pattern signal, and a logic test output compressor (LTOC) 21 that compresses a test result. The memory BIST unit 6B includes an address generator (ADR_GEN) 24, a data generator (DATA_GEN) 25, a control unit (MBIST_CTL) 26, and a memory output comparator (MCMP) 27. As a test-related I / F, a test mode, a test clock signal, and input / output data are collectively used as a test-related signal tst_sig. The 2-input AND gate 13 obtains an AND logic between the input clock signal ck and the clock enable signal cken. The input clock signal ck is transmitted to the logic unit 7 and the memory unit 8 while the clock enable signal cken is at a high level.

  The other functional blocks 2B, 2C, and 2D are configured similarly to the functional block 2A.

  FIG. 4 shows a state of actual measurement of the current flowing through the functional block 2A in the system-on-chip 1.

  The system on chip 1 is mounted on the SoC mounting board 60. A power supply voltage is supplied from the power supply device 66 to the power supply terminal 67 of the SoC mounting board 60. The power supply voltage supplied from the power supply device 66 is supplied to the system on chip 1 via the jumper 68. A high precision current probe 61 is connected to the oscilloscope 62. When the tip of the high-accuracy current probe 61 is brought close to the jumper 68, information on the current flowing through the jumper 68, that is, the current flowing through the system-on-chip 1 can be displayed on the oscilloscope 62. An enlarged display screen 62DSP of the oscilloscope 62 shows a current measurement result when the logic BIST (LBIST) 6A is used. Reference numeral 64 denotes a period during which scan-in is performed with the scan chain SCN-CHN. Reference numeral 63 denotes a period during which the user clock signal is actually operated. Reference numeral 65 denotes a scan-out period. Taking the difference between the actual operating current 66 when the user clock signal usr_ck is used and the current 67 of the PLL 3 and the control unit 4 when the clock signals of the functional blocks 2A, 2B, 2C, and 2D are stopped, the actual operating current for each functional block is Desired. For example, when only the clock enable signal cken for the functional block 2A is set to the high level and the supply of the clock signal to the other functional blocks 2B, 2C, 2D is stopped, the actual operating current for the functional block 2A is Desired.

  FIG. 5 shows the flow of current measurement.

  First, a functional block to be subjected to current measurement is selected (501). Then, it is determined whether or not the measurement is finished (502), and whether or not the logic current is measured is determined (503). Here, it is assumed that the functional block 2A is selected and current measurement is performed using the logic BIST (LBIST) unit 6A. When the functional block 2A is selected and current measurement is performed using the logic BIST unit 6A, the supply of the clock signal to the other functional blocks 2B, 2C, 2D and the bus control unit 5 is stopped. The parts that always operate are the PLL 3 and the control unit 4. The PLL 3 may be a separate power source. The logic BIST unit 6A is set (504), and the generated random pattern signal is sequentially transmitted to the flip-flop circuit 22 connected by the scan chain SCN-CHN in synchronization with the clock signal tst_ck (505, 506). The clock signal at the time of scanning is the test clock signal tst_ck among the outputs of the PLL 3. When the values of all the flip-flop circuits are set in the scan chain, one cycle operation is performed by the user clock signal usr_ck selected by the control unit 4, and the flip-flop circuit value captured after the operation is again generated by the clock signal tst_ck in the scan chain. The data are sent in order, and the result is compressed in the BIST and output outside the chip (507 to 509). Although omitted in FIGS. 1 and 2, a plurality of clock signals having different frequencies can be used as the user clock signal. The period during which the current is measured is an operation portion (one clock signal) based on the user clock signal. Since the current of the PLL 3 and the control unit 4 is obtained in the user clock signal stop state after the scan shift, the function is determined by the difference between the current 66 when the user clock signal is supplied and the current 67 of the user clock signal stop state after the scan shift. The current of block 2A can be determined.

  Next, a case where the current of the memory unit 8 is measured using the memory BIST (MBIST) unit 6B will be described.

  If it is determined in step 503 that the logic current is not measured (no), the memory BIST unit 6B is set to measure the current in the memory portion (510). After the memory BIST unit 6B is set, the address, data, and expected value of the generated memory pattern signal such as marching are generated (511). Then, the SRAM 23 is actually operated. In this actual operation, the data stored in the SRAM 23 is read and compared with the expected value (513). In this actual operation, current measurement is performed (512). The operation part in the current measurement period is only the PLL 3, the control unit 4, and the functional block 2A. When the user clock signal is stopped after the end of the memory pattern signal, the current at that time is only the PLL 3 and the control unit 4, so that when the current is measured using the logic BIST unit 6 A, By obtaining the difference when the user clock signal is stopped, the current of the functional block 2A can be obtained.

  The other functional blocks can measure the current independently as well. Usually, the current measurement uses a test pattern signal in consideration of logic operation. In this case, the operation of a plurality of functional blocks and the portion where the clock signal cannot be controlled, for example, the bus control unit always operates, but the random pattern generated by BIST6 does not need to consider the logical operation, so the scan chain or the like The current can be measured only at the logically closed location. In this example, the scan chain is separated for each functional block. For this reason, in the above current measurement, no current is consumed in other functional blocks due to clock signal control.

  It should be noted that current measurement can also be performed using the logic BIST unit 6A and the memory BIST unit 6B simultaneously.

  FIG. 3 shows the state of the functional block when the clock signal is stopped using the clock signal enable cken.

  When the clock signal enable cken is negated, the clock signal of the flip-flop circuit of the functional block is stopped, and the output logic of the flip-flop circuit is fixed. The operation of the combinational circuit (cmbB) 81 and the combinational circuit (cmbC) 82 is stopped because the input of the combinational circuit is fixed. At this time, the output interface out_IF of the functional block is fixed. Since the output interface is considered to be fixed when the clock signal enable is negated for other function blocks, the input interface of the function block is stopped except for the interface between the frequency divider and the clock signal control unit. . In FIG. 3, since all the input interfaces in_IF are stopped, the combinational circuit cmdA 80 that receives the input interface in_IF is also stopped. Therefore, when the clock signal enable is negated, the operation of most of the gates of the functional block is stopped, so that no current is consumed there.

  In the current measurement shown in FIG. 5, since the BIST is a random pattern, the current fluctuation is predicted by this pattern signal. Therefore, the current measurement of the logic BIST unit 6A and the memory BIST unit 6B is performed a plurality of times, and statistical processing such as averaging and dispersion is performed, thereby improving the accuracy of current calculation of the functional block.

  According to the above example, the following operational effects can be obtained.

  (1) A dedicated BIST circuit 6 is provided in each of the functional blocks 2A, 2B, 2C, and 2D. The logic unit 7 automatically generates pattern signals using the logic BIST unit 6A and the memory unit 8 uses the memory BIST unit 6B. be able to. A random pattern generator (LRPG) 20 in the logic BIST unit 6A generates a pattern signal for scanning, and an address generator 24, a data generator 25, and a control unit 26 in the memory BIST unit 6B test patterns such as marching and checker boards. A signal is generated. The current of the functional block can be measured by using a plurality of automatically generated pattern signals for failure detection and following the measurement flowchart of FIG. During the operation based on the user clock signal, the logic BIST unit 6A can be used to consume current only by the logic unit 7, and the memory BIST unit 6B can be used to consume current only by the memory unit 8.

  (2) By controlling whether or not the clock signal is supplied by the control unit 4, the circuit can be operated independently in order to enable the current measurement of a single functional block in the actual chip. Moreover, said structure can perform the electric current reduction at the time of an SoC test as another usage. For example, when performing a test of the functional block FB_A, particularly a built-in self-test, it is possible to reduce current during the test by stopping functional blocks other than the functional block to be tested, for example, FB_B, FB_C, FB_D, and BC .

  Next, a case where logic is implemented in the FPGA and current evaluation is performed at high speed will be described as a second embodiment.

  Since the FPGA operates at several tens of MHz, it is several hundred times faster than RTL (register, transfer level hardware description language) and gate simulation. However, since the mounting rate is low, the additional circuit for current evaluation must be made as small as possible.

  In FIG. 6, the functional block (FB) according to the second embodiment of the present invention is formed by FPGA. The functional block 2A shown in FIG. 6 is greatly different from that shown in FIG. 2 including a logic power information detection unit (PWR_LGC) 30 and a memory power information detection unit (PWR_MEM) 31, The strobe signal strb is used as a signal. In the FPGA, since it is not necessary to detect a failure, there is no need for LBISTTMBIST.

  The logic unit 7 includes the combinational circuits 34A, 34B, 34C, 34D, 34E, and 34F and a plurality of flip-flop circuits 22. The flip-flop circuit 23 is accompanied by combination circuits 34A to 34F of a certain scale. It shall be. For example, assume that a 100-gate combination circuit is attached to a 1-bit flip-flop circuit on average. Then, by measuring the number of toggles from the logical value “0” to the logical value “1” and from the logical value “1” to the logical value “0” in the flip-flop circuit 22, the number of toggles of the associated gate is determined with an appropriate probability. Assume to toggle. For example, assume that 10% of the output of 100 gates toggles when a 1-bit flip-flop circuit toggles. The number of gates attached to these flip-flop circuits may be calculated in advance from the function blocks of some products by checking the gates in advance. By measuring the number of toggles of the flip-flop circuit in this way, the number of toggles of the logic unit 7 can be estimated. Therefore, the current can be estimated using a capacity parameter such as process and area. In the logic unit 7, an EOR gate 32 that takes an exclusive OR of the output and input of each flip-flop circuit 22 is coupled to the flip-flop circuit 22, and an output signal of the EOR gate 32 is a logic power information detection unit (PWR_LGC) 30. Is input. The memory unit 8 is provided with a plurality of SRAMs 23 such as a compiled RAM. The power of the SRAM 23 can be calculated by using parameters such as the clock signal, chip enable, and size of each SRAM. Therefore, the clock signal clk 54 and clock enable signal cen of each SRAM 23, and coefficients taking into account parameters such as size are used.

  FIG. 8 shows a configuration example of the logic power information detection unit 30.

  The logic power information detection unit 30 has a function of detecting power for each logic circuit based on the number of toggles of the output logic in the flip-flop circuit, and is not particularly limited, but includes a toggle counter (CNT) 40, an adder (+) 41, a logic toggle holding register (LREG) 42, a measurement cycle number holding register 45, and an incrementer (INC) 46. N (where N represents a positive integer other than 0) toggle number ff_toggle of flip-flop circuits and a strobe signal strb indicating the measurement period of flip-flop circuit 42 are input to flip-flops in logic toggle holding register 42 The count number of the circuit is held. The measurement cycle number holding register 45 holds the measurement cycle number while incrementing it by the incrementer 46 one cycle during the assertion period of the measurement strobe signal. Output signals of the plurality of EOR gates 32 are transmitted to the toggle counter 40. The number of toggles of the flip-flop circuit is summed by the toggle counter 40 to have a log (N + 1) bit width, and the number of toggles of a plurality of cycles is accumulated by the adder 41. The larger the cumulative number of toggles, the more power is consumed. Therefore, the power for each logic circuit can be detected based on the cumulative number of toggles. Since the logic toggle holding register 42 and the measurement cycle number holding register 45 are memory mapped registers having addresses, the registers can be read / written from the internal bus 9 by address designation.

  FIG. 9 shows a configuration example of the memory power information detection unit 31.

  The memory power information detection unit 31 has a function of using a signal weighted by a predetermined coefficient for the clock enable signal cen for selecting the memory as information for calculating the current value of the memory, but is not particularly limited. AND gate 50 for obtaining AND logic of clock enable signal cen and clock signal clk, and AND logic of coefficient information Coeff1 for corresponding to different power values by parameters such as size, and output signal of buffer 58 An AND gate 51, an adder 52, a memory power information holding register (MREG) 53, a measurement cycle number holding register 56, and an incrementer (INC) 57 are included. The clock enable signal cen and the clock signal clk and the corresponding logic circuits 50 to 51 correspond to the plurality of SRAMs 23 shown in FIG. The coefficient weights current information according to the type of memory, for example, single port, dual port, register file, ROM, or the size of 1 kB or 16 kB. The adder 42 accumulates memory information of a plurality of cycles. The measurement cycle number holding register 56 holds the number of measurement cycles while the incrementer 57 adds one by one during the assertion period of the measurement strobe signal. The measurement cycle number holding register 56 and the incrementer 57 may be shared with the logic power information detection unit 30. Since the memory power information holding register 53 and the measurement cycle number holding register 56 are memory mapped registers having addresses, each register can be read / written from the internal bus 9 by address designation.

  FIG. 7 shows a flow of current measurement when the configuration shown in FIG. 6 is adopted.

  The current measurement may be performed by either the normal program or the logic BIST unit 6A or the memory BIST unit 6B of the test automatic generation pattern (701). Although the logic unit 7 and the memory unit 8 can measure simultaneously, since the setting method and the measuring method are different, they are separated in this flowchart for convenience of explanation.

  First, a case where the logic unit 7 is measured, that is, a case where “yes” is determined in the determination in step 702 will be described.

  The logic toggle holding register 42 and the measurement cycle number holding register 45 are initialized (703). To start measurement, the strobe signal strb is asserted (704). The measurement strobe signal is generated by the control unit 4. A memory-mapped register for generating a strobe signal may be provided in the control unit 4 so that the measurement period can be set by software. The toggle sum of the flip-flop circuit of the logic unit 7 is obtained by counting the output of the EOR gate 32 (705). The number of measurement cycles can be obtained by updating the strobe signal every cycle. During the measurement cycle, the number of toggles of the flip-flop circuit is accumulated (706). The end of measurement can be known by negating the strb signal (707). Based on the accumulation of the number of toggles of the flip-flop circuit and the number of effective cycles, the toggle of the combinational circuit connected to the FF is also taken into consideration, and a current value converted from the accumulation of the number of toggles of the flip-flop circuit and the number of effective cycles is prepared in advance Thus, a current value is obtained (708).

  Next, a case where the memory unit 8 is measured, that is, a case where “no” is determined in the determination in step 707 will be described.

  The memory toggle holding register 42 and the measurement cycle number holding register 45 are initialized (710). To start measurement, the strobe signal strb is asserted (711). A signal obtained by coefficient weighting the clock enable signal cen of the memory is used as current value calculation information (712). Here, the reason why the chip enable signal is used for calculating the current value of the memory will be described.

  For example, it is assumed that the SRAM 23 is configured as shown in FIG. That is, the SRAM 23 includes an SRAM control unit (CTL) 70, an SRAM clock signal control unit (CCTL) 71 that performs clock signal control, an input / output buffer (IOBUF) 72 for data and addresses, a row decoder (RDEC) 73 for addresses, a word A driver (WD) 74, a column decoder (CDEC) 75, a column driver (CD) 76, a memory array (MARY) 77, and a sense amplifier (SA) 78 are included. The memory clock enable signal cen is high active (positive logic), and supplies a clock signal to the SRAM control unit 70 and the input / output buffer 72. The SRAM control unit 70 controls the word driver 74, the column driver 76, and the sense amplifier 78. When the clock enable signal cen is deactivated, the SRAM control unit 70, the input / output buffer 72, the word driver 74, the column driver 76, and the sense amplifier 78 are stopped, so that almost no current is consumed. Therefore, whether or not current is consumed in the SRAM 23 can be determined based on the logic state of the clock enable signal cen. Since the current consumption in the memory unit 8 varies depending on the memory size and the like, weighting is performed with an appropriate coefficient.

  The number of memory measurement cycles is obtained by updating the strobe signal every cycle (713). During the measurement cycle, the clock enable signal cen is accumulated with a coefficient weighted value. The end of the measurement can be known by the negation of the strb signal (714). From the accumulation of the cen sum with coefficients and the number of effective cycles, a current value converted from the accumulation of cen sums with coefficients and the number of effective cycles is prepared in advance to obtain the current value of the memory (715). Then, it is determined whether or not to end the measurement (709). In this determination, if it is determined that the measurement is not yet finished, the process returns to step 701.

  According to the above example, the single logic power information detection unit 30 captures the output signals of the plurality of EOR gates 32, thereby enabling power detection based on the number of toggles of the output logic in the flip-flop circuit 22. Therefore, the circuit scale of the toggle measurement circuit on the FPGA can be reduced. Moreover, since the EOR gate 32 can capture the number of toggles of the output logic in the flip-flop circuit 22 with high accuracy, it is possible to suppress a decrease in current accuracy.

  Although the invention made by the present inventor has been specifically described above, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.

  In the above description, the case where the invention made by the present inventor is applied to the SoC, which is the field of use behind the invention, has been described. However, the present invention is not limited to this and is widely applied to various semiconductor integrated circuits. can do.

1 is a block diagram illustrating a configuration example of a semiconductor integrated circuit according to the present invention. It is a block diagram of a configuration example of functional blocks included in the system on chip. It is state explanatory drawing of the functional block at the time of stopping a clock signal using a clock enable signal. It is actual measurement explanatory drawing of the electric current which flows into the functional block in the said system on chip. It is a flowchart which shows the flow of the current measurement which flows into the functional block in the said system on chip. FIG. 6 is a block diagram showing another configuration example of the semiconductor integrated circuit according to the present invention. It is a flowchart which shows the flow of an electric current measurement at the time of employ | adopting the structure shown by FIG. FIG. 7 is a block diagram illustrating a configuration example of a logic power information detection unit in FIG. 6. FIG. 7 is a block diagram illustrating a configuration example of a memory power information detection unit in FIG. 6. FIG. 7 is a block diagram illustrating a configuration example of an SRAM in FIG. 6.

Explanation of symbols

1 System-on-chip (SoC)
2A, 2B, 2C, 2D function block (FB)
3 PLL
4 Control unit (CTL)
5 Bus control unit (BC)
6 Built-in self test (BIST)
6A Logic BIST unit 6B Memo BIST unit 7 Logic unit 8 Memory unit 9 Internal bus 11, 12 Power supply terminal 13, 50, 51 AND gate 20 Logic random pattern generation unit (LRPG)
21 Logic Test Output Compressor (LTOC)
22 Flip-flop circuit with scan terminal 23 SRAM
24 Address generator (ADR_GEN)
25 Data generator (DATA_GEN)
26 Control unit (MBIST_CTL)
27 Memory Output Comparator (MCMP)
30 Logic power information detection unit 31 Memory power information detection unit 32 EOR gate 40 Toggle counter 41, 52 Adder 42 Logic toggle holding register 45, 56 Measurement cycle number holding register 46, 57 Incrementer 53 Memory information register 58 Buffer 60 SoC mounting board 61 Current probe 62 Oscilloscope 62 DSP Oscilloscope display screen 70 SRAM controller (CTL)
71 SRAM clock signal controller (CCTL)
72 I / O buffer (IOBUF)
73 Row Decoder (RDEC)
74 Word driver (WD)
75 Column decoder (CDEC)
76 Column driver (CD)
77 Memory Array (MARY)
78 Sense Amplifier (SA)
29A, 29B, 29C, 29D, 34A, 34B, 34C, 34D, 34E, 34F, 80, 81, 82 combination circuit

Claims (14)

A built-in self-test circuit capable of generating a pattern signal for self-diagnosis based on the supplied clock signal; and a scan circuit capable of scanning the pattern signal generated by the built-in self-test circuit in synchronization with the clock signal; A method for measuring current in a semiconductor integrated circuit chip having a plurality of functional blocks each including
The built-in self-test circuit in the functional block that is the current measurement target and the function block that is the current measurement target, and the supply of the clock signal to other functional blocks other than the functional block that is the current measurement target among the plurality of functional blocks A current measuring method, comprising: measuring a current flowing through a power supply terminal of the semiconductor integrated circuit chip in a state where a scan circuit is operated.   The built-in self-test circuit in the functional block that is the current measurement target and the function block that is the current measurement target, and the supply of the clock signal to other functional blocks other than the functional block that is the current measurement target among the plurality of functional blocks A current that flows to the power supply terminal of the semiconductor integrated circuit chip in a state where the scan circuit is operated, and a current that flows to the power supply terminal of the semiconductor integrated circuit chip in a state where supply of the clock signal is stopped for all of the plurality of functional blocks. The current measuring method according to claim 1, wherein an actual operating current for each functional block is obtained by obtaining a difference from the current.   The current measurement method according to claim 1, wherein the current measurement is performed in a state where the semiconductor integrated circuit chip is mounted on a mounting board. Multiple functional blocks;
A control circuit capable of selectively supplying a clock signal to a functional block that is a current measurement target among the plurality of functional blocks,
The functional block includes a built-in self-test circuit capable of generating a pattern signal for self-diagnosis based on the clock signal supplied by the control of the control circuit;
And a scan circuit capable of scanning a pattern signal generated by the built-in self-test circuit in synchronization with the clock signal supplied by the control of the control circuit.   5. The semiconductor integrated circuit according to claim 4, wherein the functional block includes a logic gate capable of controlling the supply of the clock signal to the built-in self test circuit and the scan circuit in accordance with an enable signal supplied from the control circuit. . The functional block further includes a randomly accessible memory unit,
The built-in self-test circuit includes a first built-in self-test circuit capable of generating a pattern signal supplied to the scan circuit for self-diagnosis,
6. The semiconductor integrated circuit according to claim 5, further comprising a second built-in self-test circuit capable of generating a pattern signal written to the memory for self-diagnosis. The functional block includes a plurality of flip-flop circuits capable of scanning in and scanning out a pattern signal generated by the built-in self-test circuit in synchronization with the clock signal;
A logic power information detection unit capable of detecting the power of the logic unit including the flip-flop circuit based on the number of toggles of the output logic in the flip-flop circuit;
The semiconductor integrated circuit according to claim 6, further comprising a memory power information detection unit capable of detecting the power of the memory unit. The functional block includes a gate circuit that obtains an exclusive OR of data input to the flip-flop circuit and data output from the flip-flop circuit,
The logic power information detection unit accumulates the number of toggles of the flip-flop circuit by counting the output of the gate circuit during a measurement cycle, and detects the power of the logic unit based on the accumulation result. Item 8. A semiconductor integrated circuit according to Item 7.   8. The semiconductor integrated circuit according to claim 7, wherein the memory power information detection unit uses a signal obtained by weighting an enable signal capable of selecting the memory unit with a predetermined coefficient as information for calculating a current value of the memory. A semiconductor integrated circuit having a plurality of functional blocks,
The functional block includes a logic unit including a combinational circuit and a flip-flop,
A randomly accessible memory section;
A logic power information detection unit capable of detecting the power of the logic unit including the flip-flop circuit based on the number of toggles of the output logic in the flip-flop circuit;
And a memory power information detecting unit capable of detecting the power of the memory unit. The functional block includes a gate circuit that obtains an exclusive OR of data input to the flip-flop circuit and data output from the flip-flop circuit,
The logic power information detection unit accumulates the number of toggles of the flip-flop circuit by counting the output of the gate circuit during a measurement cycle, and detects the power of the logic unit based on the accumulation result. Item 11. A semiconductor integrated circuit according to Item 10.   11. The semiconductor integrated circuit according to claim 10, wherein the memory power information detection unit uses a signal obtained by weighting an enable signal capable of selecting the memory unit with a predetermined coefficient as information for calculating a current value of the memory. The functional block includes a built-in self-test circuit capable of generating a pattern for self-diagnosis based on a supplied clock signal,
The logic unit is diagnosed by scanning in and out the pattern generated by the built-in self-test circuit in synchronization with the clock signal by the flip-flop,
The semiconductor integrated circuit according to claim 10, wherein the memory unit is diagnosed using a pattern generated by the built-in self-test circuit.   The semiconductor integrated circuit according to claim 10, formed by FPGA.

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