JP3442226B2 - Integrated circuit with delay evaluation circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit capable of evaluating a delay time of an internal circuit such as a high speed semiconductor integrated circuit device in a wafer test stage.

[0002]

2. Description of the Related Art As the speed of computers has increased in recent years, the speed of LSIs used therein has increased significantly. However, as the LSI speed increases, the LS is
There is a problem that the signal propagation delay time (delay time) inside I cannot be evaluated accurately.

This delay time is the time from when input data is given to the internal combinational circuit or the like until output data corresponding to it is output, and normally, it is a latch circuit in which the input data is latched in the input section. It is performed by giving a clock to input data to the combinational circuit and determining whether or not the output data has changed to the expected data at the next clock. By changing the speed of this clock, the delay time until the output data comes out can be detected. Moreover, the delay time for all paths can be detected from the combination of input and output.

In addition, a plurality of LSI chips are mounted on one module due to the demand for multi-chip, and accurate delay time evaluation must be performed at the wafer stage before mounting on a module. It is impossible to solve the problem of defects due to problems such as compatibility with other chips.

[0005]

However, in order to perform the delay time evaluation test at the wafer stage, it is necessary to supply a high-speed clock from the outside through a contact means such as a probe, which is technically not possible. Very difficult.

First of all, the accuracy of the external tester is not so high, and it is not possible to generate a high-speed clock with high accuracy corresponding to the short delay time inside the LSI. For example, if the clock frequency inside the LSI is 200 MHz, the clock cycle is as short as 5 nsec, and the current external tester can generate the clock with an accuracy of at most ± 0.5 nsec. Therefore, it is not suitable for evaluating the delay time.

Secondly, with the increase in the number of pins of LSI, it is difficult to use a probe which can accurately contact a large number of small input / output pads and has a good high frequency characteristic.

Therefore, as a conventional example, it has been proposed that a closed loop is formed inside the LSI by giving a control signal, and the speed of output data that changes due to the closed loop is detected (for example, JPA
57-197478). However, with such a method, the paths in the circuit for measuring the delay time are fixed, and the delay time cannot be evaluated for all the paths. Furthermore,
It is not always easy to form a closed loop in a complicated logic circuit, and it is necessary to perform a closed loop operation every time one path is measured, which increases the measurement time.

SUMMARY OF THE INVENTION An object of the present invention is to provide an integrated circuit which solves the above problems and can perform a highly accurate delay time evaluation test at the wafer stage.

A further object of the present invention is to provide an integrated circuit capable of performing a highly accurate delay time evaluation test without requiring a clock from an external tester at the wafer stage.

A further object of the present invention is to provide an integrated circuit capable of performing a highly accurate delay time evaluation test without requiring a clock from an external tester.

[0012]

According to the present invention, there is provided a delay evaluation circuit for evaluating a delay time from input of input data to an internal circuit under test to generation of output data thereof. In the integrated circuit additionally provided, the delay evaluation circuit includes a time setting circuit having an oscillation circuit, a variable frequency dividing circuit for variable frequency dividing the output of the oscillation circuit, and means for externally setting the frequency dividing number, A latch circuit which is arranged at the input stage and the output stage of the circuit under test and latches at the timing of the internal clock from the variable frequency dividing circuit of the time setting circuit; and means for outputting the latch data of the latch circuit. Is achieved by providing an integrated circuit.

Further, the integrated circuit of the present invention has a plurality of the circuits under test, the latch circuits are arranged at the input stage and the output stage of each circuit under test, and the internal clock is supplied to the latch circuits. Is performed in accordance with an address signal from the outside, and the latch data of the latch circuit is output in accordance with the address signal from the outside.

With such a configuration, the integrated circuit can generate an internal clock having an accurate and desired cycle by itself, so that the internal high-speed measured object is not supplied with the high-speed clock from the external tester. The delay time of the circuit can be measured. Moreover, since the internal clock can be set to an arbitrary cycle from the outside, more accurate delay time can be measured.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION An example of an embodiment of the present invention will be described below with reference to the drawings. However, such an embodiment does not limit the technical scope of the present invention.

FIG. 1 is a schematic block diagram of an integrated circuit according to an embodiment of the present invention. In the figure, 3 is an internal circuit under test such as a combinational circuit. Normally, in synchronization with the clock 31, the latch circuit 21 takes in the input data, supplies the input data to the combinational circuit 3, and the result is taken in by the latch circuit 21 on the output side. Then, the data is transferred to the next stage in synchronization with the clock applied to the latch circuit 21 on the output side.

In the example of FIG. 1, as a circuit for evaluating the delay time, the latch circuit 21 is first modified so that the data can be read from the scan circuit 23 during the evaluation test. Then, the address setting circuit 22 that generates the address set by the setting input pin 14
By this, an address is given to each latch circuit 21 and the like, and the data of the selected latch circuit is transferred to the scan circuit 23.
Will be output. Up to this point, it has been realized by a normal integrated circuit.

In the example of FIG. 1, a time setting circuit 1 for generating a high-speed internal clock 16 during the evaluation test is provided. In the time setting circuit 1, the ring oscillator circuit 11,
A variable frequency divider 12 and a frequency division number setting unit 15 are provided. By having this time setting circuit 1 inside itself, it is not necessary to give a high-speed clock for evaluation from an external tester.

Moreover, the time setting circuit 1 can generate a clock signal with extremely high accuracy. That is, the output of the ring oscillation circuit 11 is the scan circuit 23 for the evaluation test.
Is connected to an external oscillation cycle monitor output pin 13 via the, and the oscillation cycle is monitored by an external measuring instrument. Usually, the characteristics such as transistors and resistors inside the LSI are varied due to the manufacturing process of the LSI and the oscillation cycle of the ring oscillation circuit is also varied. Therefore, the frequency division number of the variable frequency divider 12 is adjusted from the setting input pin 14 via the frequency division number setting unit 15 based on the oscillation period detected by external monitoring. As a result, it becomes possible to generate the internal clock 16 with a cycle suitable for delay time evaluation with high accuracy. Moreover, it is possible to generate the clock 16 having an arbitrary oscillation cycle for delay time evaluation.

In this manner, the input data is latched at the delay evaluation latch circuit 21 at the rising edge of the clock 16 and input to the circuit under test 3 by the internal clock 16 having an accurate cycle, as described above. Next clock 16
The data in the latch circuit 21 on the output side at the time of rising is read from the scan circuit 23, and the external tester checks whether or not the expected output data is detected. Then, by changing the setting of the frequency division number in the time measuring circuit and changing the cycle of the internal clock 16, it is possible to know the exact delay time of the circuit under measurement. Further, by paying attention to the specific input terminal and the specific output terminal, the delay time of the specific path can be measured.

FIG. 2 is a detailed block diagram of the delay evaluation latch circuit 21. The latch circuit 211 has a function for a scan circuit so that its output can be supplied to the scan circuit 23 at the time of a test, in addition to a latch function used during a normal operation. Therefore, the clock signal is also supplied with the external clock 31 during the normal operation and with the internal clock 16 during the delay evaluation test. The clocks are switched by the switch 212. Moreover,
The switch circuit 212 is switched by the output of the decoder 214 which decodes the address signal from the address setting circuit 22. Further, the set / reset signal S / R is applied to the latch circuit 211.

FIG. 3 is a circuit diagram of another example of the embodiment of the present invention. In this example, the time setting circuit 1 is adjusted from the setting input pin 14 so that an accurate internal clock signal 16 can be generated, which is the same as FIG. This example is different in that there are a plurality of evaluated circuits 3A and 3B, and each evaluated circuit 3A and 3B can individually perform delay evaluation. Therefore, the delay evaluation latch circuit 21 is provided on the input side and the output side of the circuit under test 3A and the input side and the output side of the circuit under test 3B, and supplies the input data and detects the output data at the timing of the internal clock 16. Is done. Latch circuit 21 selected by address
Only, the internal clock 16 can be applied, and the delay time of each circuit under test can be measured individually. The scan circuit 23 is configured to scan the outputs of all the latch circuits.

Furthermore, the high-speed internal clock 16 can be applied only to the latch circuit 21 selected by the address, and the internal clock 16 of a desired speed can be applied to each circuit under test. It should be noted that the accuracy of the internal clock 16 can be kept high by externally monitoring the oscillation cycle of the ring oscillation circuit during the evaluation.

FIG. 4 shows a delay evaluation latch circuit 21.
2 is a circuit layout diagram in which is fixedly arranged in the LSI chip 100. FIG. A delay evaluation latch circuit group 21 is fixedly formed in a region between the circuits under test 3 arranged separately in four blocks and in the peripheral portion of the chip 100. An I / O circuit 5 is also provided on the peripheral portion of the chip 100.

By thus fixedly forming, in order to reduce the power consumption after the evaluation test is completed, the power supply to the dedicated power supply line of the latch circuit group 21 is turned off. Will be possible.

FIG. 5 further shows a latch circuit 2 for delay evaluation.
2 is a circuit layout diagram in which 1 is arranged only in the peripheral portion of the LSI chip 100. FIG. In this example, since the latch circuit 21 for delay evaluation is provided only in the peripheral portion, the circuit under test 3 can be arranged relatively freely in the chip.

[0027]

As described above, according to the present invention, the high-speed clock signal for the delay time evaluation test can be generated by the internal ring oscillation circuit, and the oscillation period can be adjusted. The delay time evaluation test can be performed without applying a high-speed clock from an external tester or the like. Therefore, a highly accurate delay evaluation test at the wafer stage becomes possible, and the yield of the multi-chip module can be increased.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of an integrated circuit according to an embodiment of the present invention.

FIG. 2 is a detailed block diagram of a delay evaluation latch circuit 21.

FIG. 3 is a circuit diagram of another example of the embodiment of the present invention.

FIG. 4 is a circuit layout diagram in which a delay evaluation latch circuit 21 is fixedly arranged in an LSI chip 100.

FIG. 5 is a circuit layout diagram in which a delay evaluation latch circuit 21 is arranged only on a peripheral portion of the LSI chip 100.

[Explanation of symbols]

1 hour setting circuit 3 circuit under test 11 oscillator circuit 12 Variable frequency divider 13 Divider setting section 14 Setting input pin 16 Internal clock 21 Latch circuit 22 Address setting circuit 23 Scan circuit

Continuation of the front page (56) Reference JP-A-6-43220 (JP, A) JP-A-6-148293 (JP, A) JP-A-4-274100 (JP, A) JP-A-4-204274 (JP , A) JP 64-43773 (JP, A) Patent 2515704 (JP, B2) (58) Fields investigated (Int.Cl. ⁷ , DB name) G01R 31/28-31/3193 H01L 27/04

Claims (2)

(57) [Claims] 1. An integrated circuit provided with a delay evaluation circuit for evaluating a delay time from application of input data to an internal circuit under test to generation of output data thereof, wherein the delay evaluation circuit is a ring oscillator. Circuit, a variable frequency dividing circuit for variably dividing the output of the ring oscillation circuit, a time setting circuit having means for externally setting the frequency dividing number, and an input stage and an output stage of the circuit under test, respectively. Placed,
The internal clock from the variable frequency divider of the time setting circuit
An integrated circuit comprising: a latch circuit that is supplied to each of the latch circuits and that latches at the timing of the supplied internal clock ; and a unit that outputs latch data of the latch circuit. 2. The integrated circuit according to claim 1, further comprising a plurality of said circuits under test, said latch circuits being arranged at an input stage and an output stage of each circuit under test, and said internal clock to said latch circuit. Is supplied in accordance with an address signal from the outside, and further, latch data of the latch circuit is output in accordance with an address signal from the outside.