JP4407110B2 - Semiconductor integrated circuit and power supply voltage drop measuring method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit having means for measuring a power supply voltage drop at a predetermined position in an integrated circuit, and a power supply voltage drop measurement method.
[0002]
[Prior art]
In recent semiconductor integrated circuits with a reduced power supply voltage, it is important to predict the amount of power supply voltage drop during operation in order to ensure reliable circuit operation.
Conventionally, the amount of power supply voltage drop in a semiconductor integrated circuit has been obtained by simulation using various CAD (Computer Aided Design). Once the expected power supply voltage drop is obtained, this is reflected in the design of the semiconductor integrated circuit, and the wiring is designed so that the power supply voltage drop is suppressed at critical points, or it can operate reliably even at the low power supply voltage. In this way, the characteristics of the integrated circuit were determined.
[0003]
[Problems to be solved by the invention]
The amount of power supply voltage drop described above is a simulation value, and is only a guideline when an integrated circuit is ideally formed under an assumed process. Therefore, in recent semiconductor integrated circuits (hereinafter referred to as LSI) having a large scale and a low power supply voltage, it is necessary to actually measure the amount of power supply voltage drop and feed it back to the design.
[0004]
The following two methods are conceivable as a method for measuring the amount of drop in the power supply voltage at a necessary location for an actually formed semiconductor integrated circuit.
[0005]
First, a pad for setting a probe for measurement is prepared in advance in a location in the LSI chip where the amount of power supply voltage drop is to be checked. A method for examining how much the power supply voltage supplied at a location in the wafer is reduced can be considered.
Second, a voltage measurement comparator to which a comparison reference voltage is applied from the outside is prepared in advance at the time of design, and after the LSI is assembled in a wafer state or in a package, the voltage measurement comparator is prepared. A method for examining how much the supplied power supply voltage is reduced can also be considered.
[0006]
However, the method for forming the first measurement pad in advance requires a measurement pad. In the formation of this measurement pad, it is necessary to secure an extra free space near a predetermined functional circuit block for obtaining the amount of power supply voltage drop in order to eliminate the influence of the voltage drop of the wiring when measuring a minute voltage difference. . In particular, since the pad for setting up the probe occupies a considerably large area, a useless region that is not actually used as a semiconductor circuit is formed in an LSI logic circuit or the like. In addition, the contact resistance of the probe is large, and it is difficult to accurately measure a minute voltage drop. Further, in the wafer state test, individual function tests are mainly examined individually, and in many cases, the test is not performed in the same state as when the LSI is used. In this case, the amount of power supply voltage drop during actual use cannot be measured.
[0007]
Further, in the method using the second voltage measurement comparator cell, since this cell is composed of an analog circuit, in the digital LSI, the process of the analog circuit is added only for this purpose in terms of process cost. It is not realistic. In addition, in an analog circuit, the transistor size for increasing accuracy increases, the cell area increases, and a large area penalty is incurred. Furthermore, since it is a judgment whether it is larger than the given reference voltage, it is necessary to change the reference voltage and measure it many times, and the measurement time becomes longer.
[0008]
These methods are not practical for the reasons described above, and there is a need for a technique for accurately measuring a small amount of power supply voltage drop by a simple method without increasing the area of the LSI.
[0009]
The present invention has been made in response to such a request, and the object of the present invention is to accurately measure a small amount of power supply voltage drop by a simple method without increasing the area of the semiconductor integrated circuit. There is to do.
[0010]
[Means for Solving the Problems]
  The semiconductor integrated circuit according to the present invention is for achieving the above object,As a circuit for measuring the amount of power supply voltage drop in which the oscillation frequency of the output signal changes due to the power supply voltage drop during operation at a predetermined position in the integrated circuit, it is distributed in a predetermined position in the integrated circuit and is an odd number A plurality of logic gate circuits including a plurality of inversion logic gate circuits are connected in a ring shape, and a plurality of logic gate circuits each having a unique oscillation frequency and a control input for controlling start and stop of oscillationAn oscillation circuit, and an output unit for measuring a power supply voltage drop amount for outputting an output of the oscillation circuit or a signal corresponding to the output to the outside;A decoder connected to the control input of the plurality of oscillation circuits, and selecting and oscillating a specific oscillation circuit from the plurality of oscillation circuits in accordance with an input selection signal.
[0012]
  The method for measuring the amount of power supply voltage drop according to the present invention is for achieving the above-described object, and the power supply voltage in which the oscillation frequency of the output signal changes due to the power supply voltage drop during operation at a predetermined position in the integrated circuit. A circuit for measuring the amount of drop is distributed at predetermined positions in the integrated circuit, and a plurality of logic gate circuits including an odd number of inverted logic gate circuits are connected in a ring shape, and each is formed. In a semiconductor integrated circuit having a plurality of oscillation circuits each having a specific oscillation frequency and capable of selecting the plurality of oscillation circuits, the plurality of oscillation circuits are different from the plurality of oscillation circuits and the circuit for selection. AboveSemiconductor integrated circuitSelect the oscillation circuit to operate, change the power supply voltage value to which the selected oscillation circuit is applied, oscillate, determine the relationship between the oscillation frequency and the power supply voltage value, and select the above The above-mentioned process in which the above relationship is obtained in all the oscillation circuits by changing the above and the predetermined power supply voltage value is appliedSemiconductor integrated circuitA step of measuring a plurality of oscillation frequencies of the plurality of oscillation circuits in the operating state, and a drop amount of the power supply voltage at the oscillation frequency in the operating state based on the relationship between the oscillation frequency and the power supply voltage value obtained in the non-operating state. The plurality of oscillation circuits while switching the selection targetOscillation circuitAnd a step for obtaining each.
[0013]
According to the semiconductor integrated circuit of the present invention, the oscillation circuit is provided in advance at a position where the amount of drop in the power supply voltage is desired. A ring oscillator suitable as an oscillation circuit has a configuration in which a plurality of logic gate circuits including an odd number of inverted logic gate circuits (inverters) are connected in a ring shape, and is formed by a so-called digital integrated circuit process. The semiconductor integrated circuit also has an output unit for measuring the amount of power supply voltage drop that causes the output of the oscillation circuit or a signal corresponding to the output to be output to the outside.
[0014]
According to the power supply voltage drop measuring method of the present invention, the oscillation circuit is oscillated while changing the power supply voltage in a non-operating state in which other circuit portions around the oscillation circuit are not operated, and the oscillation frequency and the power supply voltage are Measure the relationship. Thereafter, the semiconductor circuit is operated with a predetermined power supply voltage applied, and the oscillation frequency of the oscillation circuit is measured in this operating state. In the operating state, the power supply voltage drop occurs because the circuits around the oscillation circuit are operating dynamically, resulting in a deviation from the relationship between the oscillation frequency and the power supply voltage obtained in the non-operating state. That is, normally, when transitioning from the non-operating state to the operating state, the oscillation frequency decreases, and the power supply voltage value actually applied to the circuit differs. The power supply voltage difference between the operating state and the non-operating state at the predetermined oscillation frequency is the amount of power supply voltage drop during operation to be obtained.
In this measurement, the frequency or cycle of the output signal of the oscillation circuit output from the output unit for measuring the power supply voltage drop is measured. Even if the output unit is separated from the oscillation circuit and a signal delay occurs, the frequency and period can be measured accurately.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings, taking as an example the case of using a ring oscillator (hereinafter referred to as a ROSC circuit) as an oscillation circuit.
[0016]
FIG. 1 is a conceptual diagram of a semiconductor integrated circuit according to an embodiment of the present invention in which five ROSC circuits are distributed and arranged.
A semiconductor integrated circuit (hereinafter referred to as LSI) 1 illustrated in FIG. 1 is a digital IC, and is roughly composed of an internal logic circuit portion 2 and an input / output circuit portion 3 around it.
Although not particularly shown, the input / output circuit unit 3 is provided with I / O pads to which various I / O pins are connected, input / output circuits (buffers, etc.), power supply circuits, and the like.
Although not specifically shown, the internal logic circuit unit 2 is provided with necessary functional blocks including a CPU and the like according to the type of the LSI, and a memory unit such as a ROM and a RAM as necessary. Yes.
[0017]
In the LSI of the present embodiment, a plurality of oscillation circuits, for example, a plurality of ROSC circuits, are provided in the internal logic circuit unit 2.
The number of the oscillation circuits, the arrangement location, and the oscillation frequency are arbitrary. An oscillation circuit that oscillates at a specific frequency can be arranged near the block for which the amount of power supply voltage drop is to be measured. In addition, when it is simply desired to examine the distribution of the power supply voltage drop in the LSI, a plurality of oscillation circuits that oscillate at a predetermined frequency can be equally arranged in the internal logic circuit section 2.
[0018]
In the example illustrated in FIG. 1, five ROSC circuits 4A, 4B, 4C, 4D, and 4E are provided. For example, the ROSC circuit 4C is arranged near the center of the internal logic circuit unit 2, and the other four ROSC circuits 4A, 4B, 4D, and 4E are arranged near the four corners of the internal logic circuit unit 2. .
Also, a decoder 5 for operating any one of the five ROSC circuits at an arbitrary position in the internal logic circuit unit 2 and a selector for selecting and outputting an output signal of the operating ROSC circuit to the outside 6 are provided. When the decoder 5 operates any one of the five ROSC circuits as in this example, the selector 6 can be omitted. The decoder 5 may operate a plurality of ROSC circuits simultaneously. In this case, the selector 6 is essential. Hereinafter, a case where any one of the ROSC circuits is operated by the decoder 5 and the output is selected by the selector 6 will be described as an example.
[0019]
The output of the decoder 5 is connected to the inputs of the five ROSC circuits 4A to 4E, and the outputs of the ROSC circuits 4A to 4E are connected to the input of the selector 6. A selection signal S1 for selecting any one of the ROSC circuits and outputting the oscillated output signal (hereinafter also referred to as oscillation output) S0 to the outside is input to the input of the decoder 5 and the control input of the selector 6. .
The decoder 5 selects one of the ROSC circuits 4A to 4E based on the control signal S1, and oscillates at a predetermined frequency. The selector 6 permits output of the output signal S0 of the selected ROSC circuit (oscillation circuit) or the signal S0 according to the output signal to the outside based on the control signal S1. Here, the “signal according to the output signal of the oscillation circuit” means, as will be described later, a signal obtained by reducing the frequency of the output signal of the oscillation circuit by a predetermined frequency division ratio or a certain period of the output signal of the oscillation circuit. The output signal of the counter when counting the number of pulses.
[0020]
FIG. 2 is a diagram showing the arrangement position of the ROSC circuit in more detail. 3 and 4 are explanatory diagrams of an LSI composed of a general standard cell array.
Usually, the standard cell has a pair of wirings 10d and 11d called “bench” for supplying a power supply voltage Vdd and a reference voltage Vss. In a state where the standard cells are arranged in the LSI, the benches 10d and 11d are formed as parallel wirings that are long in the horizontal direction in the entire array, for example, as shown in FIG.
Further, a basic power supply voltage supply line 10b for supplying the power supply voltage Vdd and a basic reference voltage supply line 11b for supplying the reference voltage Vss are formed around the internal logic circuit section 2 of the LSI. The main power supply voltage supply line 10b is connected to each bench 10d and the power supply voltage supply pad 10a for supplying the power supply voltage Vdd, and the basic reference voltage supply line 11b is connected to each bench 11d and the reference voltage supply pad 11a for supplying the reference voltage Vss. Has been. These voltage supply lines (hereinafter referred to as trunk lines) 10b and 11b are thick wirings having sufficiently low wiring resistance to prevent voltage drop.
In particular, a large-scale LSI has a reinforcing line for preventing a voltage drop at a position far from the main lines 10b and 11b around the internal logic circuit section 2 as shown in FIG. In the example shown in FIG. 4, the power supply voltage reinforcing line 10c that connects the main power supply voltage supply line 10b in the horizontal or vertical direction and the reference voltage that connects the main reference voltage supply line 11b in the horizontal or vertical direction as the reinforcing lines. And a reinforcing wire 11c. These reinforcing wires 10c and 11c may be arranged only in the direction intersecting with the wiring direction of the bench, that is, in the vertical direction. The reinforcing wires 10c and 11c are usually thinner than the main wires 10b and 11b, but are sufficiently thicker than the benches 10d and 11d to reduce the wiring resistance. Note that the bench is not shown in FIG.
[0021]
The five ROSC circuits 4A to 4E are desirably arranged near the main power supply voltage supply line 10b and the main reference voltage supply line 11b as illustrated in FIG. Alternatively, the ROSC circuit is arranged near the reinforcing wires 10c and 11c as in the central ROSC circuit 4C shown in the drawing. This is a desirable requirement in view of the purpose of minimizing the voltage drop due to the wiring included in the power supply voltage drop. This is not the case when the circuit scale is small or the resistance of the wiring in the cell called a bench is sufficiently small and the voltage drop due to the wiring hardly affects the measurement accuracy. Further, the arrangement of the oscillation circuit is not limited to the position shown in FIG. 2 as long as it is close to the main lines 10b and 11b or the reinforcing lines 10c and 11c.
[0022]
The ROSC circuits 4A to 4E that oscillate at a desired frequency have at least an odd number of inverted logic circuits. As the ROSC circuits 4A to 4E, for example, circuits in which an odd number of inverted logic circuits and an arbitrary number of positive logic circuits are logically connected in a circular manner are used. This logically connected circuit oscillates when a voltage is applied to each logic circuit, and is measured within a semiconductor circuit by increasing or decreasing the number of stages (or number of elements, signal delay value) of each circuit. An oscillation signal in which a pulse is repeated at a predetermined frequency at a desired location is generated.
[0023]
FIG. 5 is a circuit diagram showing an embodiment of the basic configuration of the ROSC circuits 4A to 4E.
The ROSC circuits 4A to 4E in the illustrated example include odd-numbered n-stage inverters 41-1, 41-2,..., 41- (n−1), 41-n, one NAND gate circuit 42, And an enable circuit 43. The inverter and the NAND gate circuit are supplied with the power supply voltage Vdd from the main power supply voltage supply line or the reinforcement lines 10b and 10c, and supplied with the reference voltage Vss from the main reference voltage supply line or the reinforcement lines 11b and 11c.
The output of the enable circuit 43 is connected to one input of the NAND gate circuit 42. The enable circuit 43 receives the signal S2 from the decoder 5 obtained by decoding the selection signal S1, and according to the signal S2, an enable signal having an “H (high)” level when selected and an “L (low)” level when not selected. S3 is output to one input of the NAND gate circuit.
[0024]
FIG. 6 is a chart showing an example of correspondence between signals and ROSC circuits selected by the decoder according to the signals S1 and S2.
When the selection signal S1 is 3 bits, there are 8 combinations of bits as shown in FIG. Among these, when the selection signal S1 is “001”, the decoder 5 selects the ROSC circuit 4A, when it is “010”, the ROSC circuit 4B is selected, when it is “011”, the ROSC circuit 4C is selected, and when it is “100”. The ROSC circuit 4D is selected. When “101”, the ROSC circuit 4E is selected. The signal S2 output from the decoder 5 is a 5-bit signal, and when the LSB (least significant bit) is set to “1”, the ROSC circuit 4A is selected. Similarly, when “1” is set in the next bit of the LSB, the ROSC circuit 4B is selected, and thereafter, the ROSC circuits 4C, 4D, and 4E are similarly selected. The enable circuit 43 in FIG. 5 controls the start and stop of oscillation by setting the output signal S3 to “H” only when “1” is set in the corresponding bit of the signal S2, and otherwise setting it to “L”. To do.
[0025]
FIG. 7 is a table showing a correspondence example between the ROSC circuit whose output is permitted by the decoder according to the signal S1 and its output.
As shown in FIG. 7, when the selection signal S1 is “001”, the selector 6 permits the output of the oscillation output SOA of the ROSC circuit 4A, and the output unit of the present invention (for example, an I / O for measuring the amount of power supply voltage drop). Output from the pad). Similarly, when the selection signal S1 is “010”, the output of the oscillation output SOB of the ROSC circuit 4B is permitted, and when the selection signal S1 is “011”, the output of the oscillation output SOC of the ROSC circuit 4C is permitted. The output of the oscillation output SOD of the ROSC circuit 4D is permitted when the signal is “100”, and the output of the oscillation output SOE of the ROSC circuit 4E is permitted when the selection signal S1 is “101”. Become.
[0026]
6 and 7, when the selection signal S1 is “000”, “110”, or “111” other than the above, the decoder 5 does not select any ROSC circuit, and the selector 6 does not permit the output. . In the normal use mode of the LSI, the selection signal S1 is set to “000”, “110”, or “111”. On the other hand, in the test mode for measuring the amount of power supply voltage drop, any of the other five combinations of bits is set.
[0027]
Next, a test method for measuring the power supply voltage drop will be described.
First, the non-operating state of the test mode is selected. Here, the non-operating state refers to a mode in which the peripheral circuits other than the five ROSC circuits 4A to 4E, the decoder 5 and the selector 6 illustrated in FIG. In the non-operating state, the static characteristics (dependence of oscillation frequency on power supply voltage) of each of the ROSC circuits 4A to 4E are measured.
[0028]
8 and 9 show examples of static characteristics. In the present invention, the oscillation frequency is assumed to include the period of the oscillation signal equivalently.
FIG. 8 is a graph showing the dependency of the period T [ns] of the oscillation signal on the power supply voltage Vdd [V]. FIG. 9 is a graph in which the vertical axis of FIG. 8 is converted into the oscillation frequency f [MHz].
When the power supply voltage Vdd supplied to the ROSC circuits 4A to 4E is increased, the oscillation frequency f of the output signal of the ROSC circuits 4A to 4E increases, and accordingly, the pulse period T of the output signal is shortened. Each of the ROSC circuits 4A to 4E desirably has the number of inverter stages and the entire delay amount set so as to oscillate at the oscillation frequency of the closest functional block when a predetermined power supply voltage is applied. Therefore, in this case, the static characteristics shown in FIG. 8 or FIG. 9 are measured while changing the applied power supply voltage Vdd for each of the ROSC circuits 4A to 4E. At this time, it is desirable to apply the power supply voltage Vdd so that the oscillation frequency changes at positive and negative required points around each predetermined oscillation frequency. The measurement result is stored as a table or a characteristic equation in a storage unit in the LSI, for example, a RAM. Note that the measurement results may be output to the outside each time or collectively.
[0029]
Next, in the test mode, the LSI is operated from a non-operating state under an operating state in which all necessary circuits are normally operated, that is, under conditions such as a normally used power supply voltage and temperature (for example, room temperature). Here, “all necessary circuits” are all circuits whose normal use operation affects the drop in power supply voltage during the operation of a particular ROSC circuit of interest, and are almost independent of the drop in power supply voltage. It is okay to stop the circuit function that seems to be.
In such an operating state, the oscillation frequency f (or the period T of the oscillation pulse) of each of the five ROSC circuits 4A to 4E is measured.
[0030]
In particular, the power supply voltage is lowered by the dynamic operation of the circuit portion connected to the main line of the same power supply voltage, and the ROSC circuit also oscillates at this reduced power supply voltage. Therefore, there is a shift in the operating point on the graph showing the correspondence relationship between the oscillation frequency f and the power supply voltage Vdd investigated by the static characteristics. In each ROSC circuit, the unique oscillation frequency is f0, and the voltage applied to the power supply voltage supply pad 10a (FIG. 2) is Vdd0. At this time, the oscillation frequency f (or period T) of the output signal SO of the selector 5 is measured by a tester connected to the pad of the output unit.
When the tester has a function of a frequency counter, the oscillation frequency f is obtained by counting the number of pulses. If this function is not provided, a counter for counting the number of pulses may be provided at the subsequent stage of the selector 5 or at the output stage of each of the ROSC circuits 4A to 4E. Further, when the oscillation frequency is high, it is not necessary to use an expensive tester, or in order to increase the measurement accuracy, a predetermined frequency division ratio is provided at the subsequent stage of the selector 5 or the output stage of each ROSC circuit 4A to 4E. A frequency divider that reduces the frequency may be provided.
[0031]
As a result of this measurement, as shown in FIG. 9, it is assumed that the frequency ft of the test output signal SO has decreased by Δf from the inherent oscillation frequency f0. At this time, the amount of change ΔV of the power supply voltage Vdd corresponding to the frequency change Δf in the relational expression in FIG. 9 is the amount of decrease in the power supply voltage Vdd0.
If such measurement is repeated while switching between the decoder 5 and the selector 6 in accordance with the selection signal S1, the power supply voltage drop amount ΔV can be obtained in all of the five ROSC circuits 4A to 4E.
With the circuit configuration and method described above, it is possible to measure the amount of power supply voltage drop considering the actual operation in the semiconductor integrated circuit.
[0032]
Note that if a process variation or the like is taken into consideration, a method of using a transistor of a type resistant to the variation can be used.
For example, even if a circuit having the same configuration is used for each of the ROSC circuits 4A to 4E, depending on the situation of the surrounding wiring including the upper layer and lower layer wiring and the arrangement of the surrounding transistors used other than the ROSC circuit, or process variation The characteristics of the ROSC circuits 4A to 4E may be significantly different. Therefore, even in the ROSC circuit having the same configuration, the voltage dependency characteristics of the oscillation frequency may be different. When it is desired to suppress such characteristic variation as much as possible, it can be dealt with by using a transistor having a large gate length.
[0033]
According to the embodiment of the present invention, the following advantages can be obtained.
First, the amount of power supply voltage drop in actual operation can be accurately measured. That is, even when the output unit is separated from the oscillation circuit and a signal delay occurs, the frequency and period can be accurately measured, and thus the obtained power supply voltage drop is highly accurate. Accordingly, the output unit can be provided in the input / output unit provided around the integrated circuit in the same manner as a normal input / output (I / O) terminal, and a larger area is not required for a pad for standing a probe.
Secondly, an oscillation circuit having an oscillation frequency equivalent to the operation frequency of the surrounding circuits, for example, a ROSC circuit can be formed in advance in a necessary number and a necessary location. For this reason, for example, it is possible to limit the test to a functional block having a particularly high oscillation frequency or to a functional block having a high charge / discharge frequency using the power supply voltage supply line. Usually, it is often sufficient in terms of ensuring the overall safe operation if the amount of power supply voltage drop in these limited functional blocks can be monitored. This eliminates unnecessary testing.
Thirdly, since the decoder 5 and the selector 6 are provided as means for switching a plurality of oscillation circuits, the number of pads for measurement can be minimized.
Fourth, a ring oscillator using an odd-stage connected inverter and one NAND gate circuit is used as an oscillation circuit. Such a ring oscillator (ROSC circuit) can be constructed as a set of normal standard cells if only the input / output line layer is specially designed. Therefore, the design is easy and the occupied area is smaller than that of an analog circuit comparator. small. Further, it can be formed together with other circuits by a digital circuit process. Therefore, increase in chip cost including design cost and process cost is sufficiently suppressed.
From the above, by using the circuit configuration and measurement method for measuring the power supply voltage drop amount according to the present embodiment, it is possible to obtain the results of the process design or the design of the power supply wiring, particularly at the start of the semiconductor process. It is extremely easy to estimate the CAD error when obtaining from simulation. In addition, since the amount of power supply voltage drop during operation can be accurately measured, this function can be incorporated into an actual semiconductor integrated circuit (product) to increase the added value as a product with a test mode.
[0034]
【The invention's effect】
According to the semiconductor integrated circuit and the method for measuring the power supply voltage drop according to the present invention, the power supply voltage drop can be accurately measured by a simple method without increasing the area of the integrated circuit.
[Brief description of the drawings]
FIG. 1 is a diagram showing a semiconductor integrated circuit according to an embodiment of the present invention having a plurality of oscillation circuits arranged in a distributed manner.
FIG. 2 is a diagram showing in more detail an example of an arrangement position of an oscillation circuit (ROSC circuit).
FIG. 3 is a diagram showing an example of supply lines for a power supply voltage and a reference voltage of an LSI configured by a standard cell array.
FIG. 4 is a diagram showing another example of supply lines for a power supply voltage and a reference voltage of an LSI configured by a standard cell array.
FIG. 5 is a circuit diagram showing an embodiment of a basic configuration of a ROSC circuit.
FIG. 6 is a chart showing correspondence between signals S1 and S2 and a ROSC circuit selected by a decoder.
FIG. 7 is a chart showing the correspondence between ROSC circuits whose output is permitted by the decoder according to signal S1 and their outputs.
FIG. 8 is a graph showing the dependency of the period of an oscillation signal on the power supply voltage as an example of static characteristics.
FIG. 9 is a graph showing the dependency of the oscillation frequency of the output signal on the power supply voltage as an example of static characteristics.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Semiconductor integrated circuit, 2 ... Internal logic circuit part, 3 ... Peripheral circuit part, 4A-4E ... Oscillator circuit, 5 ... Decoder, 6 ... Selector, 10b ... Main line of power supply voltage supply line, 10c ... Power supply voltage supply line Reinforcement line, 11b ... trunk line of reference voltage supply line, 11c ... reinforcement line of reference voltage supply line, 41-1 etc .... inverted logic circuit, 42 ... positive logic circuit, 43 ... enable circuit.

Claims (3)

As a circuit for measuring the amount of power supply voltage drop in which the oscillation frequency of the output signal changes due to the power supply voltage drop during operation at a predetermined position in the integrated circuit, it is distributed in a predetermined position in the integrated circuit and is an odd number A plurality of logic gate circuits each including a plurality of inverting logic gate circuits connected in a ring shape, each having a unique oscillation frequency and a control input for controlling start and stop of oscillation When,
An output unit for measuring the amount of power supply voltage drop that causes the output of the oscillation circuit or a signal corresponding to the output to be output to the outside;
A decoder connected to the control inputs of the plurality of oscillation circuits, and selecting and oscillating a specific oscillation circuit from the plurality of oscillation circuits in accordance with an input selection signal;
A semiconductor integrated circuit. And a selector that selects one of the oscillation circuits according to the selection signal and outputs an output of the selected oscillation circuit or a signal corresponding to the output when there are a plurality of the specific oscillation circuits that oscillate. 2. The semiconductor integrated circuit according to 1. As a circuit for measuring the amount of power supply voltage drop in which the oscillation frequency of the output signal changes due to the power supply voltage drop during operation at a predetermined position in the integrated circuit, it is distributed in a predetermined position in the integrated circuit and is an odd number A plurality of logic gate circuits including a plurality of inverting logic gate circuits are connected in a ring shape, and each has a plurality of oscillation circuits having specific oscillation frequencies, and the plurality of oscillation circuits can be selected. In the semiconductor integrated circuit, the plurality of oscillation circuits are selected by selecting an oscillation circuit to be operated in a non-operating state in which the portions of the semiconductor integrated circuit other than the plurality of oscillation circuits and the selection circuit are not operated. The process of oscillating by changing the power supply voltage value to which the oscillation circuit is applied, obtaining the relationship between the oscillation frequency and the power supply voltage value, and changing the selection target to obtain the relationship in all the oscillation circuits ,
Measuring a plurality of oscillation frequencies of the plurality of oscillation circuits in an operating state of the semiconductor integrated circuit to which a predetermined power supply voltage value is applied;
A step of determining, for each oscillation circuit of the plurality of oscillation circuits, a drop amount of the power supply voltage at the oscillation frequency in the operation state from the relationship between the oscillation frequency obtained in the non-operation state and the power supply voltage value
Including power supply voltage drop measurement method.

Images