JP2000315767A - Semiconductor integrated circuit and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a variable logic integrated circuit (FPGA) whose inside circuit can be tested without using a high-performance external tester. SOLUTION: This semiconductor chip 100 is provided with a plurality of basic logic cells CLB and variable switch circuits CSW capable of connecting signal lines between these basic logic cells CLB thereon. A variable logic circuit FPGA which can output a signal showing a normal/abnormal state of the circuit for each basic logic circuit CLB and constitute arbitrary logic by switching the connection by the variable switching circuits CSW is mounted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit capable of forming arbitrary logic, for example, an FPGA (Field Programmable Circuit).
The present invention relates to an effective gate array) and an effective technology applied to an FPGA capable of detecting a fault and avoiding a fault location and forming a logic or a logic integrated circuit (hereinafter, referred to as a logic IC) incorporating the FPGA. is there.

[0002]

2. Description of the Related Art Conventionally, an FPGA has been provided as a logic IC that allows a user to configure an arbitrary logic. For example, as shown in FIG. 1, the FPGA includes a plurality of basic logic cells (cell logic blocks) CLB capable of arbitrarily configuring a plurality of functions that can be described by Boolean algebras, and a cell provided between each cell logic block CLB. It is composed of wiring groups 121 and 122 for connecting the wirings and a crosspoint switch CSW capable of changing the state of the wiring connection from the outside. It's being used.

When designing a logic system using an FPGA, a desired logic function is converted to an HDL (Hardware Description Lan) using a support tool or the like provided by an EDA vendor.
guage) and obtains logic circuit data (type of logic gate to be used and information on connection between terminals, etc.) using a logic synthesis tool. The logic operation control data of the basic logic cell CLB and C
The connection data between the LBs is obtained, and the wiring to be used and the ON / OFF control data of the cross point switch CSW are determined from the connection data to construct an overall logic circuit system. Such a logic design can be easily executed by a user, and its convenience has been widely recognized.

When a logic IC is developed, test pattern data is generally generated by a tester called a tester, input to the IC, and the output data signal is compared with an expected value to detect whether the IC operates normally. Tests have been conducted. However, in a logic IC, as the scale of the logic increases, the number of steps in the test pattern increases, and the time required to create the test pattern and to perform a test using the test pattern increases.

Therefore, as a method of facilitating a test by a tester, a shift register is designed so that a sequential circuit such as a flip-flop constituting an original function of an IC is cascade-connected so that a shift register can be configured. A test pattern is serially input (scan-in) to the shift register and is fetched (set), and the test data fetched into the shift register is input to a desired combinational logic circuit.
Thereafter, a test-easy design technique called a so-called scan path method, in which an output data signal of the logic circuit is taken into a shift register and shifted to be taken out (scan-out), has been developed and put into practical use.

In a method of inputting a test pattern from the outside, if a logic circuit includes a sequential circuit, the output differs depending on the internal state. Therefore, in order to test a certain logic circuit, the state of the sequential circuit included in the logic circuit must be determined. First, since the test pattern must be set, the test pattern becomes very long. However, the test pattern can be greatly reduced by inputting (scanning in) the test pattern by using a flip-flop as a shift register.

On the other hand, a BIST (Built in self test) in which a pattern generation circuit for generating a random test pattern such as a pseudo random number generation circuit is built in a logic integrated circuit.
Test techniques have also been proposed.

[0008]

SUMMARY OF THE INVENTION Regarding FPGA,
In order to guarantee the reliability, it is common to use a tester or the like to test whether or not the IC operates normally after manufacturing, and to provide only normal ICs to the market, as in the case of a normal logic IC. However, FPGAs are also increasingly required to be large in size, and the test patterns increase with the increase in scale, making it difficult to achieve a sufficient defect detection rate. Compared to a normal logic IC, there is a problem that the yield is low but the cost is high because the logic scale of the entire chip is large and the chip area is large compared to the original logic scale.

Further, an LS equipped with a conventional test circuit
In any case I, no measure is taken for its own failure or defect in the test circuit. In other words, when the test circuit itself breaks down, there is a defect that a failure determination is made even if the original circuit of the chip is normal. The only countermeasure is to suppress the occurrence of failures and defects by minimizing the scale of the test circuit, but this results in a result inconsistent with the purpose of improving the test sufficiency, that is, improving the defect detection rate. .

An object of the present invention is to provide a variable logic integrated circuit (FPGA) capable of testing an internal circuit without using a sophisticated external tester.

Another object of the present invention is to provide a variable logic integrated circuit (FPGA) with a high yield and high reliability, which can detect a faulty part and repair itself by itself.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0013]

The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, the semiconductor integrated circuit according to the present invention comprises a plurality of basic logic cells (cell logic blocks) on a chip, and can output a signal indicating whether the circuit is normal or abnormal for each of the basic logic cells, and at any given time. FP with configurable logic
A variable logic circuit such as a GA (Field Programmable Gate Array) is mounted. This allows
Variable logic circuit (FPG without using external tester)
It is possible to know that there is a defective part in A) and its position. Further, the yield can be improved by configuring the logic while avoiding the defective part.

As a basic logic cell capable of outputting a signal indicating whether the circuit is normal or abnormal, for example, a two-wire line logic (logical product gate circuit) having a complementary output is compared with its complementary output to determine whether there is an abnormality. There is a circuit composed of a determination means (exclusive OR gate) that performs the determination. With such a configuration of the basic logic cell, a variable logic circuit (FPGA) that can output a signal indicating whether the circuit is normal or abnormal and that can configure any logic can be realized with a relatively small circuit. And a test result of the internal circuit can be obtained without using a sophisticated external tester.

The basic logic cell has a plurality of input signal latch means for latching two or more input signals, respectively, and can selectively execute a plurality of logic operations by using output signals of these input signal latch means as input signals. A logic unit, output signal latching means capable of latching and outputting an output of the logic unit, and readable and writable memory means for storing control information designating a logic operation of the logic unit;
A random number generation circuit for generating a test pattern and supplying the same to the input signal latch means and the logic unit; and a determination means for comparing the signal output from the output signal latch means with an expected value to determine the presence or absence of an abnormality. And a circuit (B) configured to output an output signal of the determination means from each basic logic cell as a signal indicating whether the circuit is normal or abnormal.
IST).

As a result, in a conventional LSI having a built-in BIST, one BIST is a global BIST for inspecting all the LSI internal circuits, and the test pattern generated does not guarantee the test adequacy.
In the present invention, since the BIST is a local BIST provided for each basic logic cell, test sufficiency is guaranteed. Moreover, since the variable logic circuit of the present invention is composed of a plurality of identical basic logic cells,
The optimization of BIST can be performed uniformly, and the design burden is reduced.

The variable switch circuit comprises switch means for disconnecting and connecting signal lines crossing each other, and writable and readable storage means for storing information for controlling the state of the switch means. A signal output from the determination means indicating whether the circuit is normal or abnormal is stored in the storage means. Thus, the circuit can be provided without providing dedicated storage means for storing a signal indicating normal / abnormal of a circuit output from each basic logic cell, a large number of terminals for monitoring signals, or a selector circuit for selectively outputting them. Normal / abnormal can be known from outside,
An increase in circuit scale can be suppressed.

Further, selecting means for selecting one of the storage means in the variable switch circuit based on an external signal, and writing means for writing externally input data to the selected storage element. Is provided. This eliminates the need to provide a data input / output terminal corresponding to each storage element, thereby reducing the number of external terminals of the chip.

In the semiconductor integrated circuit according to the present invention, a self-test is first performed by an internal variable logic circuit (FPGA), and the basic logic excluding the defective part is obtained by using the information indicating the defective part obtained as a result. A desired logic can be constituted only by cells, and thereby a logic system with high yield and high reliability can be constituted.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of an FPGA to which the present invention is applied. One semiconductor chip 10 such as single-crystal silicon is manufactured by a known semiconductor integrated circuit manufacturing technique.
0.

The FPGA of this embodiment has a plurality of cell logic blocks CLB arranged in a matrix, wiring groups 121 and 122 provided between the cell logic blocks CLB for connecting cells, and an external circuit. -Point switch C that can change the state of wiring connection
SW, and a desired logic function can be configured by changing the connection state between wirings by the cross point switch CSW or designating the logic of each cell logic block CLB according to the logic to be realized. ing.

It is desirable that the wiring groups 121 and 122 be formed in a state in which they are insulated from each other by different wiring layers using a multilayer wiring technique. Although FIG. 1 shows two wirings between each cell logic block, more wirings are actually formed. The number of wirings increases in proportion to the number of cell logic blocks.

Although not particularly limited, an X-decoder circuit, a Y-decoder circuit, and a write circuit for selecting the wiring connection information storage memory cell SMC and writing data around the FPGA as described later. May be provided.

As shown in FIG. 2A, for example, the cross point switch CSW includes a switch MOSFET Qsw having a source and a drain connected to a horizontal wiring Lx and a vertical wiring Ly, and a switch MOSFET Qsw.
And a memory cell SMC for storing wiring connection information for storing control information applied to the gate of the FET Qsw.

The memory cell SMC for storing the wiring connection information
Is a flip-flop type latch circuit LT in which input and output terminals of two inverters are cross-coupled, and a latch circuit L
T internal nodes N1, N2 and data input / output nodes N3,
Transmission MOSFET TG1, T connected between N4
G2 and a lead provided correspondingly.
Data writing and reading are performed by the write control unit RWC.

The read / write control unit RWC includes a data input / output terminal DIO and the data input / output nodes N3, N
4 between the data input / output terminal DIO and the data input / output node N4, the transmission MOSFETs TG3 and TG4 being turned on and off by a write / read control signal W / R applied to the gate and connected to the data input / output terminal DIO. A transmission MOSFET TG5 for reading data connected to the transmission MOSFET and a transmission MOSFET for inverting the write / read control signal W / R.
It comprises an inverter INV1 applied to the gate of TG5, and an inverter INV2 for inverting the write data and supplying the inverted data to the transmission MOSFET TG3.

The gate terminals of the transmission MOSFETs TG1 and TG2 have an address signal ADD inputted from outside.
Is applied, and TG is generated by the address signal ADD.
1 and TG2 are turned on, the corresponding memory cell is selected. At this time, if the write / read control signal W / R is at a high level, the MOSFETs TG3 and TG4 are turned on and the data input / output terminal DIO Is supplied to the latch circuit LT and held.
On the other hand, if the write / read control signal W / R is set to the low level in a state where the TG1 and TG2 are turned on by the address signal ADD, the MOSFETs TG3 and TG4 are turned off and TG5 is turned on instead of the MOSFET TG3, TG4. Is output to the outside of the memory cell SMC via TG2 and TG5.

In the memory cell SMC for wiring connection information storage of this embodiment, the potential of the internal
Switch MOS connected between the gate and the vertical wiring Ly
The on / off state of Qsw is controlled by data applied to the gate terminal of the FET Qsw, input from the data input / output terminal DIO, and held in the latch circuit LT. Further, a signal (self-verification signal) SD from the corresponding cell logic block CLB is provided to the gate terminal of the MOSFET Q1 forming the latch circuit LT.
Is supplied, and the state of the cell logic block CLB can be stored in the memory cell SMC.

In the memory cell SMC for storing wiring connection information, a sense amplifier circuit may be provided between the data input / output nodes N3 and N4. The memory cell SMC for storing wiring connection information is provided with a switch M
Instead of being provided in a one-to-one relationship in the vicinity of the OSFET Qsw, it is also possible to collectively provide an SRAM memory array around the FPGA block.

The cell logic block CLB is, for example, shown in FIG.
As shown in (a), an AND gate circuit (two-line logic) LG1 having complementary outputs such as AND logic and NAND logic, and an exclusive OR gate circuit (comparing means) having the complementary output as an input LG2. The gate circuit LG2 outputs a low-level output signal when the two input signals have the same logical level, and outputs a high-level output signal when the two input signals have different logical levels. When the output of the gate circuit LG2 becomes a low level when the portion where the output is to be the complementary output due to the defect of the LG1 becomes low, it informs that the gate circuit LG1 is defective.

The output signal of the gate circuit LG2 may be output as it is to the outside of the FPGA block, but in this embodiment, the wiring constituting the cross point switch CSW shown in FIG. The connection information storage memory cell SMC is configured so that it can be inputted to the gate (internal node N2) of the MOSFET Q1 and stored.

Therefore, the power supply voltage is applied to each cell logic block CLB, the output state of the gate circuit LG2 at that time is stored in the wiring connection information storage memory cell SMC, and then stored in the wiring connection information storage memory cell SMC. By reading the information to the outside, it can be known whether or not the cell logic block CLB operates normally.

The memory cell S for storing each wiring connection information
By sequentially writing and reading data from the outside of the chip to the MC, it is also possible to detect whether or not the memory cell has failed. Further, the memory cell SM for wiring connection information storage
Write data to C and switch MOSFET as desired
By turning on Qsw and inputting and checking a signal from the outside using the wiring groups 121 and 122, the switch MO
Whether the SFET Qsw has failed can also be detected.

It is to be noted that the output of the gate circuit LG2 is at a low level by devising the gate structure or the memory cell circuit of the MOSFET Q1 which constitutes the wiring connection information storage memory cell SMC to which the output state of the gate circuit LG2 is inputted. Is MOS by external data input
The configuration may be such that the FET Q1 is not inverted or turned off. This makes it possible to efficiently detect whether or not the cell logic block CLB has a failure.

As a specific method of realizing such a function, the MOSFET Q1 constituting the memory cell SMC
Has a structure having a control gate CG and a floating gate FG, for example, as shown in FIG.
The self-verification output SD of the gate circuit LG2 is MOSFET
A method is conceivable in which charge is applied to the control gate CG of Q1 to inject charges into the floating gate FG so that the state of the memory cell does not change depending on external data input.

A specific circuit of a cell logic block composed of the AND gate circuit LG1 and the exclusive OR gate circuit (comparing means) LG2 shown in FIG. 3A is, for example, as shown in FIG. 3B. Circuit is conceivable.

That is, the logical product gate circuit LG1 is composed of the first MOs composed of MOSFETs M1, M2 and LM1 connected in series between the power supply voltage terminal Vcc and the ground.
A series of MOSFETs LM2 and M
3, M4, and M2
A first input signal X is applied to the gates of M3 and M3, and M2 and M4
The second input signal Y is applied to the gate of
A logical product output Z (= X · Y) of the input signals X and Y is output from the output node N11 of the first MOSFET row and the second MOS
An operation is performed such that an inverted output / Z (= / XY) of the logical product output Z of the input signals X and Y is output from the output node N12 of the FET array. The MOSFET L shown in FIG.
The gates and the drains of M1 and LM2 act as load resistances when the gates and the drains are coupled or a predetermined potential is applied to the gates.

The AND gate circuit LG1 of this embodiment is composed of
The output / Z is a delay circuit DLY and a feedback MOSFE.
The input terminals (X,
Y), the feedback MOSFET
The test execution signal CHK is applied to the gate terminals of FM1 and FM2.
Is applied. Thereby, the cell logic block C
When the self-verification of the LB is desired, the test execution signal CHK
Is set to high level, the feedback MOSFET
The signal whose output / Z is delayed by turning on the FM1 and FM2 is fed back to the gate terminals of the MOSFETs M1 to M4, and the AND gate circuit LG1 oscillates at a predetermined frequency.

Exclusive OR gate circuit (comparing means) LG
2 are MOSFETs CM1 and CM2 connected in series between the power supply voltage terminal Vcc and the ground GND, and MOSFETs LCM3 and CM4 connected in series between the high voltage power supply terminal VH and the ground GND. , CM1 and C
A first capacitor C1 connected between a connection node N21 with M2 and a ground point GND and a second capacitor C2 connected between a connection node N22 between CM3 and CM4 and a ground point GND. Become. The negative-phase output signal / Z of the preceding AND gate circuit LG1 is applied to the gates of CM1 and CM4, and the preceding AND gate circuit L is applied to the gates of CM2 and CM3.
It is configured such that the positive-phase output signal Z of G1 is applied.

As described above, this circuit sets the test execution signal CHK to high level and sets the logical product gate circuit LG1.
When the AND gate circuit LG1 is operating normally, the output signals Z and / Z alternately alternately alternate between high level and low level.
Since 1 and CM2 are alternately turned on and off, and CM3 and CM4 are turned on and off alternately, the capacitors C1 and C2 repeat charging and discharging, respectively, and the potentials of the nodes N21 and N22 do not rise.

However, if the AND gate circuit LG1 has a defect, the output signals Z and / Z do not repeat the high level and the low level complementarily, respectively.
Since either M1 or CM2 and either CM3 or CM4 continue to be turned on, the capacitance C1
Alternatively, the charge or discharge of C2 becomes unbalanced, and the potential of one of the nodes N21 and N22 rises. This potential is applied to the MOSFET Q of the memory cell SMC for wiring connection information storage via the diodes D1 and D2.
1 gate, the AND gate circuit L
By reading out the data stored in the wiring connection information storage memory cell SMC after oscillating G1 for a predetermined time or more, it is possible to detect whether or not the AND gate LG1 operates normally.

The test execution signal CHK may be directly input from outside the chip, or a suitable mode control circuit may be provided so that when a test mode is designated from the outside, a high level test execution signal is output from the mode control circuit. The signal CHK may be output to cause the cell logic block CLB to perform a self-verification operation.

FIG. 4A shows the cell logic block CLB.
2 shows another configuration example.

The cell logic block CLB of this embodiment is
A flip-flop FF1 that is a built-in BIST (built in self test) built-in logic block and latches two input signals X and Y and outputs positive and negative phase signals X, / X; Y, / Y, respectively. , FF2, a logic unit ALU which can perform a plurality of logical operations such as a logical sum, a logical product, and an exclusive logical sum using these four output signals as input signals, and latches an output Z of the logical unit ALU to be in a positive phase. The signal Z of the opposite phase,
/ Z, a readable / writable memory MEM for storing control information for specifying the logical operation of the logical unit, and a well-known LFSR (Linear Feedback Shift) for generating a test pattern in the form of a random number.
Register) and a comparator CMP and the like.

The memory MEM for storing the logical unit control information is configured so that control information can be written from outside. The LFSR has a switch MOSFET G
It is configured to be connectable to the input signal X, Y and the transmission signal line of the logical unit control information and the output signal Z, / Z of the FF 3 via 1 to G7, and operates in synchronization with the clock CLK.

When the cell logic block CLB of this embodiment is operated for self-verification, the switch MOSFET G
The inspection execution signal CHK is input to the gates 1 to G7 and turned on. Then, a random pattern is formed by the LFSR and supplied to the flip-flops FF1 and FF2 and the logic unit ALU, and the generated pattern and the output of the flip-flop FF3 are logically synthesized and compressed, and are output as the comparator CM as a signature pattern.
Output to P.

The comparator CMP is, for example, as shown in FIG.
, A read-only memory ROM storing an expected signature pattern, an exclusive OR gate EOR, an output latch OLT, and a clock C
It comprises a timing generating circuit TMG for generating a latch timing signal from the LK. When the signature pattern is input from the LFSR, the comparator CMP
Lead by exclusive OR gate EOR
The expected signature pattern stored in the only memory ROM is compared with the output pattern of the LFSR. If they match, a low-level signal is output. If they do not match, a high-level signal is output. This output is the latch OLT
And is output as a signal ERR indicating good / bad.

Then, as shown in FIG. 2C, the output signal ERR is applied to the wiring connection information storage memory cell SM.
Since it is configured to be inputted to the drain of the MOSFET Q1 of C, that is, the gate of Q2, by performing the self-verification operation of the cell logic block CLB, by reading the storage data of the memory cell SMC for storing the wiring connection information, It is possible to detect whether the corresponding cell logic block CLB operates normally. When using LFSR,
The error signal ERR to the memory cell SMC is at a normal high level, and is a reverse signal in FIG.

The principle of operation of the LFSR is already known and has been described in various documents, so that a detailed description thereof will be omitted. However, optimization according to the principle can be performed according to the principle. In a general logic LSI having a built-in BIST to which the LFSR is applied, optimization of the LFSR is required for each logic circuit, which is troublesome in design. However, the FPGA of the present embodiment uses the same cell logic block CLB. Therefore, the optimization can be performed uniformly, and the design burden is reduced. Further, in a conventional LSI having a built-in BIST, one BIST is a global BIST for inspecting all the LSI internal circuits.
Since the BIST of this embodiment is a local BIST provided in each cell logic block CLB, test sufficiency is also guaranteed.

Next, the procedure of the self-verification test in the FPGA (variable logic integrated circuit) shown in FIG.
This will be described with reference to FIG.

In the FPGA of this embodiment, after the power supply voltage of the chip is first turned on, the connection information storage memory cell SMC in the FPGA is cleared or the connection information storage memory cell SMC is shown to be normal by using a tester. Data (for example, a logic level opposite to a logic level indicating a defect state by self-verification of the cell logic block CLB) is written (step S11).

Then, the test execution signal CHK is set to a high level. Then, in the FPGA using the cell logic block CLB of the embodiment of FIG. 3, the logic gate circuit LG
When the logic gate circuit LG1 is activated and the logic gate circuit LG1 oscillates and has a defect, the output of the logic gate circuit LG2 goes high and the output state is stored in the connection information storage memory cell SMC. (Step S12). In addition, F using the cell logic block CLB of the embodiment of FIG.
In the PGA, when the LFSR operates to generate a random number and a failure occurs, a high-level error signal ERR is output, and the output state is stored in the connection information storage memory cell SMC.

Next, data is read from the memory cell SMC (step S13). Then, by checking the read data, it is determined which cell logical block CLB has a defect (step S11).
4).

Subsequently, for example, data opposite to the data set or written in step S11 is stored in the memory cell S.
The data is written to and read from the MC (step S15). And
By comparing the read data with the write data, a cross point switch CSW having a defect in the memory cell SMC or the switch Qsw is detected (step S16).

Next, in the tester, a map of the normal cross point switch CSW and the cell logic block CLB is created based on the above determination result (step S1).
7). The created map, that is, information indicating normal / abnormal of the cross point switch CSW and the cell logic block CLB is stored in a storage device or the like in the tester.

Then, the HDL description of the logic circuit to be built on the FPGA is read from a database or the like, and is subjected to logic synthesis or the like using a tester, and the defective cross point switch CSW and the cell logic block CLB are avoided based on the above map. Data for constructing a logic circuit having a desired function is generated (step S18). This data is obtained from the switch M of the normal crosspoint switch CSW.
This is data for selectively turning on the OSFET Qsw in accordance with the logic to be configured.

Finally, the generated data is written into the memory cell SMC for storing wiring connection information of the cross point switch CSW and the memory MEM for storing logical operation control information of the cell logic block CLB by a tester (step S1).
9). As a result, a circuit having desired logic is constructed on the FPGA using only normal cell logic blocks without defects.

FIG. 6 shows a circuit configuration example of a system for writing data to the memory cells SMC and MEM. This data writing system is operated separately from the original operation of the FPGA. The normal operation and the memory cell write operation of such an FPGA are switched by, for example, a control signal WM supplied from outside the chip to a mode switching control terminal. When the control signal WM indicates the memory cell write mode, an externally input address signal ADR is taken into the address input buffer circuit AIB, and the X decoder circuit XD
The signals are supplied to the EC and Y decoder circuit Y-DEC and decoded.

The X decode circuit X-DEC receives the input X
According to the address signal, one of a plurality of word lines WL extending from the X decoder circuit X-DEC to the FPGA including the variable logic block and the cross point switch is set to a selection level. The decode output of the Y decoder circuit Y-DEC is supplied to a write circuit WDR. The write circuit WDR includes a plurality of write circuits extending from the Y decoder circuit Y-DEC toward the variable logic block CBL and the cross point switch CSW in the FPGA. One of the data lines DL is selected, and at the same time, the selected data line DL is set to a high level or a low level in accordance with data input from outside via the data input buffer circuit DIB.

It should be noted that IOB is a buffer circuit for input / output signals to and from the original logic section constituted by the variable logic block CLB and the cross point switch CSW. The input / output buffer circuit IOB may be configured by the cell logic block CBL and the cross point switch CSW, or may be separately configured as a dedicated input / output buffer cell. This is because a semiconductor integrated circuit always requires a signal input / output buffer.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, in the above-described embodiment, the exclusive OR gate circuit L which detects whether or not the circuit in the cell logic block CLB is normal and outputs it is output.
Although the output state of G2 is stored in the memory cell SMC in the cross point switch circuit CSW, the output state may be output to the outside of the chip.

In the above description, the invention made mainly by the present inventor is described in the field of application of FPG
A case where the present invention is applied to A has been described as an example, but the present invention is not limited thereto, and in addition to an FPGA, a CPU, an SRAM,
Logic LSI with DRAM etc. and analog FPG
It can also be used for A and semiconductor integrated circuits on which digital and analog circuits are mounted.

[0065]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

In other words, according to the present invention, the internal circuit can be tested without using a high-performance external tester, and the yield and reliability can be detected and the self-rescue can be detected by itself. There is an effect that a high variable logic integrated circuit (FPGA) can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of an embodiment of an FPGA as an example of a variable logic integrated circuit to which the present invention is applied.

FIG. 2 is a block diagram showing a specific example of a cross point switch constituting the FPGA.

FIG. 3 is a logic circuit diagram and a conceptual diagram showing a specific example of a cell logic block constituting an FPGA.

FIG. 4 is a logic circuit diagram showing another example of a cell logic block constituting the FPGA.

FIG. 5 is a flowchart illustrating an example of a self-verification procedure in an FPGA to which the present invention is applied.

FIG. 6 is a circuit diagram showing an example of a circuit for writing data to memory cells constituting a cell logic block and a switch matrix.

FIG. 7 is a block diagram illustrating an example of a conventional variable logic integrated circuit.

[Explanation of symbols]

Reference Signs List 100 semiconductor chip 121, 122 wiring group CLB cell logic block (basic logic cell) CSW cross point switch (variable switch circuit) SMC wiring connection information storage memory cell LFSR random number generation circuit ALU logical operation unit CMP determination means (comparison circuit)

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Masayuki Sato 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Within the Semiconductor Group, Hitachi, Ltd. F-term in Hitachi Semiconductor Co., Ltd. F-term (reference) 5F038 AV13 CA02 CA04 CD08 DF01 DF05 DF14 DT02 DT06 DT07 DT08 DT14 DT17 DT19 EZ20

Claims (6)

[Claims] 1. A semiconductor chip comprising: a plurality of basic logic cells on a semiconductor chip; and a variable switch circuit capable of switching connection of a signal line between these basic logic cells. And a variable logic circuit capable of outputting a signal indicating the same and configuring an arbitrary logic by switching the connection by the variable switch circuit. 2. The basic logic cell comprises a two-line logic circuit capable of outputting a complementary signal and a judging means for comparing the complementary output signal of the two-line logic circuit to determine the presence or absence of an abnormality. The signal output from the two-line logic circuit is supplied to the two-line logic circuit in another basic logic cell, and the output signal of the determination means determines whether the circuit is normal or abnormal. 2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is configured to be output from a cell. 3. The basic logic cell includes a plurality of input signal latch means for respectively latching two or more input signals, and selectively executes a plurality of logic operations using output signals of these input signal latch means as input signals. A possible logic unit, output signal latch means capable of latching the output of the logic unit and outputting the logic unit, readable and writable memory means for storing control information designating the logic operation of the logic unit, and generating a test pattern A random number generation circuit for supplying the input signal to the input signal latch means and the logic unit; and a determination means for comparing the signal output from the output signal latch means with an expected value to determine the presence or absence of an abnormality. The signal output from the signal latch means is supplied to the input signal latch means in another basic logic cell, and the output signal of the determination means is 2. The semiconductor integrated circuit according to claim 1, wherein each of the basic logic cells outputs a signal indicating whether the circuit is normal or abnormal. 4. The variable switch circuit comprises: switch means for disconnecting signal lines crossing each other, and readable and readable storage means for storing information for controlling the state of the switch means. 4. The semiconductor integrated circuit according to claim 2, wherein a signal indicating whether the circuit output from the means is normal or abnormal is stored in the storage means. 5. A storage device comprising: a selection unit that can select any one of the storage units based on an external signal; and a writing unit that writes externally input data to a selected storage element. The semiconductor integrated circuit according to claim 2, 3 or 4, wherein: 6. A semiconductor integrated circuit having a variable logic circuit having a plurality of basic logic cells and a variable switch circuit capable of switching connection of signal lines between these basic logic cells mounted on a semiconductor chip. In the method, first, the variable logic circuit performs a self-test on whether the circuit is normal or abnormal for each of the basic logic cells, and uses the information indicating the defective portion obtained as a result in the variable logic circuit. A method of manufacturing a semiconductor integrated circuit, wherein a desired logic function is configured using only basic logic cells determined to be normal by switching connections by the variable switch circuit.