JP3618181B2 - Semiconductor integrated circuit having test circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a test circuit capable of performing a direct current test of an input / output circuit portion of a semiconductor integrated circuit, in particular, a current leak test without directly probing the input / output terminal.
[0002]
[Prior art]
Conventional integrated circuit testing methods include a method in which a test probe is brought into direct contact with an input / output terminal and a tester driver circuit, a comparator, and a DC measurement circuit are connected, and an internal flip-flop circuit as in the JTAG boundary test method. Connect to the input / output terminal by inputting a predetermined test pattern (diagnostic pattern) connected in a chain, driving the internal circuit, and detecting the drive result from the internal flip-flop circuit connected in the chain again There is a method of performing the test without any problem.
[0003]
On the other hand, as shown in FIG. 11, in recent large scale integrated circuits, an area bump system in which a large number of input / output terminals (pads) of 1000 or more are arranged in a matrix on the surface of the chip is adopted. The distance between the pads has been shortened, and direct contact with the test probe is reaching its limit.
[0004]
In addition, with such an increase in scale, there is a tendency that the leak failure between the input / output pads and the leak failure of the elements inside the integrated circuit tend to occur. Besides simply confirming that the logic is normal, It is becoming important to conduct a leak test.
[0005]
FIG. 12 is a diagram illustrating an example of a circuit that performs a test without touching the input / output pads described above. Pa1 and Pa2 are input / output pads, and the inverter I1 is a part of the internal circuit. The inverter I2 is a part of the test circuit. In this example, the switch SW1 can be closed to transmit the signal from the input terminal Pa1, or the switch SW2 can be closed to supply the output of the inverter I2 to the inverter I1 of the internal circuit. Further, in the test mode, by configuring a scan chain in which the flip-flops 10 and 11 are connected in a chain shape, test pattern input setting and driving result reading are performed.
[0006]
Then, for example, the test pattern data is supplied from the Sin to the flip-flops 10 and 11 for setting, and the logic circuit executes one clock operation, thereby driving the internal inverter I1 by the inverter I2 and flipping the output thereof. By reading the data fetched by the flip-flop 11 and the data fetched again by the flip-flops 10 and 11 from Sout, it is possible to test whether or not the inverter I1 is operating normally.
[0007]
[Problems to be solved by the invention]
However, in such a test circuit, a test is performed to determine whether or not there is a leak L1 between the input / output pads Pa1 and Pa2 for some reason, and whether or not there is a leak L2 such as a junction portion of an internal element. It cannot be done normally. That is, since the drive capability of the inverter I2 is set to be relatively large, even if the leaks L1 and L2 exist, the logic of the output detected by the flip-flop 11 is normal due to the drive capability to overcome the leak current. It becomes logic.
[0008]
Therefore, the above test circuit can perform a logic test, but cannot detect the presence of a minute leak current. Such a minute leakage current increases as a result of long-term use of the integrated circuit, and may change as the logic is inverted in the future, and is desired to be detected at the shipping stage.
[0009]
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit having a test circuit that can detect a leakage current without contact with an input / output pad.
[0010]
[Means for Solving the Problems]
According to the present invention, the above object is achieved in a semiconductor integrated circuit having a plurality of input / output terminals, a plurality of flip-flops and a logic circuit therein,
The plurality of flip-flops are connected in a chain or via a decoder to set test pattern data and read out internal data of test results, and have a driving capability lower than that of the internal logic circuit driver A test circuit configured such that data from a predetermined flip-flop is supplied to its input, its output is connected to the input / output terminal, and data according to the output is taken into another flip-flop. This is achieved by providing a semiconductor integrated circuit characterized by the following.
[0011]
When there is a leak current at the input / output terminal or the internal element, the leak test driver cannot invert the output, and the presence of the leak current can be detected from the data taken into the flip-flop.
[0012]
Further, according to the present invention, in the semiconductor integrated circuit having a plurality of input / output terminals, a plurality of flip-flops and a logic circuit,
The plurality of flip-flops are connected in a chain or via a decoder to set test pattern data and read out internal data of test results, and have a driving capability lower than that of the internal logic circuit driver This is achieved by providing a semiconductor integrated circuit provided between the flip-flops, wherein the output of the leak test driver is connected to the input / output terminal.
[0013]
By providing a leak test driver in the scan chain circuit, the presence of a rake current can be detected by a shift operation between flip-flops. In order to shorten the test time, in the present invention, a driver having a higher driving capability is provided in parallel with the driver for leak testing, and the driving capability is set at the time of setting and reading test pattern data in the flip-flop. A high driver is enabled, and the leak test driver is enabled at the time of the leak detection test after the setting, and a shift operation is performed.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, examples of embodiments of the present invention will be described with reference to the drawings. However, such an embodiment does not limit the technical scope of the present invention.
[0015]
FIG. 1 is a circuit diagram of the first embodiment. In this example, an inverter circuit I3 which is a driver having a small driving capability for detecting DC leakage is added to the conventional circuit shown in FIG. 12, and the inverters I2 and I3 which are driver circuits can be appropriately selected by a test signal TEST. There is a feature in this point. That is, in the normal logic test, the inverter I2 having a large driving capability is enabled by the test signal TEST, the test pattern data is set by the flip-flops 10 and 11 via the scan chain, the logic circuit is driven, and the result is read. In the DC leak test, the inverter I3 having a smaller driving capability is enabled by the test signal TEST, and the test pattern is set, the logic circuit is driven, and the result is read out in the same manner. When the inverter I3 having a small driving capability is enabled, the logic of the output of the inverter I3 is inverted due to the presence of the leakage currents L1 and L2, and is detected as a logic inversion by the flip-flop 11 provided in the internal circuit.
[0016]
Accordingly, the flip-flops 10 and 11 are connected to form a scan chain. As a test pattern, for example, “1” is input to the flip-flop 10 and “0” is input to the flip-flop 11, and the inverter I2 is enabled to make the logic circuit 1 Clock operation. As a result, the logical value read into the flip-flop 11 is formed again from the Sout by forming a scan chain, and the leakage current depends on whether the value of the flip-flop 11 has changed from “0” to “1”. Whether it exists or not can be detected.
[0017]
In the example of FIG. 1, the leak current can be similarly detected even if the flip-flop 11 directly takes in the output of the inverter I3 via the switch SW2 without going through the inverter I1.
[0018]
FIG. 2 is a detailed circuit diagram of the circuit of FIG. FIG. 3 is a chart for explaining the operation of the circuit. In FIG. 2, switches SW1 and SW2 are CMOS switches composed of P-type transistors P1 and P2 and N-type transistors N1 and N2. The inverters I2 and I3 are CMOS inverters controlled by a test signal TEST, and the transistor of the inverter I3 is designed so that the driving capability is smaller than that of the inverter I2. Reference numerals 12, 13, 14, and 15 denote an inverter, a NOR circuit, a NAND circuit, and an inverter, respectively.
[0019]
As shown in the chart of FIG. 3, when the selection signal SELECT is 0 and the test signal TEST is 0, the switch SW1 is opened and the input / output pad P1 is used as a normal input. During the test, the selection signal SELECT is 1 and the test signal TEST is 0, and the test pattern in the flip-flop 10 is input from the inverter I2. In this case, it is the same as the conventional test.
[0020]
Further, when the selection signal SELECT is 0 and the test signal TEST is 1, it is a DC leak test state, the switches SW1 and SW2 are both on, and the inverter I3 is enabled. Therefore, the inverted output according to the test pattern input to the flip-flop 10 is supplied to the internal circuit by the inverter I3 having a low driving capability. Since the transistors P5, P6, N5, and N6 have a small driving capability and are supplied with only a minute driving current, if the leakage current L1 between the input / output pads Pa1 and Pa2 or the leakage current L of the internal element exists, the driving of the inverter I3 is performed. The current cannot overcome these leakage currents and the logic is reversed. Therefore, the presence of a minute leak current can be confirmed.
[0021]
In this test, a desired leak current can be detected by combining the test pattern Sin with an appropriate combination. For example, a leak between the input / output pad Pa1 and the power supply pad can be detected by setting at least 1 and 0 signals to the flip-flop 10 as the test pattern Sin once.
[0022]
When the selection signal SELECT is 1 and the test signal TEST is 1, only the switch SW2 is turned on and the output of the inverter I3 is supplied to the internal circuit. In this mode, it is possible to determine whether or not the inverter I3 is operating normally by cutting off the influence from the input / output pads.
[0023]
FIG. 4 is a circuit diagram of the second embodiment. FIG. 5 is a detailed circuit diagram thereof. FIG. 6 is a chart for explaining the operation. This example differs from FIGS. 1 and 2 in that the output of the inverter I3 having a small driving capability is directly connected to the input / output pad Pa1. The inverters I2 and I3 are switched by the test signal TEST, and the switches SW3 and SW4 are switched by the selection signal SELECT. The switches SW3 and SW4 are composed of an inverter 16 and NOR circuits 17, 18, 19 as shown in FIG. The inverters I2 and I3 are switched by a CMOS circuit similar to that shown in FIG.
[0024]
As shown in the chart showing the operation of FIG. 6, when the selection signal SELECT is 0, the output of the NOR gate 17 is forcibly set to 0, but the output of the NOR gate 18 has a logic corresponding to the output of the inverter I2. Thus, the output of the inverter I2 is given to the inverter I1 which is an internal circuit through the NOR gate 19. When the selection signal SELECT is 1, the output of the NOR gate 18 is forcibly set to 0, and the output of the NOR gate 17 becomes a logical value according to the output value of the input pad Pa1 or the inverter I3 and is supplied to the inverter I1. The
[0025]
Therefore, if the test signal TEST is set to 1 to enable the inverter I3, the selection signal SELECT is set to 1 and the switch SW3 is turned on, the leakage currents L1 and L2 can be detected.
[0026]
4 and 5, by setting the scan signal Sin to the internal flip-flop 10, it is possible to form a situation as if a logical value set from the input pad Pa1 is input. Therefore, it is possible to perform a test of a single chip even when an integrated circuit is mounted. Even in the case of such a test circuit, the present invention can detect the presence of a leakage current by reducing the drive capability of the inverter I3.
[0027]
FIG. 7 is a circuit diagram of the third embodiment. In this example, a plurality of inverters having a small driving capability that can be replaced with the inverter I2 constituting the normal scan chain circuit are provided in a plurality of I31, I32, I33. . Each drive capability is varied step by step, and the selection signal is decoded by the decoder DEC so that one inverter can be selected. In this way, for example, the inverters I31, I32, I33. . The DC leakage test is performed, and the inversion of the logic output due to the leakage current is detected in each inverter, so that it is possible to detect how much the leakage current is.
[0028]
The test signal TEST and the selection signal SELECT shown in FIG. 7 enable the switches SW1 and SW2 to be turned on at the same time and select the inverters I31 to I38 having a small capacity in the same combination as in FIGS. Therefore, a stricter leak detection test is possible.
[0029]
FIG. 8 is a signal waveform diagram for explaining that the degree of leakage current detected in FIG. 7 can be detected even in the case of the circuits of FIGS. In the case of the circuits of FIGS. 1 to 5, there is only one type of inverter with a small driving capability. However, as shown in FIG. 8, when the leakage current is extremely small, even if the inverter has a small driving capability, the inverter overcomes and the logic output becomes H level, for example. In that case, if the leakage current is a certain level, the drive capability of the inverter is lost, and the logic output becomes L level as shown by the alternate long and short dash line. When the leakage current is about halfway between them, for example, by switching the logic and waiting for time td, it is detected that the logic output becomes H level as shown by the broken line in the figure. Therefore, it is possible to detect a certain level of leakage current intensity by waiting for a relatively long time. By increasing the timing time td of the data fetch clock of the flip-flop 10 that fetches the output of the inverter I3 stepwise, the degree of the leak current can be detected.
[0030]
FIG. 9 is a circuit diagram in which driver circuits I2 and I3 are provided in a scan chain composed of flip-flops 10, 11, and 12 to perform a leak test. In other words, in the above-described embodiment, test pattern data is set with a scan chain connecting flip-flops, the driver in the non-test circuit is switched to one with a low driving capability, and the result is again displayed with the scan chain. I'm reading. In contrast, in this example, a driver I2 having a large driving capability and a driver I3 having a small driving capability are provided in the scan chain so as to be switchable. By adopting such a configuration, it is possible to detect the presence of a leak current at the input / output pad simply by scanning the scan chain.
[0031]
In this example, the flip-flops 10, 11, and 13 forming the scan chain are constituted by, for example, master slaves. Then, in the scan chain, for example, “0” is set to the flip-flop 10 and “0” is set to the flip-flop 11 via the driver I2 having high driving capability from Sin. Then, switching to the driver I3 side is performed, and the scan chain is shifted once again. As a result, “1” is taken into the flip-flop 10 according to the data “0” set in the flip-flop 11. In this case, it means that there was no leakage current. When the leak current is in the input / output pad Pa1 or the like, the flip-flop 10 remains “0”. Then, the driver I2 is switched again and the data in the flip-flop 10 is read from Sout.
[0032]
As described above, when setting or reading test data by the shift operation in the scan chain, the driver I2 having a relatively high driving ability is used, and the driver I3 having a small driving ability is used for detecting a leak current. By using the driver I2 at the time of reading again, the time of the entire test can be shortened.
[0033]
Further, by changing the period of each of the clocks CLK1 and CLK2 stepwise, a correct logical value is detected in a certain period according to the degree of leakage current, and an inverted logical value is detected in a certain period. That is, the cycle of the clock signal shown in FIG. 10 is made variable. By doing so, the degree of leakage current can also be detected.
[0034]
In the above example, the flip-flops are connected in a chain shape. However, the present invention can also be applied to a configuration in which a predetermined flip-flop is selected by a decoder and connected to an internal logic circuit, for example. In this case, test pattern data is set for each flip-flop selected by the decoder, and after the operation by a driver having low driving capability, the flip-flop selected by the decoder is read. To do.
[0035]
【The invention's effect】
As described above, according to the present invention, in a semiconductor integrated circuit, it is possible to detect the presence of a DC leakage current inside or at an input / output pad without contacting the input / output pad. In addition, by providing a plurality of types of inverters and drivers having a low drive capability provided in the test circuit, the degree of the leakage current can be detected. Further, by providing a leak test driver having a low driving capability in the scan chain, a leak current detection test can be performed only by a shift operation in the scan chain circuit.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a first embodiment.
FIG. 2 is a detailed circuit diagram of the circuit of FIG.
FIG. 3 is a chart for explaining the operation of the circuit of FIG. 2;
FIG. 4 is a circuit diagram of a second embodiment.
FIG. 5 is a detailed circuit diagram of FIG. 4;
6 is a chart for explaining the operation of the circuit of FIG. 4;
FIG. 7 is a circuit diagram of a third embodiment.
FIG. 8 is a signal waveform diagram for explaining that the degree of leakage current can be detected even in the case of the circuits of FIGS.
FIG. 9 is a circuit diagram in which driver circuits I2 and I3 are provided in a scan chain constituted by flip-flops 10, 11, and 12 to perform a leak test.
FIG. 10 is a diagram illustrating a clock signal.
FIG. 11 is a surface view of a conventional large-scale integrated circuit chip.
FIG. 12 is a diagram illustrating an example of a circuit that performs a test without touching an input / output pad;
[Explanation of symbols]
10, 11 Flip-flop Pa1 Input / output terminal I1 Internal logic circuit I2 Driver I3 Driver for leak test

Claims (4)

In a semiconductor integrated circuit having a plurality of input / output terminals, a plurality of flip-flops and a logic circuit therein,
The plurality of flip-flops are connected in a chain or via a decoder to set test pattern data and read internal data of test results,
A leak test driver having a driving capability lower than that of the internal logic circuit driver is supplied with data from a predetermined flip-flop at its input, its output is connected to the input / output terminal, and data according to its output is different. A semiconductor integrated circuit comprising a test circuit configured to be incorporated into a flip-flop of The semiconductor integrated circuit according to claim 1,
The leak test driver includes a plurality of drivers having different driving capacities in stages, and a plurality of drivers are appropriately selected. In a semiconductor integrated circuit having a plurality of input / output terminals, a plurality of flip-flops and a logic circuit therein,
The plurality of flip-flops are connected in a chain or via a decoder to set test pattern data and read internal data of test results,
A semiconductor integrated circuit characterized in that a leak test driver having a driving capability lower than that of the driver of the internal logic circuit is provided between the flip-flops, and an output of the leak test driver is connected to the input / output terminal. circuit. The semiconductor integrated circuit according to claim 3.
A driver with higher driving capability is provided in parallel with the driver for leak testing, and the driver with higher driving capability becomes effective when setting and reading test pattern data in the flip-flop, and the leak detection test after the setting At this time, the leak test driver is enabled and a shift operation is performed.

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