JPH10123212A - Semiconductor integrated circuit with test circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect a leak current without contacting an I/O terminal by connecting output to the I/O terminal and further allowing data that follow the output to be taken by another flip flop. SOLUTION: An inverter circuit I3 that is a driver with a small driving capacity for detecting DC leakage is added and, an inverter 12 and the drive I3 that are drivers are properly selected according to a test signal TEST. Flip flops 10 and 11 are connected to constitute a scan chain, '1' and '0' are inputted, as a test pattern, to the flip flops 10 and 11, respectively, to make efficient the inverter I2 and to operate a logic circuit as one-clock operation. As a result, by reading a logic value that is read by the flip flop 11 from Soul by constituting a scan chain again, the presence or absence of a leak current can be detected depending on whether the value of the flip flop 11 has changed from '0' to '1' or not.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test circuit capable of performing a DC test on an input / output circuit portion of a semiconductor integrated circuit, particularly, a current leak test without directly probing the input / output terminals.

[0002]

2. Description of the Related Art Conventional integrated circuit testing methods include a method in which a test probe is brought into direct contact with an input / output terminal and a tester driver circuit, a comparator and a DC measurement circuit are connected, and an internal method such as a JTAG boundary test method. The flip-flop circuits are connected in a chain and a predetermined test pattern (diagnosis pattern) is input to drive the internal circuit.
There is a method in which a test is performed without contacting an input / output terminal by detecting the driving result from an internal flip-flop circuit connected in a chain again.

On the other hand, as shown in FIG. 11, a recent large-scale integrated circuit employs an area bump method in which a large number of input / output terminals (pads) of 1000 or more are arranged in a matrix on the surface of a chip. As the distance between input and output pads is shortened, direct contact with a test probe is reaching its limit.

Further, with such a large scale, there is a tendency that the probability of occurrence of leakage failure between input / output pads and leakage failure of elements inside an integrated circuit tends to increase, and it is simply confirmed that the logic is normal. Besides, it has become important to conduct a leak test.

FIG. 12 is a diagram showing an example of a circuit for performing a test without touching the above-mentioned input / output pad. Pa1,
Pa2 is an input / output pad, and the inverter I1 is a part of an internal circuit. The inverter I2 is a part of the test circuit. In this example, the switch SW1 is closed to transmit a signal from the input terminal Pa1 to the inside,
2, the output of the inverter I2 can be supplied to the inverter I1 of the internal circuit. In the test mode, a scan chain in which the flip-flops 10 and 11 are connected in a chain form is used to set a test pattern input and read a driving result.

Then, for example, flip-flops 10, 1
1, the test pattern data is supplied from Sin, the setting is performed, and a single clock operation is executed by the logic circuit. The internal inverter I1 is driven by the inverter I2, the output is taken into the flip-flop 11, and the flip-flop 11 is again activated. The data captured by the
By reading from t, it can be tested whether the inverter I1 is operating normally.

[0007]

However, in such a test circuit, it is determined whether or not the leak L1 exists between the input / output pads Pa1 and Pa2 for some reason, and the leak L2 such as a junction between the internal elements. Cannot be tested normally for the presence of That is, the inverter I
2 is set relatively large, and even if the leaks L1 and L2 exist, the output logic detected by the flip-flop 11 becomes a normal logic due to the drive ability overcoming the leak current. .

Accordingly, the above test circuit can perform a logic test, but cannot detect the presence of a minute leak current. Such a small leak current increases as a result of using the integrated circuit for a long period of time, and may change in the future so that the logic is inverted.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor integrated circuit having a test circuit capable of detecting a leakage current without contacting an input / output pad.

[0010]

According to the present invention, there is provided a semiconductor integrated circuit having a plurality of input / output terminals, a plurality of flip-flops and a logic circuit therein, wherein the plurality of flip-flops are chained. Configuration of the test pattern data,
The internal data of the test result is read, and a leak test driver having a lower driving ability than the driver of the internal logic circuit is supplied with data from a predetermined flip-flop at its input. And a test circuit configured to take in data according to the output of the flip-flop into another flip-flop.

When a leak current exists at an input / output terminal or an internal element, the leak test driver cannot invert its output, and can detect the presence of the leak current based on data taken into a flip-flop. it can.

Further, according to the present invention, there is provided a semiconductor integrated circuit having a plurality of input / output terminals, a plurality of flip-flops and a logic circuit therein, wherein the plurality of flip-flops are arranged in a chain or a decoder. The setting of the test pattern data and the reading of the internal data of the test result are performed, and a leak test driver having a lower driving capability than the driver of the internal logic circuit is provided.
This is achieved by providing a semiconductor integrated circuit provided between the flip-flops, wherein an output of the leak test driver is connected to the input / output terminal.

By providing a leak test driver in the scan chain circuit, the presence of a rake current can be detected by a shift operation between flip-flops. Further, in order to shorten the test time, in the present invention, a driver having a higher driving capability is provided in parallel with the leak test driver, and the driving capability is set when the test pattern data is set and read in the flip-flop. A high driver is enabled, and at the time of a leak detection test after the setting, the leak test driver is enabled to perform a shift operation.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, such embodiments do not limit the technical scope of the present invention.

FIG. 1 is a circuit diagram of the first embodiment. In this example, an inverter circuit I3, which is a driver having a small driving capability for DC leakage detection, is added to the conventional circuit shown in FIG. 12, and the inverters I2 and I3, which are driver circuits, can be appropriately selected by a test signal TEST. There is a characteristic in the point that it did. That is, in a normal logic test, the inverter I2 having a large driving capability is connected to the test signal T
Enable by EST and flip-flops 10, 11
Setting of test pattern data, driving of a logic circuit, and reading of a result through a scan chain according to the above. In the DC leakage test, an inverter I3 having a smaller driving capability is enabled by a test signal TEST, and a test pattern is similarly set. Setting, driving the logic circuit, and reading the result. When the inverter I3 having a small driving capability is enabled, the logic of the output of the inverter I3 is inverted due to the presence of the leakage currents L1 and L2, and is detected as inverted by the flip-flop 11 provided in the internal circuit.

Therefore, a scan chain is formed by connecting the flip-flops 10 and 11, and, for example, "1" is input to the flip-flop 10 and "0" is input to the flip-flop 11 as a test pattern, and the inverter I2 is enabled to enable the logic. The circuit is clocked once. As a result, the logic value read into the flip-flop 11 is read again from Sout by forming a scan chain again, and the leak current is determined depending on whether the value of the flip-flop 11 changes from “0” to “1”. It can be detected whether it exists.

In the example shown in FIG. 1, even if the flip-flop 11 directly takes in the output of the inverter I3 via the switch SW2 without passing through the inverter I1, the leak current can be detected similarly.

FIG. 2 is a detailed circuit diagram of the circuit of FIG.
FIG. 3 is a chart for explaining the operation of the circuit. In FIG. 2, switches SW1 and SW2 are CMOS switches composed of P-type transistors P1 and P2 and N-type transistors N1 and N2. In addition, inverters I2, I
Reference numeral 3 denotes a CMOS inverter controlled by the test signal TEST, and the transistor of the inverter I3 is designed so that the driving capability is smaller than that of the inverter I2. 12, 13, 14, and 15 are inverters and N, respectively.
An OR circuit, a NAND circuit, and an inverter.

As shown in FIG. 3, the selection signal S
When ELECT is 0 and test signal TEST is 0, switch SW1 is opened and input / output pad P1 is used as a normal input. At the time of the test, the selection signal SELE
When CT is 1, the test signal TEST becomes 0, and the test pattern in the flip-flop 10 is input internally from the inverter I2. In this case, it is the same as the conventional test.

Further, when the selection signal SELECT is 0 and the test signal TEST is 1, a DC leakage test is being performed, the switches SW1 and SW2 are both on, and the inverter I3 is enabled. Therefore, an inverted output according to the test pattern input to the flip-flop 10 is supplied to the internal circuit by the inverter I3 having a low driving ability. Since the transistors P5, P6, N5, and N6 have a small driving capability and supply only a small driving current, if there is a leakage current L1 between the input / output pads Pa1 and Pa2 and a leakage current L of the internal element, the driving of the inverter I3 is performed. The current is unable to overcome those leakage currents and the logic is inverted. Therefore, the existence of a minute leak current can be confirmed.

In this test, a desired leak current can be detected by appropriately combining the test patterns Sin. For example, if there is a leak between the input / output pad Pa1 and the power supply pad, the test pattern Sin
Can be detected by setting the signals of at least 1 and 0 to the flip-flop 10 at least once.

When the selection signal SELECT is 1 and the test signal T
When EST is also 1, only switch SW2 is turned on, and the output of inverter I3 is supplied to the internal circuit. In this mode, it is possible to simply determine whether the inverter I3 is operating normally by cutting the influence from the input / output pad.

FIG. 4 is a circuit diagram of the second embodiment. FIG. 5 is a detailed circuit diagram thereof. FIG. 6 is a chart for explaining the operation. In this example, the output of the inverter I3 having a small driving capability is directly input / output pad Pa
1 and 2 is different from FIGS. The switching between the inverters I2 and I3 is performed by a test signal TEST, and the switching of the switches SW3 and SW4 is performed by a selection signal SELECT. Switch SW3, SW
4 includes an inverter 16 and NOR circuits 17, 18, and 19 as shown in FIG. The switching between the inverters I2 and I3 is performed by the same CMOS circuit as in FIG.

As shown in the operation chart of FIG. 6, when the selection signal SELECT is 0, the output of the NOR gate 17 is forcibly set to 0, but the output of the NOR gate 18 depends on the output of the inverter I2. Logic becomes NOR gate 1
9, the output of the inverter I2 is supplied to the inverter I1 which is an internal circuit. Also, the selection signal SELECT
Is 1, the output of the NOR gate 18 is forcibly set to 0, the output of the NOR gate 17 becomes a logical value according to the value of the output of the input pad Pa1 or the inverter I3, and is supplied to the inverter I1.

Therefore, if the test signal TEST is set to 1 to enable the inverter I3 and the selection signal SELECT is set to 1 to turn on the switch SW3, the leakage current L1,
L2 can be detected.

In the examples of FIGS. 4 and 5, by setting the scan signal Sin to the internal flip-flop 10, a situation can be formed as if the set logical value was input from the input pad Pa1. Therefore, it is possible to perform a test of a single chip even in a state where the integrated circuit is mounted. According to the present invention, even in the case of such a test circuit, the presence of a leak current can be detected by reducing the driving capability of the inverter I3.

FIG. 7 is a circuit diagram of the third embodiment. In this example, a plurality of inverters I31, I32, I33. . Provided,
The respective driving capacities are made to differ in stages, and a selection signal is decoded by a decoder DEC so that one inverter can be selected. In this way, for example, the inverters I31, I32, I3
3. . Is selected, a DC leakage test is performed, and each inverter detects the inversion of the logic output due to the leakage current, so that it is possible to detect how much leakage current.

The test signal TEST and the selection signal SE shown in FIG.
The LECT enables the switches SW1 and SW2 to be simultaneously turned on and the selection of the inverters I31 to I38 having a small capacity by a combination similar to that of FIGS. Therefore,
Enables a more rigorous leak detection test.

FIG. 8 is a signal waveform diagram for explaining that the degree of the leak current detected in FIG. 7 can be detected even in the circuits of FIGS. Figure 1
In the case of the circuit No. 5, there is only one type of inverter having a small driving capability. However, as shown in FIG. 8, when the leakage current is extremely small, it is assumed that even if the inverter has a small driving ability, the inverter overcomes the logic and the logical output becomes H level, for example. In this case, if the leakage current is a certain amount, the driving capability of the inverter is lost, and the logical output becomes L level as indicated by the dashed line. And
When the leakage current has an intermediate strength between them, for example, by switching the logic and waiting for the time td, it is detected that the logic output goes to the H level as shown by the broken line in the figure. Therefore, by waiting for a relatively long time,
It is possible to detect a certain level of leakage current.
Flip-flop 10 for taking in output of inverter I3
By gradually increasing the timing time td of the data fetch clock, the degree of the leak current can be detected.

FIG. 9 shows flip-flops 10, 11, 1
Driver circuit I in the scan chain composed of
FIG. 2 is a circuit diagram for performing a leak test by providing I2 and I3. That is, in the above-described embodiment, the test pattern data is set by the scan chain connecting the flip-flops, the driver in the non-test circuit is switched to the one having the lower driving capability, and the operation is performed again. I'm reading. On the other hand, in this example, a driver I2 having a large driving capability and a driver I3 having a small driving capability are provided in the scan chain so as to be switchable. With this configuration, it is possible to detect the presence of a leak current at the input / output pad by simply performing the scan operation of the scan chain.

In this example, the flip-flops 10, 11, and 13 forming a scan chain are constituted by, for example, a master slave. Then, in the scan chain, for example, “0” is set to the flip-flop 10 and “0” is set to the flip-flop 11 from the Sin via the driver I2 having a high driving capability. Then, the operation is switched to the driver I3 side, and the shift operation of the scan chain is performed once again. As a result, "1" is taken into the flip-flop 10 according to the data "0" set in the flip-flop 11. In this case, it means that there was no leak current. If a leak current is present at the input / output pad Pa1 or the like, the flip-flop 10 remains "0". Then, the mode is switched to the driver I2 again and Sou
The data in the flip-flop 10 is read from t.

As described above, when the test data is set or read out by the shift operation in the scan chain, the driver I2 having a relatively high driving capability is used, and the driving capability is reduced to detect the leak current. By using the driver I3 at the time of re-reading using the driver I3, the time of the entire test can be shortened.

Further, each of the clocks CLK1, CL
By changing the cycle of K2 stepwise, a correct logic value is detected in a certain cycle and an inverted logic value is detected in a certain cycle according to the degree of the leak current. That is, the period of the clock signal shown in FIG. 10 is made variable. By doing so, the degree of the leak current can be detected.

In the above example, an example in which flip-flops are connected in a chain has been described. However, the present invention is also applicable to a configuration in which, for example, a predetermined flip-flop is selected by a decoder and connected to an internal logic circuit. it can. In that case, the test pattern data is set for each flip-flop selected by the decoder, and the read after operation by a driver with low driving capability is to read each flip-flop selected by the decoder. Do with.

[0035]

As described above, according to the present invention, in a semiconductor integrated circuit, it is possible to detect the presence of a DC leakage current inside or at an input / output pad without contacting the input / output pad. Moreover, by providing a plurality of types of inverters and drivers having low drive capability provided in the test circuit, the degree of the leak current can be detected.
Further, by providing a leak test driver having a low driving capability in the scan chain, a leak current detection test can be performed only by a shift operation in the scan chain circuit.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment.

FIG. 2 is a detailed circuit diagram of the circuit of FIG. 1;

FIG. 3 is a table illustrating the operation of the circuit of FIG. 2;

FIG. 4 is a circuit diagram of a second embodiment.

FIG. 5 is a detailed circuit diagram of FIG. 4;

FIG. 6 is a table illustrating the operation of the circuit in FIG. 4;

FIG. 7 is a circuit diagram of a third embodiment.

FIG. 8 is a signal waveform diagram for explaining that the degree of leakage current can be detected even in the circuits of FIGS. 1, 2 and FIGS.

FIG. 9 is a circuit diagram for performing a leak test by providing driver circuits I2 and I3 in a scan chain composed of flip-flops 10, 11, and 12;

FIG. 10 is a diagram showing a clock signal.

FIG. 11 is a front view of a conventional large-scale integrated circuit chip.

FIG. 12 is a diagram illustrating an example of a circuit that performs a test without touching an input / output pad.

[Explanation of symbols]

 10, 11 flip-flop Pa1 input / output terminal I1 internal logic circuit I2 driver I3 leak test driver

Claims (4)

[Claims] 1. A semiconductor integrated circuit having a plurality of input / output terminals and a plurality of flip-flops and a logic circuit therein, wherein the plurality of flip-flops are connected in a chain or via a decoder to set test pattern data. The internal data of the test result is read out. A driver for a leak test having a lower driving ability than the driver of the internal logic circuit is supplied with data from a predetermined flip-flop at its input, and its output is input / output. A semiconductor integrated circuit having a test circuit connected to a terminal and configured so that data according to the output is taken into another flip-flop. 2. The semiconductor integrated circuit according to claim 1, wherein said leak test driver has a plurality of drivers having different driving capabilities in a stepwise manner, and a plurality of drivers are appropriately selected. . 3. A semiconductor integrated circuit having a plurality of input / output terminals and a plurality of flip-flops and a logic circuit therein, wherein the plurality of flip-flops are connected in a chain or via a decoder to set test pattern data. Internal data of a test result is read out, a leak test driver having a lower driving ability than a driver of the internal logic circuit is provided between the flip-flops, and an output of the leak test driver is input and output. A semiconductor integrated circuit connected to a terminal. 4. The semiconductor integrated circuit according to claim 3, further comprising a driver having a higher driving capability in parallel with said leak test driver, wherein said driver has a higher driving capability when setting and reading test pattern data in said flip-flop. The driver having a higher value is enabled, and at the time of the leak detection test after the setting, the driver for the leak test is enabled and the shift operation is performed.