JPH1152019A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid false detection, improve a failure detection rate and prevent the increase of consumption power on the occasion of a normal operation when the failure of a semiconductor integrated circuit including a tristate element is inspected by a scan test. SOLUTION: A bus signal auxiliary circuit 160 is set which generates a scan mode signal indicating that a scan mode is being executed and has a bus connection terminal 161 determining an electric state by the scan mode signal. The bus connection terminal 161 of the bus signal auxiliary circuit 160 is connected to a bus signal line 130 connecting outputs of one or more tristate elements 142. The bus signal auxiliary circuit 160 is constituted to pull up or pull down the bus connection terminal 161 at a scan test. At other times than the scan test, the bus connection terminal 161 is not pulled up or down, and therefore the bus connection terminal 161 is turned to a high impedance, preventing an unnecessary lead-through current from running.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a semiconductor integrated circuit capable of efficiently performing a failure test on a semiconductor integrated circuit having a tri-state element.

[0002]

2. Description of the Related Art In a failure test of a semiconductor integrated circuit including a tri-state element, when a failure occurs, particularly when the failure is a failure related to a control signal of the tri-state element, a failure state in a bus signal becomes high impedance,
Alternatively, there is no assurance that a logical value becomes an undefined state due to collision of signals output from a plurality of tri-state elements and a logical value different from a normal value surely appears at an observation point for detecting a failure.

For example, in the circuit of FIG. 22, if there is a "0" stuck-at fault at the control terminal C of the tri-state element 3005, "1" is applied to the terminal C of the tri-state element 3005 to check for this fault. A test pattern is required. At this time, “0” is applied to the control terminal C of the tri-state element 3006.

At this time, in a normal circuit, the bus signal line 30
07 has the same logical value as the logical value of the terminal A of the tri-state element 3005.

On the other hand, if there is a failure, the bus signal line 3
007 becomes high impedance and becomes unstable as a logical value.

When such a test pattern is used,
Since it is logically unstable, it is unclear whether or not an expected value is recognized as an error in a failure test by a tester. For this reason, a test pattern having a similar state for a certain number of times or more is prepared, and if no error is found with respect to the expected value in all states, it has been determined that there is no failure in that part in a pseudo manner.

In the case of a test using a sequential test pattern, if a failure state is simulated assuming that the bus signal line holds the previous value, the bus signal line is logically determined. It is possible to detect a fault condition that clearly does not match the normal value at the observation point,
When the scan test is used, since the test is performed only in one clock cycle, the state before the bus signal line cannot be determined, and as a result, a failure state cannot be reliably detected.

[0008] Therefore, a circuit has been added for pulling up or pulling down a bus signal line to determine a logical value when all the tri-state elements are brought into a high impedance state in a fault state. .

[0009]

However, since the bus signal lines are pulled up or pulled down, a through current flows through the bus signal lines even in a steady state, which causes an increase in power consumption.

[0010] Further, since the current always flows, there is another problem that the Iddq test for judging the presence or absence of a failure cannot be performed based on the current amount in a steady state.

Furthermore, if the pull-up circuit and the pull-down circuit are deleted to reduce power consumption, a fault can be detected only in a pseudo manner.

In addition, there is also a problem that only the failure in which the logic value according to the failure state becomes one of the logic values “0” and “1” can be detected by constantly pulling up or pulling down.

SUMMARY OF THE INVENTION The present invention has been made in view of the foregoing, and an object of the present invention is to provide a semiconductor integrated circuit having a high tri-state element failure detection rate while suppressing an increase in power consumption.

[0014]

In order to solve the above-mentioned problems, the present invention employs a configuration in which a bus signal line is pulled up or down only during a scan test.

Specifically, the semiconductor integrated circuit according to the first aspect of the present invention is a semiconductor integrated circuit having a tri-state element, wherein outputs of one or more of the tri-state elements are connected. A bus signal line, a test mode signal indicating that a test is being performed, and a bus signal auxiliary circuit having a bus connection terminal whose electrical state is determined by the test mode signal; A connection terminal is connected to the bus signal line.

According to a second aspect of the present invention, in the semiconductor integrated circuit according to the first aspect, the test mode signal is a scan mode signal indicating that a scan test is being performed.

According to a third aspect of the present invention, in the semiconductor integrated circuit according to the second aspect, the bus signal auxiliary circuit comprises:
The bus connection terminal is pulled up during a scan test in which a scan mode signal is output, and the bus connection terminal is set to a high impedance when not in a scan test in which the scan mode signal is not output.

According to a fourth aspect of the present invention, in the semiconductor integrated circuit of the second aspect, the bus signal auxiliary circuit comprises:
The bus connection terminal is pulled down during a scan test in which a scan mode signal is output, and the bus connection terminal is set to high impedance in a scan test in which the scan mode signal is not output.

According to a fifth aspect of the present invention, in the semiconductor integrated circuit of the second aspect, the bus signal auxiliary circuit comprises:
When a scan test in which a scan mode signal is output is being performed, a bus connection terminal is pulled up, and a holding circuit is provided. And outputting the same logical value as the logical value of the bus signal line determined from the bus connection terminal with a driving capability weaker than the driving capability of the output unit of the tri-state element.

According to a sixth aspect of the present invention, in the semiconductor integrated circuit of the second aspect, the bus signal auxiliary circuit comprises:
When the scan mode signal is being output, the bus connection terminal is pulled down when the scan test is being performed, and a holding circuit is provided.When the scan mode signal is not output and the scan test is not being performed, the holding circuit is provided with a tri-state element. A logical value equal to the determined logical value of the bus signal line is output from the bus connection terminal with a driving capability weaker than the driving capability of the output unit of the tri-state element.

According to a seventh aspect of the present invention, in the semiconductor integrated circuit of the second aspect, a shift mode signal indicating that a shift operation of the scan test is being performed, and a shift of the scan test in which the shift mode signal is output. A tri-state control circuit that controls the tri-state element so that the output of the tri-state element becomes high impedance based on the shift mode signal during operation.

According to an eighth aspect of the present invention, in the semiconductor integrated circuit according to the second aspect, the bus signal auxiliary circuit is configured such that the bus connection terminal is controlled by a bus signal auxiliary circuit control signal in addition to the scan mode signal. The electrical state of the bus connection terminal is switched to pull-up or pull-down by the bus signal auxiliary circuit control signal during the scan test in which the electrical state is determined and the scan mode signal is output. And

According to a ninth aspect of the present invention, in the semiconductor integrated circuit of the eighth aspect, the bus signal auxiliary circuit comprises:
A holding circuit that, when not in a scan test in which the scan mode signal is not output, outputs the same logical value as the logical value of the bus signal line determined by the tri-state element from the bus connection terminal to the It is characterized in that the output is performed with a driving capability weaker than the driving capability of the output section of the tristate element.

According to a tenth aspect of the present invention, in the semiconductor integrated circuit according to the eighth aspect, a flip-flop for outputting the bus signal auxiliary circuit control signal is provided, and the flip-flop is arranged on a scan chain. Features.

A semiconductor integrated circuit according to an eleventh aspect of the present invention is a semiconductor integrated circuit having a tri-state element, wherein a bus signal line to which an output of one or more of the tri-state elements is connected. , A test mode signal indicating that a test is being performed, an Iddq test mode signal indicating that an Iddq test is being performed, and a bus connection terminal whose electrical state is determined by the test mode signal and the Iddq test mode signal. A bus signal auxiliary circuit, wherein a bus connection terminal of the bus signal auxiliary circuit is connected to the bus signal line.

According to a twelfth aspect of the present invention, there is provided the twelfth aspect.
In the described semiconductor integrated circuit, the test mode signal is
A scan mode signal indicating that a scan test is being performed.

The invention according to claim 13 is the invention according to claim 12.
3. The semiconductor integrated circuit according to claim 2, wherein the bus signal auxiliary circuit pulls up the bus connection terminal during a scan test in which the scan mode signal is output and in an Iddq test in which the Iddq test mode signal is not output. The bus connection terminal may be set to a high impedance when the scan mode signal is not output and the scan test is not being performed, or when the Iddq test mode signal is output and the Iddq test is being performed.

The invention according to claim 14 is the invention according to claim 12.
In the semiconductor integrated circuit according to the aspect, the bus signal auxiliary circuit pulls down the bus connection terminal during a scan test in which the scan mode signal is output and when not in an Iddq test in which the Iddq test mode signal is not output, The bus connection terminal is set to a high impedance when the scan mode signal is not output and the scan test is not being performed, or when the Iddq test mode signal is output and the Iddq test is being performed.

The invention according to claim 15 is the invention according to claim 12.
In the semiconductor integrated circuit described in the above, the bus signal auxiliary circuit has a holding circuit, and this holding circuit is not in a scan test in which the scan mode signal is not output,
Id not outputting the Iddq test mode signal
When the dq test is not being performed, the same logical value as the logical value of the bus signal line determined by the tri-state element is output from the bus connection terminal with a driving capability weaker than the driving capability of the output unit of the tri-state element. It is characterized by.

With the above arrangement, according to the first to tenth aspects of the present invention, even when the control signal of the tri-state element becomes a logical value "0" due to a failure and the bus signal line becomes high impedance, the scan signal can be changed. At the time of the test, the bus signal line is pulled up or down by the bus signal auxiliary circuit, and the logical value of this bus signal line is determined to be "1" or "0". It becomes possible. At times other than the scan test, the bus connection terminal of the bus signal auxiliary circuit has a high impedance, so that it is possible to prevent a through current from flowing.

In particular, in the present invention, a plurality of tri-state elements are prevented from outputting logically different outputs during the shift operation of the scan test by the tri-state control circuit. It is possible to prevent a current from flowing and to prevent an increase in power consumption.

In the invention according to claims 8 to 10, the bus signal auxiliary circuit is provided even when the control signal of the tristate element becomes a logical value "0" due to a fault and the bus signal line becomes high impedance. Thereby, the logical value of the bus signal line can be determined to be “0” or “1”. At this time, the logical value of the bus signal line in the normal state can be set to the opposite logical value by the bus signal auxiliary circuit control signal. It is possible to set the logical value of the bus signal line in the state different from the normal value. As a result, the failure detection rate can be improved. Also, except during the scan test,
Since the bus connection terminal of the bus signal auxiliary circuit has a high impedance, a through current can be prevented from flowing, and an increase in power consumption can be suppressed.

In particular, according to the tenth aspect of the present invention, since the flip-flop for outputting the bus signal auxiliary circuit control signal is arranged on the scan chain, the bus signal auxiliary circuit control signal is scanned in the same manner as other scan test patterns. It can be set by the shift operation of the test.
Therefore, it is easy to set the bus signal auxiliary circuit control signal according to each test pattern, and it is possible to reduce the number of bus signal auxiliary circuit control signal generation circuits.

According to the present invention, when a circuit state for an Iddq test is set by using a scan test, an Iddq test mode signal is used to set a bus connection terminal of a bus signal auxiliary circuit. Because the electrical state of can be changed to high impedance,
The Iddq test can be performed by forcibly stopping the through current generated during the scan test.

[0035]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) First, a first embodiment will be described with reference to FIGS.

FIG. 1 is a diagram showing a circuit configuration of a semiconductor integrated circuit according to the first embodiment. In FIG. 1, 14
Reference numerals 1 and 142 denote tri-state elements, and 111 and 11
2 is a control signal for the tri-state elements 141 and 142, respectively, and 101 and 102 are data input signals for the tri-state elements, respectively.

Reference numeral 121 denotes a scan mode signal indicating that a scan test is being performed. Reference numeral 130 denotes a bus signal line to which the outputs of the tri-state elements 141 and 142 are connected. Reference numeral 160 denotes a bus signal auxiliary circuit. The bus signal auxiliary circuit 160 has a bus connection terminal 161 whose electrical state is determined by the scan mode signal.

FIG. 2 is a diagram showing a circuit configuration of the bus signal auxiliary circuit 160 according to the first embodiment. 1, reference numeral 201 denotes a scan mode signal; 202, a bus connection terminal; 203, a logic inversion element; and 204, a tri-state element 141 or 142 in FIG. 1 which is turned on when the logic of the gate is "0". Are smaller in size than the transistors in the output section. 205 is a power supply. 203, 204 and 205 constitute a pull-up element.

Next, the operation of the semiconductor integrated circuit of this embodiment will be described.

At the time of a scan test, the scan test mode signal has a logical value "1", and other than at the time of the scan test, the scan mode signal has a logical value "0". The bus connection terminal 202 of the bus signal auxiliary circuit 160 is pulled up at the time of the scan test, and becomes high impedance except at the time of the scan test.

Except during the scan test, the bus signal line 1
Numeral 30 determines its logical value only by the outputs of the tri-state elements 141 and 142.

At the time of the scan test, if there is an output whose impedance is lower than that of the tri-state elements 141 and 142, the transistor size of the tri-state element is larger than the transistor size of the pull-up element of the bus signal auxiliary circuit. The logic value depends on the output of the tri-state element.

When both the tri-state elements 141 and 142 output high impedance, the bus signal line 13
The logical value of 0 becomes the logical value “1” by the pull-up of the bus connection terminal 202 of the bus signal auxiliary circuit 160.

Next, a case where a failure has occurred will be described. Control terminal of tri-state element 141 is "0"
When the stuck-at fault occurs, the logical value of the control terminal of the tri-state element 141 is set to “1”,
The logical value of the control terminal of the tristate element 14 is “0”.
When a test pattern is input such that the logical value of the data input terminal of the data input terminal 1 is "0", the logical value of the bus signal line 130 becomes "0" when there is no failure. The value becomes “1”. The difference between the normal state and the failure state in the bus signal line 130 is such that the difference in the bus signal line 130 is transmitted to the flip-flop via the intermediate circuit to the flip-flop using the logic of the bus signal line 130. The failure is detected at the time of inspection by using the test pattern.

When the test pattern is used, a through current path is generated by a pull-up element and a tri-state element in a normal circuit during a scan test. However, even in the same circuit state, the pull-up element does not operate except during the scan test. Therefore, a through current path does not occur and power consumption can be suppressed.

FIG. 3 is a diagram showing a different circuit configuration of the bus signal auxiliary circuit 160 'according to the first embodiment. In the figure, reference numeral 301 denotes a scan mode signal;
Is a bus connection terminal, and 304 is a tri-state element 14 which is turned on when the logic value of the gate is "1".
The transistor is smaller in size than the transistors 1 and 142.
305 is a ground. 304 and 305 constitute a pull-down element.

When this circuit configuration is used, when both the tri-state elements 141 and 142 output high impedance during the scan test, the bus signal line 130 has a logical value "0".

As described above, the tri-state element 141
, The logic value of the control terminal of the tri-state element 141 is “1”, the logic value of the control terminal of the tri-state element 142 is “0”, When a test pattern is input so that the logical value of the data input terminal is “1”, the bus signal line 130 has a logical value “1” when there is no failure, whereas the logical value “ 0 ", and the failure can be reliably inspected in the same manner as described above.

FIG. 4 shows a first embodiment in which, as shown in FIG. 23, a holding circuit 3010 having a function of holding a value immediately before the bus signal line becomes high impedance when the bus signal line is high impedance is provided. Bus signal auxiliary circuit 1 according to
FIG. 50 is a diagram showing a different circuit configuration of the embodiment shown in FIG.

Reference numeral 401 denotes a scan mode signal.
2 is a bus connection terminal, 403 is a logic inversion element, 404 is a transistor smaller in size than a tri-state element which becomes conductive when the logic value of the gate is "0", and 405 is a power supply. Reference numeral 406 denotes a tri-state element having a smaller transistor size than the tri-state elements 141 and 142, and reference numeral 407 denotes a logic inversion element. The transistor 404 and the power supply 405 form a pull-up element. Further, the holding circuit that re-outputs the value of the bus signal line is configured by the tri-state element 406 and the logical inversion element 407. By controlling the tri-state element 406 with the scan mode signal 401, the logical value of the bus signal line 130 is re-output from the bus connection terminal 402 only during a scan test, and the tri-state elements 141 and 142 become high impedance. The function has a function of retaining the logical value of the bus signal line 130 even when the signal is transmitted.

By using this circuit configuration, the same effects as those of the circuit configuration of FIG. 2 can be obtained at the time of a scan test, and the tri-state elements 141 and 14 can be used at times other than the scan test.
When both become high-impedance, the bus signal line 130 becomes high-impedance, which can prevent a through current path from occurring.

FIG. 5 shows a first embodiment in which the bus signal line has a holding circuit 3010 having a function of holding a value immediately before the bus signal line becomes high impedance as shown in FIG. Such a bus signal auxiliary circuit 1
FIG. 50 is a diagram showing a different circuit configuration of the circuit diagram of FIG.

Reference numeral 501 denotes a scan mode signal.
Numeral 2 is a bus connection terminal, 503 is an inverted logic element, 504 is a transistor which becomes conductive when the logic value of the gate is "1" and is smaller in size than the tri-state elements 141 and 142. Is ground. Reference numeral 506 denotes the tri-state elements 141 and 142
A tri-state element 507 having a smaller transistor size than that of the transistor 507 is a logic inversion element. A pull-down element is constituted by 504 and 505. The tristate element 506 and the logic inversion element 507 constitute a holding circuit for re-outputting the value of the bus signal line. By controlling the tri-state element 506 with the scan mode signal 501, the logical value of the bus signal line 130 is re-output from the bus connection terminal 502 only at the time other than the scan test,
It has a function of retaining the logical value of the bus signal line 130 even when the tri-state elements 141 and 142 become high impedance.

By using this circuit configuration, the same effects as those of the circuit configuration of FIG. 3 can be obtained at the time of a scan test, and the tri-state elements 141 and 142 can be used at times other than the scan test.
When both become high impedance, the bus signal line 1
30 becomes high impedance, and it is possible to prevent a through current path from being caused.

(Second Embodiment) Next, a second embodiment will be described with reference to FIG.

FIG. 6 is a diagram showing a circuit configuration of a semiconductor integrated circuit according to the second embodiment. In FIG. 6, 64
1, 642 are tri-state elements;
Reference numeral 2 denotes a control signal during normal operation of the tri-state elements 641 and 642, which are not involved in the scan test.
Reference numerals 1 and 602 denote data input signals of the tri-state element, respectively.

Reference numeral 621 denotes a scan mode signal indicating that a scan test is being performed, and 622 is a shift mode signal indicating that a shift operation is being performed in the scan test. 630 is a tri-state element 64
1 and 642 are bus signal lines to which outputs are connected.
0 is a bus signal auxiliary circuit.
60 has a bus connection terminal 661 whose electrical state is determined by the scan mode signal. In addition, 651,
Reference numeral 652 denotes a tri-state control circuit that controls a control signal of the tri-state elements 641 and 642 by a shift mode signal.

FIG. 7 shows a circuit configuration of the tri-state control circuits 651 and 652 according to the second embodiment. FIG.
In the figure, 703 is a shift mode signal, 704 is a control signal during normal operation of the tristate element not involved in the scan test, and 705 is a generated control signal of the tristate element. 701 is a logic inversion element, 702
Is an AND element.

When this circuit configuration is used, the tristate control signal 705 becomes
The logical value is "0" regardless of the value of the control signal 704, and the output of the tri-state element controlled by the tri-state control signal 705 becomes high impedance.

With the circuit configurations shown in FIGS. 6 and 7, in addition to the effects of the first embodiment, all the tri-state elements connected to the bus signal line 630 have a high impedance output during the shift operation in the scan test. Therefore, it is possible to prevent a through current from flowing due to a signal collision between the outputs of the plurality of tri-state elements on the bus signal line 630 during the shift operation.

Since the bus connection terminal of the bus signal auxiliary circuit 660 is pulled up or pulled down during the scan test, the bus signal line 630 does not become high impedance and the bus signal line 630 becomes high impedance. Therefore, it is possible to prevent a through current from being generated.

(Third Embodiment) Next, a third embodiment will be described with reference to FIGS.

FIG. 8 shows a circuit configuration of a semiconductor integrated circuit according to the third embodiment. In FIG. 8, 841, 842
Is a tri-state element, and 811 and 812 are control signals for the tri-state elements 841 and 842, respectively.
01 and 802 are data input signals of the tri-state element, respectively.

Reference numeral 821 is a scan mode signal indicating that a scan test is being performed, 830 is a bus signal line to which the outputs of the tri-state elements 841 and 842 are connected, 860 is a bus signal auxiliary circuit, and 870 is a bus signal auxiliary circuit. , A bus signal auxiliary circuit control signal relating to the operation of a bus connection terminal (described later) of the bus signal auxiliary circuit 860. The bus signal auxiliary circuit 860 has a bus connection terminal 861 whose electrical state is determined by the scan mode signal 821 and the bus signal auxiliary circuit control signal 870.

FIG. 9 shows an internal configuration of a bus signal auxiliary circuit 860 according to the third embodiment. In FIG. 9, 90
1 is a scan mode signal, 902 is a bus connection terminal, and 903 is a bus signal auxiliary circuit control signal. 9
04 and 906 are logical inversion elements, and 905 and 907 are logical AND elements. Reference numeral 908 denotes a pull-up element which is turned on when the logic value of the gate terminal is “0” and is formed of a transistor smaller in size than the tri-state elements 841 and 842 in FIG. Reference numeral 909 denotes a pull-down element which is turned on when the logic value of the gate terminal is "1" and is composed of a transistor smaller in size than the tri-state elements 841 and 842 in FIG.

Next, the operation of the semiconductor integrated circuit of this embodiment will be described.

At the time of the scan test, the scan mode signal 901 has a logical value "1", and other than at the time of the scan test, the scan mode signal has a logical value "0". The bus connection terminal 902 of the bus signal auxiliary circuit 860 has a high impedance except during the scan test. In the scan test, when the bus signal auxiliary circuit control signal 903 has a logical value “1”, the bus connection terminal 902 is pulled down. When the logical value 903 is “0”, the pull-up is performed. Except during the scan test, the bus signal line 830 is
The logic value is determined only by the outputs of the tri-state elements 841 and 842.

At the time of the scan test, if there is an output having a higher impedance than the tri-state elements 841 and 842, the transistor size of the tri-state element is larger than the transistor size of the pull-up element and the pull-down element of the bus signal auxiliary circuit 860. The logical value of the bus signal line 830 depends on the output of the tri-state element.

When the outputs of the tri-state elements 841 and 842 both become high impedance, the bus signal line 8
The logical value of 30 depends on the operation of the bus connection terminal 903 of the bus signal auxiliary circuit 860, and the bus signal auxiliary circuit control signal 903
Is a logical value "1" by the pull-up element when the logical value is "0", and becomes a logical value "0" by the pull-down element when the bus signal auxiliary circuit control signal 903 is the logical value "0".

Next, a case where a failure has occurred will be described. Control terminal of tri-state element 841 is “0”
When the stuck-at fault occurs, the logical value of the control terminal of the tri-state element 841 is “1”, the logical value of the control terminal of the tri-state element 842 is “0”, and the tri-state element 841
To make the logical value of the data input terminal 801 “0” and the logical value of the bus signal auxiliary circuit control signal 903 “0”.
When the test pattern is input, the bus signal line 830
When there is no failure, the logic value is "0", whereas when there is a failure, the logic value is "1". The difference between the normal state and the fault state in the bus signal line 830 is such that the difference in the bus signal line 830 is transmitted to the flip-flop using the logic of the bus signal line 830 to the flip-flop via an intermediate circuit. By using a test pattern, a failure is detected during a test.

When the test pattern is used, a through current path is generated by the pull-up element and the tri-state element in the normal circuit at the time of the scan test. Since it does not operate, a through current path does not occur, and power consumption can be suppressed.

Further, even when the logical value of the data input terminal 801 of the tri-state element 841 is "1", when a test pattern is input so that the logical value of the bus signal auxiliary circuit control signal 903 is "1", The bus signal line 830 has a logical value "1" when there is no failure, and has a logical value "0" when there is a failure.

That is, in the third embodiment, in addition to the effects of the first embodiment, the logical value of the data input terminal of the tristate element is changed to either logical value “0” or logical value “1”. Without limitation, by operating the bus signal auxiliary circuit control signal 903, a fault can be detected, so that an effect of facilitating the creation of a test pattern can be obtained, and the fault detection rate can be improved. .

In the present embodiment, the circuit configuration is such that when the logical value of the bus signal auxiliary circuit control signal 903 is "1", it is pulled down, and when the logical value is "0", it is pulled up. Even if the relationship between the logical value of the bus signal auxiliary circuit control signal 903 and the pull-up and pull-down is different, the same effect can be obtained if the selection can be made uniquely.

FIG. 10 shows a third embodiment in which, as shown in FIG. 23, when the bus signal line has a holding circuit 3010 having a function of holding the value immediately before the bus signal line becomes high impedance when the bus signal line becomes high impedance. FIG. 16 is a diagram showing a different circuit configuration of a bus signal auxiliary circuit 860 ′ according to the embodiment.

In the figure, reference numeral 1001 denotes a scan mode signal; 1002, a bus connection terminal;
Is a bus signal auxiliary circuit control signal. 1004, 100
6, 1008 and 1010 are logic inversion elements, and 100
Reference numerals 5 and 1007 denote AND elements, and reference numeral 1009 denotes a tri-state element formed of a transistor having a size smaller than that of the transistors forming the output units of the tri-state elements 841 and 842 in FIG.

Reference numeral 1012 denotes a conductive state when the logic value of the gate is "1", and the tri-state element 84 shown in FIG.
1, 842 are transistors smaller in size than the transistors forming the output section, and 1014 is ground. The transistor 1012 and the ground 1014 form a pull-down element.

Reference numeral 1011 denotes a transistor which becomes conductive when the logic value of the gate is "0", and is smaller in size than the transistors constituting the output portions of the tri-state elements 841 and 842 in FIG. 1013 is a power supply. The transistor 1011 and the power supply 101
3 constitutes a pull-up element.

The holding circuit for re-outputting the value of the bus signal line 830 is constituted by the tri-state element 1009 and the logical inversion element 1010. Tri-state element 100
9 by the scan mode signal 1001 so that the bus connection terminals 1002
Has the function of re-outputting the logical value of the bus signal line 830 from the device and retaining the logical value of the bus signal line 830 even when the tri-state elements 841 and 842 become high impedance.

By using this circuit configuration, at the time of the scan test, the same effect as that of the circuit configuration of FIG. 9 can be obtained.
When both become high impedance, the bus signal line 830 becomes high impedance, which can prevent a through current path from being caused.

This embodiment has the following advantages over the first embodiment. That is, in general, a fault relating to a data input signal and an output signal of a tri-state element can be detected in the same manner as in a normal circuit. Conventionally, a failure relating to a control signal of a tri-state element cannot be detected. Therefore, if the data signal of the tri-state element targeted for failure can be set freely, the first
The problem can be solved by the pull-up or pull-down circuit configuration described in the embodiment. On the other hand, as shown in FIG. 25, when the input of the tri-state element is fixed to the power supply or the ground and the data signal of the tri-state element cannot be freely set, the failure of the control unit of the tri-state element is detected. In order to achieve this, the problem can be solved by using a circuit configuration capable of controlling pull-down and pull-up as in this embodiment.

(Fourth Embodiment) Next, a fourth embodiment will be described with reference to FIG.

FIG. 11 shows a circuit configuration of a semiconductor integrated circuit according to the fourth embodiment. In FIG. 11, 114
1, 1142 are tri-state elements;
Reference numerals 1112 denote tri-state elements 1141 and 1142, respectively.
, And 1101 and 1102 are data input signals of the tri-state elements, respectively. Reference numeral 1121 denotes a scan mode signal indicating that a scan test is being performed. Reference numeral 1122 denotes a shift mode signal indicating that a shift operation is being performed in the scan test. Reference numeral 1130 denotes an output of the tri-state elements 1141 and 1142. A bus signal line; 1160, a bus signal auxiliary circuit;
Reference numeral 1170 denotes a bus signal auxiliary circuit control signal related to the operation of a bus connection terminal (described later) of the bus signal auxiliary circuit 1160. The bus signal auxiliary circuit 1160 includes a scan mode signal 1121 and a bus signal auxiliary circuit control signal 1170.
Bus connection terminal 1161 whose electrical state is determined by
have.

Reference numeral 1171 denotes a flip-flop for outputting a bus signal auxiliary circuit control signal 1170. The flip-flop 1171 includes a normal data input terminal D, a scan data input terminal DT, an input data switching terminal NT, a clock terminal CK, and an output terminal Q.
When the input data switching terminal NT has the logical value “0”, the normal data input is selected, and when the logical value is “1”, the scan data is selected. Normally, the input terminal is connected to the output terminal,
Input data switching terminal NT is connected to a shift mode signal.

Further, reference numerals 1181 and 1182 denote signal lines constituting a part of the scan chain.
Is connected to the output terminal of the preceding flip-flop on the scan chain, and the signal line 1182 is connected to the scan-in terminal of the subsequent flip-flop on the scan chain. As the bus signal auxiliary circuit 1160, the circuit having the internal configuration shown in FIG. 9 or FIG. 10 described in the third embodiment is used.

Next, the operation of the semiconductor integrated circuit of this embodiment will be described.

To create a test pattern for detecting a stuck-at-0 fault related to the tristate control signal 1111, first, a logical value “1” is applied to the tristate control signal 1111 and the tristate control signal 1111 is applied.
A test pattern is created so that a logical value “0” is applied to the reference numeral 12.

Next, when the data signal 1101 has a logical value “0” according to the test pattern, the bus signal auxiliary circuit control signal 1170 and the terminal 1161 are pulled to detect the failure of the tristate control signal 1111. The logic must be up. When the bus signal auxiliary circuit shown in FIG. 9 is used, the bus signal auxiliary circuit control signal 117
0 is a logical value “0”.

In order to realize the above control, the logical value “0” is set to the bus signal auxiliary circuit control signal flip-flop 1171 by a shift operation. Since the value of the flip-flop 1171 is not used except during the scan test, the logical value may be either “0” or “1” except during the scan test.

(Fifth Embodiment) Next, a fifth embodiment will be described with reference to FIGS.

FIG. 12 shows a circuit configuration of a semiconductor integrated circuit according to the fifth embodiment. In FIG. 12, 1241,
Reference numeral 1242 denotes a tri-state element.
Reference numeral 12 denotes a control signal during normal operation of the tri-state elements 1241 and 1242, and reference numerals 1201 and 1202 denote data input signals of the tri-state elements. 125
Reference numerals 1 and 1252 denote tristate control circuits for operating a control signal of the tristate element by a shift mode signal, and have an internal configuration shown in FIG.

Reference numeral 1221 denotes a scan mode signal indicating that a scan test is being performed. Reference numeral 1222 denotes a shift mode signal indicating that a scan test shift operation is being performed.
242 is a bus signal line to which the output is connected, and 1260
Is a bus signal auxiliary circuit, and 1270 is a bus signal auxiliary circuit control signal related to the operation of a bus connection terminal (described later) of the bus signal auxiliary circuit 1260. The bus signal auxiliary circuit 1260 has a bus connection terminal 1261 whose electrical state is determined by the scan mode signal 1221 and the bus signal auxiliary circuit control signal 1270.

1271 is a bus signal auxiliary circuit control signal 1
270, which has a normal data input terminal D, a scan data input terminal DT, an input data switching terminal NT, a clock terminal CK, and an output terminal Q. The input data switching terminal NT has a logical value "0". At this time, the normal data input is selected, and when the logical value is "1", the scan data is selected. Usually, the input terminal is connected to the output terminal, and the input data switching terminal NT is connected to the shift mode signal.

Reference numerals 1281 and 1282 denote signal lines constituting a part of the scan chain. The signal line 1281 is connected to the output terminal of the preceding flip-flop on the scan chain, and the signal line 1282 is connected to the subsequent flip-flop on the scan chain. Connected to the scan-in terminal of the

FIG. 13 shows the internal configuration of a bus signal auxiliary circuit 1260 according to the fifth embodiment. In FIG. 13, reference numeral 1301 denotes a scan mode signal, 1302 denotes a bus connection terminal, 1303 denotes a bus signal auxiliary circuit control signal, and 1304 denotes a shift mode signal. 1
305, 1308, 1309 are logical inversion elements, 130
6 and 1310 are AND elements, and 1307 is an OR element.

Reference numeral 1311 indicates that the logical value of the gate terminal is "0"
And a pull-up element formed of a transistor smaller in size than the transistors constituting the output portions of the tri-state elements 1241 and 1242 in FIG. Reference numeral 1312 denotes a pull-down element which is turned on when the logic value of the gate terminal is "1" and is made of a transistor smaller in size than the transistor constituting the output part of the tri-state element in FIG.

According to the fifth embodiment, in addition to the operation of the fourth embodiment, the output of the tri-state element is fixed at a high impedance during the shift operation of the scan test, and the bus signal auxiliary circuit 1260 The operation of the bus connection terminal 1302 is also controlled by the bus signal auxiliary circuit control signal 1
It is fixed regardless of the value of 303.

As a result, in the present embodiment, the state of the bus connection terminal 1302 of the bus signal auxiliary circuit 1260 changes during the shift operation even if the value of the flip-flop 1271 for outputting the bus signal auxiliary circuit control signal frequently changes. Since there is no change, an effect is obtained that unnecessary current can be prevented from flowing.

(Sixth Embodiment) Next, a sixth embodiment will be described with reference to FIGS.

FIG. 14 shows a circuit configuration of a semiconductor integrated circuit according to the sixth embodiment. In FIG. 14, 144
1, 1442 are tri-state elements;
1412 are tri-state elements 1441 and 1442, respectively.
, And 1401 and 1402 are data input signals of the tri-state element. Reference numeral 1421 denotes a scan mode signal indicating that a scan test is being performed. Reference numeral 1430 denotes tri-state elements 1441 and 1442.
Is a bus signal line to which the output is connected, 1460 is a bus signal auxiliary circuit, and 1423 is an Iddq test mode signal indicating that an Iddq test is being performed. The bus signal auxiliary circuit 1460 controls the scan mode signal 1
241 and an Iddq test mode signal 1423 to determine an electrical state.

FIG. 15 shows an internal configuration of a bus signal auxiliary circuit 1460 according to the sixth embodiment. In FIG. 15, reference numeral 1501 denotes a scan mode signal;
Is a bus connection terminal, and 1503 is an Iddq test mode signal. Reference numeral 1504 denotes a pull-up element which is turned on when the logic value of the gate terminal is "0" and is smaller in size than the transistors forming the output units of the tri-state elements 1441 and 1442 in FIG. . 1505 is a power supply. 1506
Is a logical inversion element, and 1507 is a logical sum element.

Next, the operation of the circuit of this embodiment will be described.

At the time of the scan test, the scan mode signal has a logical value “1”, and other than at the time of the scan test, the scan mode signal has a logical value “0”. The bus connection terminal 1502 of the bus signal auxiliary circuit 1460 has a high impedance except during the scan test, has a high impedance during the Iddq test mode even during the scan test, and is pulled up when not in the Iddq test mode.

Next, a case where a failure has occurred will be described.

When the control terminal of tri-state element 1541 has a stuck-at fault of “0”, the control terminal of tri-state element 1541 has a logical value of “1” and the control terminal of tri-state element 1542 has a logical value of “1” during the Iddq test. When a test pattern is input so that the logic value is “0” and the data input terminal of the tri-state element 1541 has a logic value “0”, the bus signal line 1530 determines the logic value “0” when there is no failure. If there is a failure, the impedance becomes high. As a result, a through current flows in the cell connected to the input terminal to the bus signal line 1530, and a failure is detected.

In the present embodiment, in a normal scan test, the Iddq test mode becomes “0” as a logical value, and the same effect as in the first embodiment can be obtained. Further, in the Iddq test, high impedance due to a failure can be detected.

The operation of the bus signal auxiliary circuit according to the present invention is as follows.
The scan test mode does not depend on operations other than those in the Iddq test mode. Therefore, the same effect can be obtained by making a change equivalent to that of the present embodiment to the circuit configuration for performing the operations of FIGS. 3 to 5 shown in the first embodiment. The bus signal auxiliary circuit 1460 'in this case
To 1460 '''are shown in FIGS.

In FIG. 16, reference numeral 1601 denotes a scan mode signal; 1602, a bus connection terminal;
03 is an Iddq test mode signal. Reference numeral 1604 denotes a pull-down element which is turned on when the logic value of the gate terminal is "1" and is made of a transistor smaller in size than the transistor constituting the output part of the tri-state element in FIG. Reference numeral 1605 denotes a ground. 1606 is a logical inversion element and 1607 is a logical product element.

In FIG. 17, reference numeral 1701 denotes a scan mode signal, 1702 denotes a bus connection terminal, and 1703 denotes an Iddq test mode signal. 17
Reference numeral 04 denotes a pull-up element which is made conductive when the logic value of the gate terminal is "0" and is smaller in size than the transistor constituting the output part of the tri-state element in FIG. 1705 is a power supply, 170
Reference numerals 6 and 1709 denote logical inversion elements, and reference numeral 1707 denotes a logical sum element. Reference numeral 1708 denotes a tri-state element composed of a transistor smaller in size than the transistor constituting the output section of the tri-state element in FIG.

In addition, in FIG. 18, 1801 is a scan mode signal, 1802 is a bus connection terminal, and 1803 is an Iddq test mode signal. 18
Reference numeral 04 denotes a pull-down element which is turned on when the logic value of the gate terminal is "1" and is made of a transistor smaller in size than the transistor constituting the output part of the tri-state element in FIG. 1805 is ground, 180
6, 1808 and 1810 are logical inversion elements, and 1807 is a logical AND element. Reference numeral 1709 denotes a tri-state element made of a transistor smaller in size than the transistor forming the output section of the tri-state element in FIG.

(Seventh Embodiment) Next, a seventh embodiment will be described with reference to FIGS.

FIG. 19 shows a circuit configuration of a semiconductor integrated circuit according to the seventh embodiment. In FIG. 19, 1941,
Reference numeral 1942 denotes a tri-state element.
Reference numeral 12 denotes a control signal for the tri-state elements 1941 and 1942, and reference numerals 1901 and 1902 denote data input signals of the tri-state elements. Reference numeral 1921 denotes a scan mode signal indicating that a scan test is being performed; and 1923, Id indicating that an Iddq test is being performed.
A dq test mode signal. Reference numeral 1930 denotes a bus signal line to which outputs of the tri-state elements 1941 and 1942 are connected.

Reference numeral 1960 denotes a bus signal auxiliary circuit.
Reference numeral 70 denotes a bus signal auxiliary circuit control signal related to the operation of a bus connection terminal (described later) of the bus signal auxiliary circuit 1960. The bus signal auxiliary circuit 1960 has a bus connection terminal 1961 whose electrical state is determined by the scan mode signal 1921 and the bus signal auxiliary circuit control signal 1970.

FIG. 20 shows an internal configuration of a bus signal auxiliary circuit 1960 according to the seventh embodiment. In FIG. 20, 2001 is a scan mode signal, 2002 is a bus connection terminal, and 2003 is a bus signal auxiliary circuit control signal. 2012 is an Iddq test mode signal,
2004, 2006, 2013 are logical inversion elements,
5, 2007, 2014 are AND elements. 2008
Are conductive when the logic value of the gate terminal is “0”, and the tri-state elements 1941 and 194 shown in FIG.
This is a pull-up element composed of a transistor having a size smaller than 2. Reference numeral 2009 denotes a pull-down element which is turned on when the logic value of the gate terminal is "1" and is composed of a transistor smaller in size than the tri-state elements 1941 and 1942 in FIG.

Next, the operation of the semiconductor integrated circuit of the present embodiment will be described.

At the time of the scan test, the scan mode signal has a logical value “1”, and other than at the time of the scan test, the scan mode signal has a logical value “0”. Also, Idd
The q test mode signal has a logical value “1” during the Iddq test, and has a logical value “0” except during the Iddq test.

The bus connection terminal 2002 of the bus signal auxiliary circuit 1960 has a high impedance except during the scan test and during the Iddq test, and operates in accordance with the bus signal auxiliary circuit control signal 1970 during the scan test and other than during the Iddq test. Signal auxiliary circuit control signal 1970
Is pulled down when the logical value is “1”, and pulled up when the bus signal auxiliary circuit control signal is the logical value “0”.

In the seventh embodiment, the same operation as in the third embodiment is performed except for the Iddq test, and the same effect is obtained. In addition, when the circuit state for the Iddq test is created by using the shift operation of the scan test, the bus signal auxiliary circuit control signal 1
970, the operation of the bus connection terminal 2002 is invalidated,
By setting the bus connection terminal 2002 to high impedance, the Iddq test can be performed except for the through current generated during the scan test.

FIG. 21 shows a seventh embodiment in which, as shown in FIG. 23, the bus signal line has a holding circuit 3010 having a function of holding a value immediately before high impedance at the time of high impedance. FIG. 21 is a diagram showing a different circuit configuration of a bus signal auxiliary circuit 1960 ′ according to the embodiment.

In the figure, reference numeral 2101 denotes a scan mode signal; 2102, a bus connection terminal;
Is a bus signal auxiliary circuit control signal, and 2115 is Idd
q Test mode signal. 2104, 2106, 21
08, 2110 and 2116 are logic inversion elements,
05, 2107, and 2117 are AND elements;
8 is an OR element. Reference numeral 2109 denotes a tri-state element formed of a transistor having a size smaller than that of the transistors forming the output units of the tri-state elements 1941 and 1942 in FIG. Reference numeral 2112 denotes a transistor which is turned on when the logic value of the gate is "1" and is smaller in size than the transistor constituting the output portion of the tri-state element in FIG. 2114 is a ground. The transistor 2112 and the ground 2114 form a pull-down element.

Reference numeral 2111 denotes a transistor which becomes conductive when the logic value of the gate is "0", and is smaller in size than the transistors constituting the output portions of the tri-state elements 1941 and 1942 in FIG. 21
13 is a power supply. Transistor 2111 and power supply 21
13 constitutes a pull-up element.

Further, the holding circuit for re-outputting the value of the bus signal line 1930 is constituted by the tri-state element 2109 and the logical inversion element 2110. By controlling the tri-state element 2109 with the scan mode signal 2101, the bus connection terminal 2 can be controlled only during the scan test.
The logic value of the bus signal line is re-outputted from 102, and the logic value of the bus signal line 1930 is held even when the tri-state elements 1941 and 1942 become high impedance.

By using this circuit configuration, the same effect as that of the circuit configuration of FIG. 20 can be obtained at the time of the scan test, and the circuit holding the value of the bus signal line is set not to operate at the time of the Iddq test. Therefore, when there is a fault related to the control of the tri-state element, the fault can be detected by the Iddq test.

In the present invention, the circuit configuration of the tri-state element is not limited as long as its output becomes high impedance by a control signal. Therefore, FIG.
The present invention can also obtain the same effect for a selector circuit using a pass transistor as shown in FIG.

[0126]

As described above, according to the semiconductor integrated circuit of the present invention, a bus signal line to which one or more tri-state elements are connected is formed by using a bus signal auxiliary circuit. Since the pull-up or pull-down is performed only during the scan test, the value of the bus signal line can be determined to be “1” or “0” even when the bus signal line has a high impedance due to a failure. Therefore, it is possible to reliably verify the failure of the control terminal of the tri-state element and the failure of the circuit connected to the control terminal, which have been conventionally only simulated. Moreover, since the bus signal lines are set to the high impedance state except during the scan test, it is possible to suppress the flow of the through current and to suppress an increase in power consumption other than during the scan test.

In particular, according to the semiconductor integrated circuit according to the fifth and sixth aspects of the present invention, when all the tri-state elements become high impedance except during the scan test, the electrical state of the bus signal line is changed. Is held at the logic value immediately before by the holding circuit, so that a through current can be prevented from flowing.

Furthermore, according to the semiconductor integrated circuit of the present invention, the control signal of the tri-state element is always set to high impedance in the shift operation in the scan test. It is possible to prevent a plurality of tri-state elements from outputting mutually different logic values.

In addition, according to the semiconductor integrated circuit of the present invention, whether to pull up or pull down the bus signal line at the time of the scan test can be switched by the bus signal auxiliary circuit control signal. Therefore, it is possible to set the logical value of the bus signal line to a logical value different from the normal state when there is a failure, and it is possible to improve the failure detection rate.

In particular, according to the semiconductor integrated circuit of the present invention, the bus signal auxiliary circuit control signal can be set by the shift operation at the time of the scan test. This makes it possible to simplify the circuit configuration and facilitate the creation of scan test patterns.

According to the semiconductor integrated circuit of the present invention, the operation of pulling up or pulling down the bus signal line at the time of the scan test is performed by the I
Since the test is stopped at the time of the ddq test, when the Iddq test is performed by using the scan test, it is possible to suppress the flow of the through current and to perform the Iddq test.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a first example of an internal configuration of the bus signal auxiliary circuit according to the embodiment;

FIG. 3 is a diagram illustrating a second example of the internal configuration of the bus signal auxiliary circuit according to the embodiment;

FIG. 4 is a diagram illustrating a third example of the internal configuration of the bus signal auxiliary circuit according to the embodiment;

FIG. 5 is a diagram illustrating a fourth example of the internal configuration of the bus signal auxiliary circuit according to the embodiment;

FIG. 6 is a diagram showing a configuration of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 7 is a diagram showing an internal configuration of the tri-state control circuit of the embodiment.

FIG. 8 is a diagram illustrating a configuration of a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 9 is a diagram showing a first example of the internal configuration of the bus signal auxiliary circuit of the embodiment.

FIG. 10 is a diagram showing a second example of the internal configuration of the bus signal auxiliary circuit of the embodiment.

FIG. 11 is a diagram illustrating a configuration of a semiconductor integrated circuit according to a fourth embodiment of the present invention.

FIG. 12 is a diagram illustrating a configuration of a semiconductor integrated circuit according to a fifth embodiment of the present invention.

FIG. 13 is a diagram showing an internal configuration of a bus signal auxiliary circuit of the embodiment.

FIG. 14 is a diagram illustrating a configuration of a semiconductor integrated circuit according to a sixth embodiment of the present invention.

FIG. 15 is a diagram showing a first example of the internal configuration of the bus signal auxiliary circuit of the embodiment.

FIG. 16 is a diagram showing a second example of the internal configuration of the bus signal auxiliary circuit of the embodiment.

FIG. 17 is a diagram illustrating a third example of the internal configuration of the bus signal auxiliary circuit according to the embodiment;

FIG. 18 is a diagram illustrating a fourth example of the internal configuration of the bus signal auxiliary circuit according to the embodiment;

FIG. 19 is a diagram showing a configuration of a semiconductor integrated circuit according to a seventh embodiment of the present invention.

FIG. 20 is a diagram showing a first example of the internal configuration of the bus signal auxiliary circuit of the embodiment.

FIG. 21 is a diagram showing a second example of the internal configuration of the bus signal auxiliary circuit of the embodiment.

FIG. 22 is a diagram showing a configuration of a conventional semiconductor integrated circuit.

FIG. 23 is a diagram showing a configuration of a conventional semiconductor integrated circuit having a holding circuit.

FIG. 24 is a diagram illustrating a configuration of a selector circuit using a pass transistor circuit.

FIG. 25 is a diagram showing a configuration of a semiconductor integrated circuit in which an input of a tristate element is fixed to a predetermined logical value

[Explanation of symbols]

130 bus signal line 141, 142 tri-state element 121 scan mode signal 160 bus signal auxiliary circuit 161 bus connection terminal 621 scan mode signal 622 shift mode signal 651, 652 tri-state control circuit 660 bus signal auxiliary circuit 821 scan mode signal 860 bus signal Auxiliary circuit 870 Bus signal auxiliary circuit control signal 1121 Scan mode signal 1122 Shift mode signal 1160 Bus signal auxiliary circuit 1170 Bus signal auxiliary circuit control signal 1171 Flip-flop for bus signal auxiliary circuit control signal 1181, 1182 Scan chain 1221 Scan mode signal 1222 Shift Mode signal 1251, 1252 Tri-state control circuit 1260 Bus signal auxiliary circuit 1270 Bus signal auxiliary circuit control signal 1171 Bus signal auxiliary circuit control signal flip-flops 1281 and 1282 Scan chain 1421 Scan mode signal 1423 Iddq test mode signal 1460 Bus signal auxiliary circuit 1921 Scan mode signal 1923 Iddq test mode signal 1960 Bus signal auxiliary circuit 1970 Bus signal auxiliary circuit control signal

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 21/82 T (72) Inventor Akihiro Yamada 1006 Kazuma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (15)

[Claims] 1. A semiconductor integrated circuit having a tri-state element, comprising: a bus signal line to which an output of one or more of the tri-state elements is connected; and a test mode indicating that a test is being performed. A signal, and a bus signal auxiliary circuit having a bus connection terminal whose electrical state is determined by the test mode signal, wherein a bus connection terminal of the bus signal auxiliary circuit is connected to the bus signal line. Semiconductor integrated circuit. 2. The semiconductor integrated circuit according to claim 1, wherein the test mode signal is a scan mode signal indicating that a scan test is being performed. 3. The bus signal auxiliary circuit pulls up a bus connection terminal during a scan test in which a scan mode signal is output, and connects the bus connection when the scan test in which the scan mode signal is not output is not performed. 3. The semiconductor integrated circuit according to claim 2, wherein the terminal has a high impedance. 4. The bus signal auxiliary circuit pulls down a bus connection terminal during a scan test in which a scan mode signal is output, and the bus connection terminal in a scan test in which the scan mode signal is not output. 3. The semiconductor integrated circuit according to claim 2, wherein is a high impedance. 5. The bus signal auxiliary circuit pulls up a bus connection terminal during a scan test in which a scan mode signal is output, and has a holding circuit. When a scan test is not being performed, the same logical value as the logical value of the bus signal line determined by the tri-state element is output from the bus connection terminal with a driving capability weaker than the driving capability of the output unit of the tri-state element. 3. The semiconductor integrated circuit according to claim 2, wherein the signal is output. 6. The bus signal auxiliary circuit pulls down a bus connection terminal during a scan test in which a scan mode signal is output, and has a holding circuit. When the scan test is not performed, the same logical value as the logical value of the bus signal line determined by the tri-state element is output from the bus connection terminal with a drive capability weaker than the drive capability of the output unit of the tri-state element when the scan test is not being performed. 3. The semiconductor integrated circuit according to claim 2, wherein: 7. A shift mode signal indicating that a shift operation of a scan test is being performed, and an output of a tri-state element based on the shift mode signal during a shift operation of the scan test to which the shift mode signal is output. 3. The semiconductor integrated circuit according to claim 2, further comprising a tri-state control circuit that controls the tri-state element so that the tri-state element has a high impedance. 8. The scan in which the bus connection terminal has an electrical state determined by a bus signal auxiliary circuit control signal in addition to the scan mode signal, and wherein the scan mode signal is output. 3. The semiconductor integrated circuit according to claim 2, wherein an electrical state of the bus connection terminal is switched between pull-up and pull-down according to the bus signal auxiliary circuit control signal during a test. 9. The bus signal auxiliary circuit includes a holding circuit. The holding circuit is configured to store a logical value of a bus signal line determined by a tri-state element when a scan test in which the scan mode signal is not output is not performed. 9. The semiconductor integrated circuit according to claim 8, wherein the same logical value is output from the bus connection terminal with a driving capability weaker than a driving capability of an output unit of the tri-state element. 10. The semiconductor integrated circuit according to claim 8, further comprising a flip-flop that outputs the bus signal auxiliary circuit control signal, wherein the flip-flop is arranged on a scan chain. 11. A semiconductor integrated circuit having a tri-state element, comprising: a bus signal line to which an output of one or more of the tri-state elements is connected; and a test mode indicating that a test is being performed. A signal, an Iddq test mode signal indicating that an Iddq test is being performed, and a bus signal auxiliary circuit having a bus connection terminal whose electrical state is determined by the test mode signal and the Iddq test mode signal. A semiconductor integrated circuit, wherein a bus connection terminal of a bus signal auxiliary circuit is connected to the bus signal line. 12. The semiconductor integrated circuit according to claim 11, wherein the test mode signal is a scan mode signal indicating that a scan test is being performed. 13. The bus signal auxiliary circuit pulls up the bus connection terminal during a scan test in which the scan mode signal is output and when not in an Iddq test in which the Iddq test mode signal is not output. 13. The bus connection terminal is set to high impedance during a scan test in which a scan mode signal is not output or during an Iddq test in which the Iddq test mode signal is output.
A semiconductor integrated circuit as described in the above. 14. The bus signal auxiliary circuit pulls down the bus connection terminal during a scan test in which the scan mode signal is output and not in an Iddq test in which the Iddq test mode signal is not output. 13. The bus connection terminal is set to high impedance during a scan test in which a mode signal is not output or during an Iddq test in which the Iddq test mode signal is output.
A semiconductor integrated circuit as described in the above. 15. The bus signal auxiliary circuit has a holding circuit, which is not in the scan test in which the scan mode signal is not output and in which the Iddq test mode signal is not output.
When the test is not being performed, outputting the same logical value as the logical value of the bus signal line determined by the tri-state element from the bus connection terminal with a driving capability weaker than the driving capability of the output unit of the tri-state element. Claim 1.
3. The semiconductor integrated circuit according to item 2.