JP2004012399A - Flip-flop circuit with scanning function, scanning test circuit, and semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a flip-flop circuit with a scanning function for easily detecting an electrically or physically broken transistor. <P>SOLUTION: If a selecting circuit 3 and a clocked invertor 14 which is a part of a master latch part 13a are composed of a compound element 60 for saving the layout area, a PMOS transistor 2 is provided between an output node 25 of the compound element 60 and a source potential VDD, a controllable TEST signal is inputted to its gate from outside, and the breakage of a NMOS transistor 47 can be detected without controlling the PMOS transistor 40 by the SI signal. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit provided with a flip-flop circuit for transferring serial data and a combination circuit, a flip-flop circuit with a scan function used for a testable design of the semiconductor integrated circuit, and a scan test circuit.
[0002]
[Prior art]
2. Description of the Related Art In recent years, as the circuit scale of a semiconductor integrated circuit increases, the frequency of occurrence of circuit failures tends to increase. In order to prevent such a failure in detecting a circuit failure, it is conceivable to increase the number of test patterns used for the failure inspection. However, increasing the number of test patterns increases the time and cost required for the failure inspection. Therefore, it is not preferable. Therefore, there has been proposed a method of performing design for testability to reduce omission in detection of circuit failure. Introduce a testability design to improve the failure detection rate of the semiconductor integrated circuit under test, reduce the complexity of test patterns and increase the number of patterns, and reduce the time and cost required for failure inspection. This is because it becomes possible.
[0003]
Conventionally, a scan test circuit has been generally used as such a testability design technique. The scan test circuit has a shift register configuration by connecting a plurality of flip-flop circuits with a scan function provided with a scan function to an existing flip-flop circuit. At the time of failure inspection, a scan test signal (scan enable signal) is input, and a signal output through the scan path is detected to test a logic circuit portion (sequential circuit connection) divided by the scan path. Can be.
[0004]
An example of such a flip-flop circuit with a scan function is disclosed in, for example, Japanese Patent Application Laid-Open No. 10-177060. Hereinafter, the configuration and operation of a conventional flip-flop circuit with a scan function will be described.
[0005]
FIG. 3 is a circuit diagram showing a configuration of a conventional flip-flop circuit 300 with a scan function.
[0006]
The flip-flop circuit 300 with a scan function includes a selector circuit 3 and a flip-flop circuit 13 with a reset function.
[0007]
The selector circuit 3 is composed of an inverter circuit 8, AND circuits 10 and 11, and an OR circuit 12, and depends on the value of a scan enable signal SE input to a scan enable terminal (hereinafter, referred to as SE terminal) 5. One of a scan signal SI input from a scan signal input terminal (hereinafter referred to as SI terminal) 4 and a data signal D input from a data signal input terminal (hereinafter referred to as D terminal) 6 is selected, Output.
[0008]
For example, at the time of the scan test, the scan enable signal SE becomes the “high” level, the “high” level is input to one input of the AND circuit 10, and the inverted input is input to the one input of the AND circuit 11 through the inverter circuit 8. The input signal 'low' level is input. Therefore, the scan signal SI, which is an output signal from the AND circuit 10, is input to one input of the OR circuit 12. On the other hand, the “low” level is always output from the AND circuit 11 irrespective of the value of the data signal D and is input to the other input of the OR circuit 12. Therefore, the scan signal SI is output from the OR circuit 12.
[0009]
In the normal operation, the scan enable signal SE is at the “low” level, the “low” level is input to one input of the AND circuit 10, and the inverter circuit 8 is connected to one input of the AND circuit 11 via the inverter circuit 8. The inverted signal 'high' level is input. Therefore, the data signal D which is an output signal from the AND circuit 11 is input to one input of the OR circuit 12. On the other hand, the output from the AND circuit 10 is always low and is input to the other input of the OR circuit 12. Therefore, the data signal D is output from the OR circuit 12.
[0010]
The flip-flop circuit with reset function 13 includes a master latch unit 13a, a slave latch unit 13b, an internal clock generation unit 13c, and four inverter circuits 9 and 20 to 22.
[0011]
The internal clock generator 13c is configured by inverter circuits 27 and 28 connected in series to each other. A clock signal CLK input from a clock terminal (hereinafter, referred to as a CLK terminal) 26 is input to an inverter circuit 27, inverted, and output as an inverted internal clock signal CKN. The output signal from the inverter circuit 27 is input to the inverter circuit 28, inverted, and output as the internal clock signal CK.
[0012]
The master latch unit 13a includes clocked inverter circuits 14 and 15 to which signals CK and CKN are input from the internal clock generation unit 13c, and a NOR circuit 16. An output signal from the selector circuit 3 is input to a clocked inverter 14, and an output signal from the clocked inverter 14 is input to one input of a NOR circuit 16. A reset signal RN input from a reset input terminal (hereinafter, referred to as an RN terminal) 7 is inverted and input to the other input of the NOR circuit 16 via the inverter circuit 9. The output signal from the NOR circuit 16 is input to the clocked inverter circuits 15 and 17, respectively. An output signal from the clocked inverter circuit 15 is input to one input of a NOR circuit 16.
[0013]
As a result, the output signal from the selector circuit 3 is fetched into the master latch section 13a during the period when the internal clock signal CK is at the “low” level, and is fetched during the period when the internal clock signal CK is at the “high” level. The signal is held. Here, when the reset signal RN is at the “high” level, the output signal from the selector circuit 3 is inverted and output from the NOR circuit 16, and when the reset signal RN is at the “low” level, The low 'level is output from the NOR circuit 16. The reset signal RN is asynchronous with the clock signal CLK, and is a signal for once resetting data in the master-slave latch circuit at the start of operation regardless of the clock signal CLK so as not to cause a malfunction.
[0014]
The slave latch unit 13b includes clocked inverter circuits 17 and 18 to which signals CK and CKN from the internal clock generation unit 13c are input, a NOR circuit 19, and three inverter circuits 20 to 22. The output signal from the NOR circuit 16 of the master latch unit 13a is input to the clocked inverter circuit 17, and the output signal from the clocked inverter circuit 17 is input to one input of the NOR circuit 19. The reset signal RN input from the RN terminal 7 is inverted and input to the other input of the NOR circuit 19 via the inverter circuit 9. The output signal of the NOR circuit 19 is input to the clocked inverter circuit 18 and the inverter circuits 20 and 22, respectively. An output signal from the clocked inverter circuit 18 is input to one input of a NOR circuit 19.
[0015]
As a result, the output signal from the master latch unit 13a is fetched into the slave latch unit 13b while the internal clock signal CK is at the “high” level, and is fetched while the internal clock signal CK is at the “low” level. Signal is retained. Here, when the reset signal RN is at the “high” level, the output signal from the master latch unit 13a is inverted and output from the NOR circuit 19, and when the reset signal RN is at the “low” level, The “low” level is output from the NOR circuit 19.
[0016]
The signal input from the slave latch unit 13b to the inverter circuit 20 is inverted and input to the inverter circuit 21, and an output signal from the inverter circuit 21 is output from an output terminal (hereinafter, referred to as a Q output terminal) 23. The signal input from the slave latch circuit 13b to the inverter circuit 22 is inverted and output from an inverted output terminal (hereinafter referred to as a QN output terminal) 24.
[0017]
Next, the configuration and operation of a scan test circuit using the flip-flop circuit 300 with a scan function configured as described above will be described.
[0018]
FIG. 4 is a block diagram showing a configuration of a scan test circuit 400 configured using the flip-flop circuit shown in FIG.
[0019]
The scan test circuit 400 includes the above-described flip-flop circuits with scan function 35 and 36 and combination circuits 33 and 34 used during normal operation. These circuits are used as shift registers during a scan test. Wiring is provided and a scan path is configured to operate.
[0020]
The data input terminal DATAIN31 is connected to the combination circuit 33, and an output signal from the combination circuit 33 is input to the D terminal 6 of the flip-flop circuit 35 with a scan function. Further, the scan input terminal SCANIN32 is connected to the SI terminal 4 of the flip-flop circuit with scan function 35. Further, the SE terminal 5, the CLK terminal 26 and the RN terminal 7 are connected to the respective SE terminal 5, CLK terminal 26 and RN terminal 7 of the flip-flop circuits with scan function 35 and 36, respectively. The Q output terminal 23 of the flip-flop circuit with scan function 35 is connected to the SI terminal 4 of the combination circuit 34 and the flip-flop circuit 36 with scan function, respectively, and the output signal from the combination circuit 34 is connected to the flip-flop circuit 36 with scan function. The signal is input to the D terminal 6. An output signal 37 is output from the Q output terminal 23 of the flip-flop circuit 36 with a scan function.
[0021]
The operation modes of the scan test circuit 400 include a scan test mode and a normal operation mode. The operation of the scan test circuit 400 in each operation mode will be described below.
[0022]
First, the operation in the scan test mode will be described. FIG. 5 is a block diagram for describing an operation of scan test circuit 400 in the scan test mode.
[0023]
When the scan enable signal SE is at the “high” level, the SI signal input from the SI terminal 4 is selected in the selector circuits 3 in the flip-flop circuits with scan function 35 and 36 constituting the scan path. The scan test mode is set. As a result, the SI signal is input from the SCANIN terminal 32 to the SI terminal 4 of the flip-flop circuit with scan function 35, and the input SI signal is synchronized with the CLK signal to the Q output terminal of the flip-flop circuit with scan function 35. 23, and is input to the SI terminal 4 of the flip-flop circuit 36 with a scan function at the subsequent stage. The SI signal input to the SI terminal 4 of the flip-flop circuit with scan function 36 is output as the SCANOUT signal 38 from the Q output terminal 23 of the flip-flop circuit with scan function 36 in synchronization with the CLK signal.
[0024]
Next, the operation in the normal operation mode will be described. FIG. 6 is a block diagram for describing an operation of scan test circuit 400 in the normal operation mode.
[0025]
When the scan enable signal SE is at the “low” level, the D signal input from the D terminal 6 is selected in the selector circuits 3 in the flip-flop circuits with scan function 35 and 36 constituting the scan path. The normal operation mode is set. As a result, the D signal is input from the DATAIN terminal 31 to operate the combinational circuit 33, and the result is input to the D terminal 6 of the flip-flop circuit with scan function 35. The input D signal is output from the Q output terminal 23 of the flip-flop circuit with scan function 35 in synchronization with the CLK signal to operate the combination circuit 34 at the next stage, and the result is output to the flip-flop circuit with scan function at the subsequent stage. It is input to 36 D terminals 6. The D signal input to the D terminal 6 of the flip-flop circuit with scan function 36 is output as the DATAOUT signal 39 from the Q output terminal 23 of the flip-flop circuit with scan function 36 in synchronization with the CLK signal.
[0026]
As described above, the scan test circuit 400 can switch between the scan test mode and the normal operation mode by controlling the SE signal input from the SE terminal 5. In the above description, a simple scan test circuit in which flip-flop circuits with scan functions are connected in two stages has been described as an example. However, in an actual semiconductor integrated circuit, many flip-flop circuits with scan functions are chained. And a scan test circuit is configured in such a manner as to form a large-scale circuit configuration.
[0027]
FIG. 7 is a circuit diagram showing, at a transistor level, the configuration of the selector circuit 3 in the flip-flop circuit with scan function 300 shown in FIG. 3 and the clocked inverter circuit 14 of the master latch section 13a constituting the flip-flop circuit with reset function. It is. Here, the selector circuit 3 and the clocked inverter circuit 14 are composed of composite elements 60 that realize their respective functions.
[0028]
The composite device 60 includes PMOS transistors 40 to 44, NMOS transistors 45 to 49, and an inverter circuit 8.
[0029]
The sources of the PMOS transistors 40 and 42 are connected to a power supply potential (hereinafter, referred to as VDD), and the drain of the PMOS transistor 40 is connected to the source of the PMOS transistor 41. The drain of the PMOS transistor 42 is connected to the source of the PMOS transistor 43, and the drains of the PMOS transistors 41 and 43 are connected to the source of the PMOS transistor 44.
[0030]
The drain of the PMOS transistor 44 is connected to the drain of the NMOS transistor 45, and the source of the NMOS transistor 45 is connected to the drains of the NMOS transistors 46 and 48. The source of the NMOS transistor 46 is connected to the drain of the NMOS transistor 47, and the source of the NMOS transistor 48 is connected to the drain of the NMOS transistor 49. The source of the NMOS transistor 47 and the source of the NMOS transistor 49 are grounded (hereinafter, referred to as GND).
[0031]
The gates of the PMOS transistor 40 and the NMOS transistor 47 are connected to the SI terminal 4, and the gates of the PMOS transistor 42 and the NMOS transistor 46 are connected to the SE terminal 5. The gates of the PMOS transistor 43 and the NMOS transistor 48 are connected to the D terminal 6, and the gates of the PMOS transistor 41 and the NMOS transistor 49 are connected to the SE terminal 5 via the inverter circuit 8. The internal clock signal CK is input to the gate of the PMOS transistor 44, and the internal clock signal CKN is input to the gate of the NMOS transistor 45.
[0032]
As described above, the selector circuit 3 of the flip-flop circuit 300 with the scan function shown in FIG. 3 and the clocked inverter circuit 14 of the master latch unit forming the flip-flop circuit 13 with the reset function are used to reduce the layout area. In general, it is constituted by a composite element 60 constituted by multi-stage transistors.
[0033]
Next, the operation of the composite device 60 shown in FIG. 7 will be described.
[0034]
In the scan test mode in which the “high” level is input to the SE terminal 5 as the SE signal, the PMOS transistor 41 and the NMOS transistor 46 are turned on, and the PMOS transistor 42 and the NMOS transistor 49 are turned off. When the SI signal input from the SI terminal 4 is at a “low” level, the PMOS transistor 40 is turned on and the NMOS transistor 47 is turned off, so that the SI signal is synchronized with the internal clock signals CK and CKN. The 'high' level which is an inverted signal of the signal is output from node 25. When the SI signal input from the SI terminal 4 is at the “high” level, the PMOS transistor 40 is turned off and the NMOS transistor 47 is turned on, so that the PMOS transistor 40 is turned on and synchronized with the internal clock signals CK and CKN. , SI signal, which is an inverted signal of “low” level, is output from node 25.
[0035]
Further, in the normal operation mode in which the “low” level is input to the SE terminal 5 as the SE signal, the PMOS transistor 41 and the NMOS transistor 46 are turned off, and the PMOS transistor 42 and the NMOS transistor 49 are turned on. When the D signal input from the D terminal 6 is at a “low” level, the PMOS transistor 43 is turned on and the NMOS transistor 48 is turned off, so that the D signal is synchronized with the internal clock signals CK and CKN. The 'high' level which is an inverted signal of the signal is output from node 25. Further, when the D signal input from the D terminal 6 is at the “high” level, the PMOS transistor 43 is turned off and the NMOS transistor 48 is turned on, so that the PMOS transistor 43 is turned on and synchronized with the internal clock signals CK and CKN. , D signal is output from the node 25 as a low level.
[0036]
[Problems to be solved by the invention]
However, in the composite device 60 shown in FIG. 7, if the PMOS transistor 40 or the NMOS transistor 47 is broken due to an electrical or physical cause, the following problem occurs.
[0037]
FIG. 8 is a circuit diagram for explaining a case where the PMOS transistor 40 is broken.
[0038]
When the PMOS transistor 40 is broken, it may be considered that it is electrically equivalent to the resistor 50. In such a case, in the scan test mode, when the SE signal is at the “high” level and the “high” level is input to the SI terminal 4 as the SI signal, the PMOS transistor 41 and the NMOS transistors 46 and 47 are turned on. Become. Here, assuming that the resistance 50 has a certain magnitude, for example, a resistance value having a value of several kΩ to several tens kΩ, the SI signal output to the node 25 in synchronization with the internal clock signals CK and CKN becomes' There may be an intermediate potential that is neither the high level nor the low level. If an inverter circuit is connected beyond the node 25, a high level may be output from the inverter circuit. As a result, there is no problem in operation, and it is not possible to detect that the PMOS transistor 40 has been destroyed.
[0039]
FIG. 9 is a circuit diagram for explaining a case where the NMOS transistor 47 is broken.
[0040]
When the NMOS transistor 47 is broken, it may be considered that it is electrically equivalent to the resistor 51. Similarly, in this case, when the SE signal goes high in the scan test mode and a low level is input to the SI terminal 4 as the SI signal, the PMOS transistors 40 and 41 and the NMOS transistor 46 are turned on. Become. Here, assuming that the resistor 51 has a certain magnitude, for example, a resistance value having a value of several kΩ to several tens kΩ, the SI signal output to the node 25 in synchronization with the internal clock signals CK and CKN is “ There may be an intermediate potential that is neither the high level nor the low level. If an inverter circuit is connected before the node 25, the inverter circuit may output a "low" level. As a result, there is no problem in operation, and it is not possible to detect that the NMOS transistor 47 is broken, so that the NMOS transistor 47 is selected as a non-defective product.
[0041]
By the way, when a part of a transistor included in a semiconductor integrated circuit is broken by an electrical or physical factor, a test method for detecting a defect by measuring a leak current is known. However, in a semiconductor integrated circuit, generally, transistors are connected in multiple stages in order to reduce a layout area, so that it is not easy to measure a leakage current and detect a defect.
[0042]
For example, in the circuit example shown in FIG. 8, by controlling the externally controllable SE signal to the “high” level, the PMOS transistor 41 and the NMOS transistor 46 are turned on, and the externally controllable internal clock is controlled. By controlling the signal CK to the “low” level and CKN to the “high” level, the PMOS transistor 44 and the NMOS transistor 45 are turned on, and the leak current is measured. However, since it is not easy to control the SI signal from the outside, when the NMOS transistor 47 is in the OFF state, the through current caused by the resistor 50 does not flow, and the failure is detected by measuring the leak current. You may not be able to.
[0043]
The present invention has been made in order to solve such a problem of the related art. Even if the transistors are connected in multiple stages to reduce the layout area, the leakage current is measured and the electric current is measured. Another object of the present invention is to provide a flip-flop circuit with a scan function, a scan test circuit, and a semiconductor integrated circuit, which can detect a transistor destroyed due to a physical factor.
[0044]
[Means for Solving the Problems]
The flip-flop circuit with a scan function of the present invention has a first input terminal to which a logic input signal for normal operation is input, and a second input terminal to which a logic input signal for scan test is input, and operates normally during normal operation. Circuit for selecting and outputting a logic input signal for use in a scan test and selecting and outputting the logic input signal for scan test during a scan test, and a master for taking in and holding an output signal from the select circuit in accordance with a clock signal A latch section, and a master-slave latch circuit to which a slave latch section that captures and holds an output signal from the master latch section in accordance with a clock signal is connected, wherein the selection circuit and a part of the master latch section are connected to each other. Is composed of a composite element including an NMOS transistor and a PMOS transistor. And between the power supply potential, the logic input signal the scan test detection PMOS transistor for detecting the breakdown of the NMOS transistor is input to the gate is connected, the objects can be achieved.
[0045]
Preferably, the master-slave latch circuit has a reset terminal to which a reset signal is input, and the reset terminal is connected to a gate of the detection PMOS transistor.
[0046]
The flip-flop circuit with a scan function of the present invention has a first input terminal to which a logic input signal for normal operation is input, and a second input terminal to which a logic input signal for scan test is input, and operates normally during normal operation. Circuit for selecting and outputting a logic input signal for use in a scan test and selecting and outputting the logic input signal for scan test during a scan test, and a master for taking in and holding an output signal from the select circuit in accordance with a clock signal A latch section, and a master-slave latch circuit to which a slave latch section that captures and holds an output signal from the master latch section in accordance with a clock signal is connected, wherein the selection circuit and a part of the master latch section are connected to each other. Is composed of a composite element including an NMOS transistor and a PMOS transistor. Between the ground potential, the logical input signal the scan test detection NMOS transistor for detecting the breakdown of the PMOS transistor to be input to the gate is connected, the objects can be achieved.
[0047]
Preferably, a gate of the detection NMOS transistor is connected to a test terminal to which a test signal that can be controlled from the outside is input.
[0048]
Preferably, the master-slave latch circuit has a reset terminal to which a reset signal is input, and an inverted signal of the reset signal is input to the test terminal.
[0049]
In the scan test circuit of the present invention, a scan path is formed by connecting a plurality of flip-flop circuits with a scan function of the present invention, thereby achieving the above object.
[0050]
A semiconductor integrated circuit according to the present invention includes: a flip-flop circuit having a scan function according to the present invention; and a combination circuit connected to at least one of the first input terminal and the output terminal of the flip-flop circuit having a scan function. Thereby, the above object is achieved.
[0051]
Hereinafter, the operation of the present invention will be described.
[0052]
According to the present invention, in order to reduce the layout area, when the selection circuit and a part of the master latch unit (clocked inverter) are composed of a composite element including an NMOS transistor and a PMOS transistor, A detection PMOS transistor is provided between the output of the element and the power supply potential, and an externally controllable test signal is input to the gate of the detection PMOS transistor to turn the detection PMOS transistor on. As a result, a large current can flow between the ground potential and the power supply potential through the NMOS transistor and the detection PMOS transistor that have been destroyed in the composite device. It is possible to detect the destruction of the NMOS transistor whose SI signal is input to its gate without controlling the transistor.
[0053]
Further, in the present invention, a detection NMOS transistor is provided between the output of the composite device and the ground potential, and a test signal that can be controlled from the outside is input to the gate of the detection NMOS transistor, so that the detection NMOS transistor is provided. Set to ON state. As a result, a large current can flow between the ground potential and the power supply potential through the PMOS transistor and the detection NMOS transistor that are destroyed in the composite device. Destruction of a PMOS transistor whose SI signal is input to its gate can be detected without controlling the transistor.
[0054]
By using the RN signal as a test signal for controlling the detection PMOS transistor, a test signal can be input without providing a new terminal. Also, an inverted signal of the RN signal can be used as a test signal for controlling the detection NMOS transistor.
[0055]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
[0056]
(Embodiment 1)
FIG. 1 is a circuit diagram showing a configuration of a flip-flop circuit with a scan function 100 according to an embodiment of the present invention. In FIG. 1 and FIG. 2 below, components having the same functions as those of the conventional flip-flop circuit with scan function 300 shown in FIG. 3 and FIG.
[0057]
The flip-flop circuit with scan function 100 is different from the conventional flip-flop circuit with scan function 300 shown in FIGS. 3 and 7 in that the selector circuit 3 and the clocked inverter 14 in the master latch section 13a of the latch circuit 13 with reset function are different from each other. It is composed of a composite element 60, and is connected to the output node 25 of the composite element 60, and the transistor breakdown detection circuit 1 is provided. The transistor destruction detection circuit 1 includes a detection PMOS transistor 2 and VDD. The detection PMOS transistor 2 has a drain connected to the output node 25 of the composite device 60, a source connected to VDD, and a gate to which an RN signal is input from an RN terminal 7. Although a test (TEST) signal may be separately input to the gate of the detection PMOS transistor 2, a new input terminal does not need to be separately provided by using the RN signal.
[0058]
Hereinafter, in the flip-flop circuit with scan function 100 of the present embodiment thus configured, as described with reference to FIG. 9 in the related art, when the NMOS transistor 47 is broken and becomes equivalent to the resistor 51. Will be described.
[0059]
In the scan test mode, when the SE signal is at the “high” level and the “low” level is input to the SI terminal 4 as the SI signal, the PMOS transistors 40 and 41 and the NMOS transistor 46 are turned on. Here, assuming that resistor 51 has a resistance value having a certain magnitude, the SI signal output to node 25 in synchronization with internal clock signals CK and CKN has a high level or a low level. However, there is a case where the potential becomes an intermediate potential.
[0060]
In such a case, in order to detect a defect by measuring a leak current, for example, in the flip-flop circuit with scan function 300 shown in FIG. 9, the SE signal that can be controlled from the outside is controlled to the “high” level. By turning on the PMOS transistor 41 and the NMOS transistor 46, the externally controllable internal clock signal CK is controlled to a "low" level, and CKN is controlled to a "high" level. 45 is turned on to measure the leakage current. However, since it is not easy to control the SI signal from the outside, when the PMOS transistor 40 is in the OFF state, the through current caused by the resistor 51 does not flow, and the defect is detected by measuring the leak current. You may not be able to.
[0061]
On the other hand, in the flip-flop circuit with scan function 100 of the present embodiment, by controlling the RN signal to the “low” level at the time of measuring the leak current, the PMOS transistor 2 is turned on, and the PMOS transistor 2 is switched from VDD to the PMOS transistor 2. , A node 25 and NMOS transistors 45, 46 and 47 to generate a current path through which current flows to GND. Therefore, regardless of the state of the PMOS transistor 40, when the NMOS transistor 47 is broken, a large current flows, and it becomes possible to detect a defect by measuring a leak current.
[0062]
(Embodiment 2)
FIG. 2 is a circuit diagram illustrating a configuration of a flip-flop circuit 200 with a scan function according to the second embodiment.
[0063]
This flip-flop circuit with scan function 200 is different from the conventional flip-flop circuit with scan function 300 shown in FIG. 3 and FIG. It is composed of a composite element 60, and is connected to the output node 25 of the composite element 60, and provided with a transistor destruction detection circuit 29. The transistor destruction detection circuit 29 includes a detection NMOS transistor 30 and GND. The detection NMOS transistor 29 has a drain connected to the output node 25 of the composite device 60, a source connected to GND, and a gate to which a TEST signal is input from a test input terminal (hereinafter, referred to as a TEST terminal) 52. It has become. Note that a signal obtained by inverting the RN signal input from the RN terminal 7 may be input to the gate of the detection NMOS transistor 30 instead of inputting the TEST signal from the newly provided TEST terminal. By using the RN signal in this manner, it is not necessary to separately provide a new input terminal.
[0064]
Hereinafter, in the flip-flop circuit 200 with the scan function according to the present embodiment configured as described above, as described with reference to FIG. 8 in the related art, when the PMOS transistor 40 is broken and becomes equivalent to the resistor 50 Will be described.
[0065]
In the scan test mode, when the SE signal is at the “high” level and the “low” level is input to the SI terminal 4 as the SI signal, the PMOS transistor 41 and the NMOS transistors 46 and 47 are turned on. Here, assuming that the resistance 50 has a resistance value having a certain magnitude, the SI signal output to the node 25 in synchronization with the internal clock signals CK and CKN is either the “high” level or the “low” level. However, there is a case where the potential becomes an intermediate potential.
[0066]
In such a case, in order to detect a defect by measuring a leak current, for example, in the flip-flop circuit 300 with a scan function shown in FIG. 8, the SE signal that can be controlled from the outside is controlled to a “high” level. By turning on the PMOS transistor 41 and the NMOS transistor 46, the externally controllable internal clock signal CK is controlled to a "low" level, and CKN is controlled to a "high" level. 45 is turned on to measure the leakage current. However, since it is not easy to control the SI signal from the outside, when the NMOS transistor 47 is in the OFF state, the through current caused by the resistor 50 does not flow, and the failure is detected by measuring the leak current. You may not be able to.
[0067]
On the other hand, in the flip-flop circuit 200 with the scan function of the present embodiment, the NMOS transistor 30 is turned on by controlling the TEST signal input from the TEST input terminal 52 to the “high” level at the time of measuring the leak current. In this state, a current path is generated in which a current flows from VDD to GND via the PMOS transistors 40, 41 and 44, the node 25, and the NMOS transistor 30. For this reason, regardless of the state of the NMOS transistor 47, when the PMOS transistor 40 is broken, a large current flows, and it becomes possible to detect a defect by measuring a leak current.
[0068]
The flip-flop circuits with scan function 100 and 200 of the first and second embodiments and the combination circuits 33 and 34 used in the normal operation are set so that these circuits operate as shift registers during the scan test. By wiring, a scan test circuit 400 as shown in FIG. 4 can be configured.
[0069]
In the flip-flop circuits 100 and 200 with a scan function according to the first and second embodiments, when a part of the master-slave latch circuit 13 excluding the clocked inverter 14 is destroyed by a physical factor or an electrical factor. In this case, it is possible to select a non-defective product from a non-defective product by comparing expected values with a test pattern regardless of the scan test mode and the normal operation mode. Therefore, when a part of the master-slave latch circuit 13 has a defect, the defect can be detected.
[0070]
Since the gates of the PMOS transistors 41 to 44 and the NMOS transistors 45 and 47 to 49 are connected to externally controllable terminals, if the transistors are defective, the intended input signal is not input. Since the logic changes, it is possible to distinguish non-defective products from defective products by comparing expected values with test patterns.
[0071]
【The invention's effect】
As described above, in a semiconductor integrated circuit in which a scan test circuit is configured using the flip-flop circuit with a scan function of the present invention, a transistor in which a scan signal SI, which is not easily controlled from the outside, is input to a gate. If the device is destroyed by electrical or physical factors, the leak current can be detected by controlling the reset signal or the test signal input from the externally controllable test terminal. And can be sorted out.
[Brief description of the drawings]
FIG. 1 is a circuit diagram illustrating a configuration of a flip-flop circuit with a scan function according to a first embodiment.
FIG. 2 is a circuit diagram illustrating a configuration of a flip-flop circuit with a scan function according to a second embodiment.
FIG. 3 is a circuit diagram showing a configuration of a conventional flip-flop circuit with a scan function.
FIG. 4 is a block diagram illustrating a configuration of a scan test circuit.
FIG. 5 is a block diagram for explaining an operation in a scan test mode in the scan test circuit.
FIG. 6 is a block diagram for explaining an operation in a normal operation mode in the scan test circuit.
FIG. 7 is an equivalent circuit diagram showing, at a transistor level, a configuration of a composite element forming a selector circuit of a flip-flop circuit with a scan function and a clocked inverter in the flip-flop circuit with a reset function.
8 is an equivalent circuit diagram showing a state in which a PMOS transistor is broken in the composite device shown in FIG. 7;
9 is an equivalent circuit diagram showing a state in which an NMOS transistor is broken in the composite device shown in FIG. 7;
[Explanation of symbols]
1,29 Transistor destruction detection circuit
2, 40, 41, 42, 43, 44 PMOS transistors
3 Selector circuit
4 Scan signal input terminal (SI)
5 Scan enable terminal (SE)
6 Data signal input terminal (D)
7 Reset terminal (RN)
8, 9, 20, 21, 22, 27, 28 Inverter circuit
10, 11 AND circuit
12 OR circuit
13. Flip-flop circuit with reset function
13a Master latch
13b Slave latch unit
13c Internal clock generator
14, 15, 17, 18 Clocked inverter circuit
16, 19 NOR circuit
23 Q output terminal of flip-flop circuit with scan function
24 Q output terminal inverted output terminal QN
25 Output node of composite element
26 Clock terminal
30, 45, 46, 47, 48, 49 NMOS transistors
31 DATAIN terminal
32 SCANIN terminal
33, 34 Combination circuit
35, 36, 100, 200, 300, 400 flip-flop circuits with scan function
37 Output signal of circuit with scan function
38 SCANOUT signal in scan test mode
39 DATAOUT signal in normal operation mode
50, 51 resistance
52 TEST terminal

Claims (7)

It has a first input terminal to which a logic input signal for normal operation is input, and a second input terminal to which a logic input signal for scan test is input, and selects and outputs the logic input signal for normal operation during normal operation. A selection circuit for selecting and outputting the scan test logic input signal during a scan test;
A master-slave unit connected to a master latch unit that captures and holds an output signal from the selection circuit according to a clock signal and a slave latch unit that captures and holds an output signal from the master latch unit according to a clock signal And a latch circuit,
The selection circuit and a part of the master latch section are formed by a composite element including an NMOS transistor and a PMOS transistor. The scan test logic input signal is provided between an output of the composite element and a power supply potential. A flip-flop circuit with a scan function to which a detection PMOS transistor for detecting destruction of an NMOS transistor input to its gate is connected. The flip-flop circuit with a scan function according to claim 1, wherein the master-slave latch circuit has a reset terminal to which a reset signal is input, and the reset terminal is connected to a gate of the detection PMOS transistor. It has a first input terminal to which a logic input signal for normal operation is input, and a second input terminal to which a logic input signal for scan test is input, and selects and outputs the logic input signal for normal operation during normal operation. A selection circuit for selecting and outputting the scan test logic input signal during a scan test;
A master-slave unit connected to a master latch unit that captures and holds an output signal from the selection circuit according to a clock signal and a slave latch unit that captures and holds an output signal from the master latch unit according to a clock signal And a latch circuit,
The selection circuit and a part of the master latch section are composed of a composite element including an NMOS transistor and a PMOS transistor. The scan test logic input signal is provided between the output of the composite element and the ground potential. A flip-flop circuit with a scan function to which a detection NMOS transistor for detecting destruction of a PMOS transistor input to its gate is connected. 4. The flip-flop circuit with a scan function according to claim 3, wherein a gate of the detection NMOS transistor is connected to a test terminal to which a test signal that can be controlled from the outside is input. The flip-flop circuit with a scan function according to claim 4, wherein the master-slave latch circuit has a reset terminal to which a reset signal is input, and an inverted signal of the reset signal is input to the test terminal. A scan test circuit, wherein a plurality of flip-flop circuits with a scan function according to claim 1 are connected to form a scan path. 6. A flip-flop circuit with a scan function according to claim 1, and a combination circuit connected to at least one of the first input terminal and the output terminal of the flip-flop circuit with a scan function. Semiconductor integrated circuit.

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