JP3240744B2 - Output pad circuit and test circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output pad circuit capable of improving the efficiency of detecting a short circuit of a wiring connected to an input / output pin in an integrated circuit.

[0002]

2. Description of the Related Art In recent years, a boundary scan test has been developed as an important technique for designing a testable board (printed circuit board).
1 standardizes the access method. Hereinafter, a wiring test using a boundary scan test circuit based on IEEE1149.1 will be described with reference to the drawings. 7, an output pin 702 of the integrated circuit 701,
Output pads 730 and 731 are connected to 703. The configuration of the output pads 730 and 731 is such that output buffers 706 and 707 which output logical values 1/0 having the same driving capability are provided.
Selection means 712, 713 each controlled by control signal 1
Is input. Outputs 708 from the internal logic 740 for output pads are provided to the selection means 712 and 713, respectively.
709 and the outputs of the flip-flops 714 and 715 are input. Outputs of the flip-flops 716 and 717 are input to the flip-flops 714 and 715, respectively. Outputs of the flip-flops 716 and 717 are simultaneously output as scan outputs 710 and 711. Scan outputs 711 and 720 and outputs of output buffers 706 and 707 are input to selection means 718 and 719 controlled by control signal 2, respectively, and the outputs thereof are flip-flops 716 and 71, respectively.
7 is input.

The operation of the output pad circuit configured as described above will be described. When the control signal 2 selects the scan input, the flip-flops 716 and 717 built in the output pad circuit of the integrated circuit 701 are all serial. And the input of the first flip-flop is connected to the integrated circuit 701.
, And the output of the last flip-flop is connected to the scan output pin 722 to form a scan path. As a result, an arbitrary logical value is input from the outside of the integrated circuit to each output pad circuit by the scan operation, and at the same time, the logical value previously stored in the flip-flop is scanned out.
After inputting an arbitrary logical value to the flip-flop 716,
The flip-flop 714 stores the value, and the control signal 1 causes the logic value stored in the flip-flop 714 to be output through the output buffer 706. The output of the output buffer is input to the flip-flop 716 by the control signal 2, and the output logic value is stored in the flip-flop 716 at a certain timing. By controlling the control signal 2 again, a scan path is formed, and the stored logical value of the output terminal is output to the outside of the integrated circuit.

A description will be given of an inspection operation of a wiring short defect inspection using the above operation. FIG. 8 shows an integrated circuit 800.
1 schematically shows the conventional output pad circuits 801 to 804 built in the. Block 805 of output pad 801
Indicates the flip-flop 716 in FIG. 7, and 0 and 1 in the block indicate output logic values of the flip-flop. Block 806 indicates an output buffer, and 0, 0 in the block.
1 indicates the input logical value of the output buffer. The same applies to the blocks shown in the output pad circuits 802 to 804. The test step configures a scan path by the control signal 2 as shown in FIG.
A logical value from 11 to 0001 is input. As a result, FIG.
As shown in (1), a logical value sequence is input to the block 805 of each output pad circuit. Next, as shown in FIG.
The logical value of 05 is output from the block 806 and a predetermined logical value is output to the wirings 812 to 815 connected to the output pad circuit. Next, as shown in FIG.
A logic value of 6 is measured at block 805 for each output pad circuit. If there is no defect, the logical value measured at this time is the logical value itself set as shown in the figure. Next, FIG.
e, a scan path is formed to output the measurement result to the outside of the integrated circuit, and at the same time, the next test pattern 0010 is output.
Scan input. A defect inspection is performed by comparing the scan output measurement result with an expected value 0001 outside the integrated circuit.

[0005]

By the way, in the above configuration, when the wirings 814 and 815 are short-circuited as shown in FIG. 8F, the logical values 1 and 0 of the output buffer are output with the same driving capability. As a result, the potential on the wiring becomes an intermediate potential, and the measured logical value becomes indefinite as shown in FIG. 8G. Therefore, even if a short failure occurs, the same logical value as the normal expected value (in this case, 000
There is a problem that 1) may be measured and the detection rate decreases.

In order to detect a short circuit between pins, only a specific pin is set to a logical value 1 (or 0), and all the remaining pins are set to a logical value 0 (or 1). In this way, it is necessary to perform inspection while sequentially changing specific pins. If there are N pins, it is necessary to prepare N expected value patterns. Therefore, there is a problem that the pattern length increases in an integrated circuit having a large number of pins.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and it is an object of the present invention to improve the detection efficiency by eliminating the uncertainty of a measured value even when a short circuit occurs, and to further shorten the test pattern by compressing the measured value. It is an object of the present invention to provide an output pad circuit capable of performing the following.

[0008]

In order to achieve the above-mentioned object, the present invention according to claim 1 performs a test operation according to a control signal.
Or an output pad circuit operating in normal operation,
Inputting the logical value or the second logical value of the first logical value
A first drive according to a value or the second logical value, respectively.
Output means for outputting an output signal with the ability or the second drive ability
During the test operation, the first driving ability and
The second driving capability is controlled to be different from each other,
During the normal operation, the first drive capability and the second drive
In this configuration, a control means for controlling the dynamic ability to the same drive ability is provided.

Further, according to a second aspect of the present invention , in the first aspect of the present invention, the output logical value output from the output means is measured.
It is an arrangement which comprises a measuring means for constant for.

Further, according to a third aspect of the present invention, the first logical value
Alternatively, generate a second logical value and output it as an internal logical signal
Connected to the output pin in an integrated circuit that contains internal logic
A test circuit for testing wiring failures,
A test circuit is configured in the integrated circuit and the first logic
Input a test signal having a logical value or the second logical value
Test signal input means for executing the internal logic signal and the test
Input signal and generate an output signal according to the input.
A plurality of output pad circuits, wherein the output pad circuit
Operates in test operation or normal operation depending on the control signal
An output pad circuit that outputs from the internal logic.
An input terminal to which the internal logic signal to be input is input;
The test is performed according to the test operation or the normal operation.
Signal or the internal logic input from the input terminal.
Input control means for selecting a signal and outputting it as a selection signal
And the first signal of the selection signal with the selection signal as an input.
A first value according to a logical value or the second logical value, respectively.
The output signal is output at the second driving capability or the second driving capability.
Output means for inputting the test signal,
During the first operation, the first driving ability and the second driving ability are mutually connected.
At the time of the normal operation.
The first drive power and equal have driving ability of the second drive capacity
Control means for controlling the output means, and the output means.
Measuring means for measuring an output logic value to be output,
The output pad circuit outputs the output signal of the output means to the output.
Output to the force pin .

Further, according to a fourth aspect of the present invention, in the third aspect of the present invention, the output pad circuit includes a scan input and a scan input.
A plurality of output pad circuits in serial.
Boundary scans that make up the connected scan path
It is a test circuit .

Further, according to a fifth aspect of the present invention, in the fourth aspect of the present invention, the measuring means includes the scan input and the output.
Input the output signal of the force means and select one of them
Selecting means for outputting as a second selecting signal
And receiving the second selection signal as input and changing the logic value of the signal to
Hold temporarily and output to the input control means and scan output
It is an arrangement which has a first holding means that.

Further, the invention according to claim 6 is based on the invention according to claim 5.
In the following description, the measuring means comprises an output of the input control means and
Exclusive OR of the input signal with the output of the output means as input
Exclusive OR generating means for generating an exclusive OR, and exclusive OR generating
The output of the means and the output of the output means as inputs
Measurement signal selection means for selecting and outputting one of the inputs,
The output of the measurement signal selection means and the output from the scan input terminal
Scan input as input, select either input
Scanning selection means for outputting the selected data.
Selecting means for selecting the measurement signal instead of the output signal.
It is characterized in that the output of the means is input .

Further, the invention of claim 7 is the invention of claims 5 to
In the invention according to the sixth aspect, the input control means includes the first holding unit.
Means for temporarily holding the logical value of the signal output from the means.
Holding means, output of the second holding means and the input terminal
And one of them as the selection signal.
Input signal selection means for outputting
It is.

Further, the invention according to claim 8 is the invention according to claim 3.
In the description, the control means receives the control signal as an input,
The output of the input control means is the second logical value and
Only when the control signal is a condition for selecting the normal operation,
Outputs a first logical value, and outputs the second logical value when the condition is not satisfied.
Outputting a logical value, wherein the output means outputs the
In the case of the first logical value, the first logical value is determined by the driving capability I1.
Is output, and when the selection signal is the second logical value,
The driving capability I2, which is sufficiently smaller than the driving capability I1,
First output means for outputting a logical value of 2 and the control means
The output control signal output from the
If the signal is the first logical value, the driving capability (I1-I2)
Outputs the second logical value, and the output control signal is
Second output means that does not contribute to the output in the case of the second logical value
Wherein the first output means and the second output means are
By driving the output of the output means together, the control signal
The output signal is output with the driving capability according to the signal and the selection signal.
It is characterized by force.

Further, the invention according to claim 9 is the invention according to claim 3.
In the above description, the control means further includes the control signal and the second
The control signal of the input, the selection signal and the control signal
The second control signal is input, and the control signal is
In the case of selection of normal operation, inversion of the logical value of the selection signal
Outputting a logical value, wherein the control signal selects the test operation.
, The second control signal is the first logical value of
Sometimes outputs the second logical value and the second control signal is
A logic value inverted from the logic value of the selection signal at the time of the second logic value;
First control means for outputting a value, the selection signal and the control signal,
Control signal and the second control signal, and the control signal
Is the selection of the normal operation, the logic of the selection signal
Output the inverted logic value of the test value, and the control signal
The second control signal is the first operation signal.
Outputs the inverted logical value of the logical value of the selection signal when it is a logical value
And when the second control signal is at the second logical value,
And second control means for outputting a logical value of 1.
The force means receives the selection signal as input, and has a driving capability I2.
First output means for outputting the same logical value as the selection signal;
The output of the first control means is input and the first control
When the output of the stage is the first logical value, the driving capability I2
The second logical value is output with a driving capability I1 that is sufficiently larger than
And the output of the first control means is the second logical value
A second output means which does not contribute to the output in the case;
The output of the control means is input and the output of the second control means is
Is the second logical value, it is less than the driving capability I2.
The first logical value is output with a driving capability I1 which is larger by
If the output of the second control means is the first logical value,
A third output means that does not contribute to a force, wherein the first output means
Means, said second output means and said third output means
By driving the output of the output means together, the control signal
Signal, driving according to the second control signal and the selection signal
Outputting the output signal with the ability.
is there.

[0017]

According to the configuration of the first aspect of the present invention, normal operation can be performed.
The first driving capability corresponding to the first logical value and the second driving capability
The second drive capability corresponding to the logical value of
In the strike operation, the first drive capability and the second drive
The dynamic abilities are controlled differently. That is, Tess
Improve the defect detection rate due to the difference in driving capability during
It is possible to.

Further, according to the second aspect of the present invention, the output
The output pad circuit itself can measure the logical value of the force signal .

Further, according to the third aspect of the present invention, the communication
In normal operation, the input control means selects and outputs the internal logic signal.
The first and the second output from the output means by the control means.
And the second logical value are output to the output pin with equal driving capability.
You. In the test operation, the input control means
Output from the output means by the control means.
The first and second logical values are output to the output pins with different driving capabilities.
The output logic value output and simultaneously output from the output means is
Measured by measuring means provided for each pad circuit
Is done. That is, the output of the wiring connected to the output pin is
If a short circuit has occurred, output during test operation
Strong theory of driving ability due to difference in driving ability to drive signals
Stable and easy to measure by internal measuring means
You.

Further, according to the structure of the fourth aspect of the present invention, multiple
Output pad circuits are serially connected by a scan path.
Input data from the scan input,
Scan output signal of output pad circuit from scan output
Output from the input terminal.

Further, according to the fifth aspect of the present invention, a switch is provided.
The scan selection means selects the scan input to
The first holding means in all the output pad circuits are connected serially.
The test signal is input to the input control means.
Test can be performed, and the scan selection
By selecting the output, the measurement result of the output logical value is
Results are held in the first holding means, and the test results are
Output to

Further, according to the configuration of the invention of claim 6, the measurement is performed.
The constant signal selecting means selects the output of the exclusive OR generating means
The input logical value as the test signal and the test result
Possible to obtain an exclusive logical value of the output logical value of the fruit
Become.

Further, according to the configuration of the invention of claim 7,
Test signal input from a can input to a second holding unit
At the time of test operation.
The test signal is output from the input control means instead of the logic output.
Output as force.

Further, according to the structure of the eighth aspect of the present invention,
In the test operation, if the selection signal has the first logical value,
Only the first output means outputs the first logical value with the driving capability I1
When the selection signal has the second logical value, the first output means
Only outputs the second logical value with the driving capability I2,
The first driving ability and the second driving ability can be different
You. In the normal operation, the selection signal is set to the first logical value.
In the case of (1), only the first output means has the driving capability I1 and the first theory
And outputs the first logical value when the selection signal is the second logical value.
The output means and the second output means both have a driving capability (I
1-I2) and the driving capability I2, the output
As the stage, the second logical value is output with the driving capability I1, and
That is, the first driving ability is equal to the second driving ability.
Can be.

Further, according to the ninth aspect of the present invention, the
In the test operation, when the second control signal has the first logical value.
Means that the first control means outputs the second logical value,
Output means does not contribute to the output, and the second control means
Third output means for outputting an inverted logical value of the logical value of the signal
Does not contribute to the output if the selection signal is the second logical value,
Output the first logical value with the driving capability I1.
Thus, the first output means, the second output means, and the second
If the selection signal is the first logical value by the output means of No. 3,
Outputs the first logical value as an output signal with dynamic capability I1 + I2
If the selection signal has the second logical value, the driving capability
The logical value of 2 is output as an output signal. Also, test operation
In operation, select when the second control signal is the second logical value
A second output means for outputting an inverted logical value of the logical value of the signal;
The stage has the driving capability I1 if the selection signal has the second logical value.
Output a logical value of 2, and if it is the first logical value, contribute to the output.
The second control means outputs the first logical value,
Output means does not contribute to the output, so that the first output
Means, the second output means and the third output means.
If the signal is the first logical value, the first logical value is obtained by the driving capability I2.
Is output as an output signal, and the selection signal is a second logical value.
If the driving capability I1 + I2 is used, the second logical value is used as an output signal.
Output.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An output pad circuit according to an embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, reference numeral 150 denotes an integrated circuit incorporating the output pad circuit of the present invention;
152 is an output pad circuit of the present invention. 153, 15
Reference numeral 4 denotes a scan output from the output pad circuit;
5, 156 are scan inputs to the output pad circuit.
As shown in the figure, the scan output is connected to the scan inputs of different pad circuits, and a plurality of pad circuits are serially connected to finally scan input pin 1 of integrated circuit 150.
60 and the scan output pin 161. Signals 157 and 158 from the internal logic circuit are input to the output pad circuit.

The output pad circuit 151 of the present invention will be described in detail with reference to the integrated circuit having the overall configuration.
Reference numeral 101 denotes an output circuit having a variable output logical value driving capability. Reference numeral 106 denotes a control unit 1 for making the logical value 0 sufficiently lower than the logical value 1 during inspection.
Is control means 2 for inputting an input signal 157 to the output pad circuit and inputting an arbitrary logical value to the output circuit 101;
Reference numeral 112 denotes a measurement unit that measures the output logical value of the output circuit 101.

Next, a specific configuration will be described. Output means 1 is 1
As shown by 20, a P-type MOS transistor 102 having a driving capability I1 and an N having a driving capability I2 (I1 >> I2).
The transistor 102 includes a type MOS transistor 103 and an inverter 105. The gate terminals of the transistors 102 and 103 are both connected to the output of the inverter 105, and the drain terminal is connected to the output terminal 159 of the output pad. Output means 2
N is the driving capability (I1-I2) as indicated by 104.
Type MOS transistor, the gate terminal of which is
It is connected to the output of (106), and its drain terminal is connected to the output terminal 159. The output of the control means 2 (107) is connected to the inverter 105.

The control means 1 (106) is composed of a NOR circuit, and its input receives the output of the selection means 108 and the control signal 1. The selection means 108 selects a signal from the input terminal 157 of the output pad when the control signal 3 has a logical value 0,
When the control signal 3 has the logical value 1, the output of the flip-flop 109 is selected and input to the inverter 105. Selection means 1 controlled by control signal 2 is provided in flip-flop 110
The output of the flip-flop 110 is input to the flip-flop 109, and at the same time, is output to the outside of the output pad circuit as the scan output 153. The output terminal 159 of the output pad and the scan input 155 are input to the selection unit 111. The selection unit 111 selects the scan input 155 when the control signal 2 has a logical value 0, and selects the signal from the output terminal 159 when the control signal 2 has a logical value 1.

The operation of the output pad circuit configured as described above will be described. When the control signal 3 and the control signal 1 have a logical value of 0, the selecting means 108 selects the input signal 157. When the input signal has the logical value 1, the P-type MOS transistor 102 is turned on, so that the output terminal 159 is driven to 1 by the driving capability I1, and when the input signal is the logical value 0, both the N-type MOS transistors 103 and 104 are turned on. For this purpose, the output terminal 159 is driven to the logical value 0 by the driving capability I1. When the control signal 2 has the logical value 0, the flip-flops 110 in the measuring means of all the output pads of this embodiment are serially connected to form a scan path and scan an arbitrary logical value from the scan input pin 160 to each flip-flop. In. Next, the logic value of the flip-flop 110 is stored in the flip-flop 109 in the control means 2 (107). Next, the control signal 3 is set to the logical value 1 so that the flip-flop 1
09 is output from the output circuit 101. At this time, when the control signal 1 is set to the logical value 1, the N-type M
The OS transistor 104 is always off. Therefore, when the output logical value is 1, the driving capability is I1, but the driving capability is 0.
At the time of, it becomes I2. Next, the logical value of the control signal 2 is set to 1 and the logical value of the output terminal 159 is stored in the flip-flop 110. Then, the control signal 2 is set to the logical value of 0 to configure a scan path and store the output which is stored in the flip-flop 110. The measurement result at the terminal 159 is output from the scan output pin 161 to outside the integrated circuit.

Next, the operation at the time of short-circuit inspection using the output pad circuit of this embodiment will be described with reference to FIG. FIGS. 2A and 2B schematically show the output pad circuits 201 to 204 of this embodiment incorporated in the integrated circuit 200 when the control signal 1 and the control signal 3 have the logical value 1. FIG. These drawings are diagrams corresponding to FIGS. 8C and 8D showing the procedure for inspecting the short-circuit failure of the wiring. Each output pad drives wirings 210-213. A block 222 in the output circuit 201 indicates a measuring means, and 0 and 1 in the block indicate measured logical values. A block 223 indicates an output circuit, and 0w in the block indicates a logical value 0 driven by the driving capability I2.
1s indicates a logical value 1 driven by the driving capability I1. When the wiring 212 and the wiring 213 have a short-circuit defect,
When the output circuit is driven as shown in FIG. 2A, since I1 >> I2, the wirings 212 and 213 are determined to have a logical value of 1. Therefore, the logical value measured by the measuring means is as shown in FIG.
By scanning out the result and comparing it with the expected value 0001, it is possible to reliably detect the short-circuit failure. When the control signal 1 has the logical value 0, the output logical values 1 and 0
Have no influence on the normal operation because both have the driving capability I1. Further, since the logical value of the output terminal 159 can be measured by the output pad circuit itself, it is not necessary to provide another measuring means outside the integrated circuit, and the inspection cost can be reduced.

As still another example, the output circuit 101 and the control means 1 (106) are configured as shown in FIG. Referring to FIG. 3, the output circuit 101 includes an output unit 5 indicated by 310, an output unit 6 indicated by 311 and an output unit 7 indicated by 312. The output means 5 includes a P-type MOS transistor 303 having a driving capability I2, an N-type MOS transistor 304 having a driving capability I2, and an inverter 30.
7 The gate terminals of the transistors 303 and 304 are both connected to the output of the inverter 307, and the drain terminal is connected to the output terminal 159 of the output pad. The input of the inverter 307 is connected to the output of the control means 2 (107). The output means 6 is a P-type MOS transistor having a drive capability I1 (I1 >> I2), and the output means 7 is an N-type MOS transistor having a drive capability I1.

The control means 1 is a control means 3 indicated by 313.
And control means 4 indicated by 314. Control means 3
(313) is an OR having the control signal 6 and the control signal 7 as inputs.
The circuit 306, the output of the control means 2 and the output of the OR circuit 306 are input and the output is a P-type MOS transistor 311
, And a NAND circuit 305 input to the gate terminal. The control means 4 (314) includes an inverter 315 receiving the control signal 6 as input, a control signal 7 and an inverter 315.
And an output of the control means 2 and an output of the AND circuit 309 are input and the output thereof is set to N.
NO input to the gate terminal of MOS transistor 312
An R circuit 308 is provided.

The operation of the output pad circuit configured as described above will be described. When the control signal 3 is a logical value 0 and the control signal 6 is a logical value 1, the selecting means 108
Select At this time, if the input signal has a logical value of 1, P-type M
Since both the OS transistors 311 and 303 are turned on, the output terminal 159 is driven to 1 with the driving capability I1 + I2.
Since both 2 and 304 are turned on, the output terminal 159 is driven to the logical value 0 with the driving capability I1 + I2.

At the time of the test, the control signal 3 is set to the logical value 1.
If the control signal 6 is a logical value 0 and the control signal 7 is a logical value 1, the N-type MOS transistor 312 is always off.
Therefore, when the output logic value is 1, the driving capability is I1 + I
However, when the logical value is 0, the driving capability is I2. The control signal 6 remains at the logical value 0, while the control signal 7 changes to the logical value 0.
, The P-type MOS transistor 311 is always turned off, and when the output logical value is 1, the driving capability is I2, but when the logical value is 0, the driving capability is I1 + I2.

By using this output pad circuit,
As shown in FIG. 4a, when the wiring 212 is short-circuited to the power supply line and a 1 stuck-at fault occurs, when the logical value 0 is driven by I2 and when the logical value 1 is driven by I1 + I2, the same measurement result as FIG. And a different input pattern is required to distinguish between stuck-at faults and short-circuit faults. This takes extra time to scan in a new input pattern. At this time, by inverting the control signal 7, FIG.
As shown in c, the driving capability of the output logic value is reversed, and the measurement result differs between the short-circuit failure and the stuck-at failure. This allows
Test pattern 0 with the same separation of short fault and stuck-at fault
001, the number of test patterns can be reduced.

As still another example, the measuring means 112 is shown in FIG.
The configuration shown in FIG. The configuration will be described with reference to FIG.
The measuring means 112 receives the output of the control means 2 (107) and the output of the output circuit 101 as inputs.
1 and the output of the exclusive-OR generating means 501 and the output circuit 1
A selection means 502 receives the output of the control signal 01 as an input and outputs one of the inputs according to the control signal 8. Selection means 50
The output of No. 2 is input to the selection means 111 having the scan input as another input, and the output of the selection means 111 is input to the flip-flop 110.

The operation of the measuring means configured as described above will be described. When the control signal 8 is a logical value 0 and the control signal 2 is a logical value 1, the flip-flop 110
The exclusive OR of the input and output of 1 is input. By using this output pad circuit, as shown in FIG. 6A, when a wiring short-circuit failure does not occur, the logical value measured by the measuring means is 0 regardless of the output of the control means 1. However, as shown in FIG. 6B, if the output of the control means 1 and the logical value of the output terminal of the output circuit are different due to the occurrence of a wiring short-circuit failure, the logical value 1 is measured by the measuring means. Therefore, four test patterns 0001, 0010, 0100, and 1000 in FIG. 6 are required as test patterns for a normal short-circuit defect test, and four expected value patterns are also required. However, by using the output pad circuit of this embodiment, only one expected value pattern of 0000 is required, and the expected value pattern can be significantly reduced.

[0039]

According to the output pad circuit of the first aspect of the present invention, the first driving capability and the first
The second drive capability can be controlled differently from each other
In performance, it is possible to improve the detection rate of failure.

According to the output pad circuit of the present invention, the output pad circuit itself measures the logical value of the output signal.
Since it is possible to constant, it is possible to reduce the test cost is not necessary to provide a separate measuring means outside the integrated circuit.

According to the test circuit of the third aspect of the present invention, in normal operation, the input control means is controlled by the internal logic signal.
Output from the output means by the control means.
The first and second logical values are output to the output pin with equal driving capability.
Is output. In the test operation, the input control means
Select signal and output it from the output means by the control means.
The output first and second logical values are output with different driving capabilities.
Output to the output pin and simultaneously output from the output means
The logical value is sent to the measuring means provided for each pad circuit.
Is measured. This allows only certain pins to be
Value, and all remaining pins to a second logical value.
In this case, the pin outputting the first logical value becomes the remaining pin.
Test operation when a short failure occurs with any of
Driving ability due to the difference in driving ability to drive the output signal at the time
Stable to a strong logical value and easily by internal measuring means
The measured short-circuit failure detection rate can be improved.

Further, according to the test circuit of the present invention,
Output pad circuits serially scan-path
When data is input from the scan input
In both cases, the output signal of the output pad circuit is output from the scan output.
Test signal setup and measurement
Whether to set and observe the results of the means using a scan path
Therefore, the number of test terminals for outputting the measured values can be significantly reduced.

According to the test circuit of the present invention, the first holding means is connected to the first holding means from outside using a scan path.
The test signal is input and the logical value of the output signal is
The circuit can be shared because it can be input to the holding means of
Becomes

According to the test circuit of the present invention, the measurement signal selection means outputs the output of the exclusive OR generation means.
By selecting, the input logic value as a test signal and
Take exclusive logical value of output logical value as test result
Is possible, and if a short circuit has not occurred,
The logical value is 0.
Since the theoretical value is 1, the expected value pattern can be significantly reduced .

Further, according to the test circuit of the present invention,
Then, in the test operation, the first drive capability and the second drive
Dynamic capacity can be varied, and the short-circuit defect detection rate can be increased.
Can improve. In the normal operation, the first driving capability
And the second drive capability can be made equal,
Has no effect.

According to the test circuit of the ninth aspect,
Then, in the test operation, output by the second control signal
The magnitude of the driving ability of the first logical value and the second logical value of the signal
It is possible to reverse the engagement, short-circuit failure and degeneration
Faults can be easily separated, and
Modification becomes easy.

[Brief description of the drawings]

FIG. 1 shows an output pad circuit and a test circuit according to an embodiment of the present invention.
Configuration diagram showing road

FIG. 2 is a schematic diagram illustrating the operation of the output pad circuit according to the embodiment of the present invention.

FIG. 3 is a configuration diagram showing an output pad circuit according to one embodiment of the present invention .

FIG. 4 is a schematic diagram illustrating the operation of the output pad circuit of FIG. 3;

FIG. 5 is a configuration diagram showing an output pad circuit according to one embodiment of the present invention .

6 is a schematic diagram illustrating the operation of the output pad circuit of FIG.

FIG. 7 is a configuration diagram of an output pad circuit having a conventional boundary scan test circuit.

FIG. 8 is a schematic diagram illustrating an operation of detecting a short-circuit failure using a conventional technique.

[Explanation of symbols]

 101 output circuit 106 control means 1 107 control means 2 112 measurement means 120 output means 1 104 output means 2 310 output means 5 311 output means 6 312 output means 7 313 control means 3 314 control means 4 501 exclusive OR generation means 502 Selection means

Claims (9)

(57) [Claims] 1. A test operation or a normal operation according to a control signal.
An output pad circuit operable in operation, comprising: a first logical value
Or a second logical value as an input and the first logical value or
The first driving capability and the first driving capability are respectively set according to the second logical value.
Means for outputting an output signal with a second driving ability; and, during the test operation, the first driving ability and the second
Control the driving capabilities of the
In operation, the first drive capability and the second drive capability
Control means for controlling the driving force to be equal.
Output pad circuit to butterflies. 2. An output logical value output from said output means.
2. A measuring device for measuring the temperature
Output pad circuit as described . 3. A method for generating a first logical value or a second logical value.
An integrated circuit that includes internal logic and outputs it as an internal logic signal
Test for faulty wiring connected to output pins on
A test circuit configured in the integrated circuit and having the first logical value or the second logical value.
Test signal input means for inputting a test signal, inputting the internal logic signal and the test signal as inputs,
And a plurality of output pad circuits for generating output signals according to
Wherein the output pad circuit operates in a test operation or a normal operation according to a control signal
An output pad circuit, wherein the internal logic signal output from the internal logic is input.
Input terminal and the test operation or the normal operation, respectively.
The test signal or the internal signal input from the input terminal.
Input control that selects the logical signal of the unit and outputs it as a selection signal
Means for receiving the selection signal as input and the first logic of the selection signal
The first drive according to the value or the second logical value, respectively.
The output signal is output with the dynamic capability or the second driving capability.
Output means, and the selection signal as an input.
Drive capability and second drive capability to different drive capabilities
During the normal operation, the first driving capability
Control the force and the second drive capacity to be equal drive capacity
Control means for measuring the output logical value output from the output means
Means, wherein the output pad circuit precedes the output signal of the output means.
A test circuit for outputting to an output pin. 4. The output pad circuit according to claim 1, further comprising a scan input and a scan input.
A scan having a scan output and serially connecting the plurality of output pad circuits.
Boundary scan test circuit
The test circuit according to claim 3, wherein 5. The measurement means receives the scan input and the output signal of the output means.
And select one of them and output it as the second selection signal.
Scanning selection means for inputting the second selection signal and temporarily storing the logical value of the signal
Hold and output to said input control means and scan output
5. The method according to claim 4, further comprising a holding means.
Test circuit. 6. The measuring means receives the output of the input control means and the output of the output means as an input.
Exclusive OR generation to generate exclusive OR of input signals
Means, an output of the exclusive-OR generating means, and an output of the output means.
Measurement signal to select and output either input as force
Selecting means, wherein the scan selecting means replaces the output signal with
The output of the measurement signal selection means is used as an input.
The test circuit according to claim 5, wherein 7. The input control means, Temporarily store the logical value of the signal output from the first holding unit.
Second holding means for holding; The output of the second holding means and the signal from the input terminal
An input that outputs one of them as the selection signal
6. A system according to claim 5, further comprising a force signal selecting unit.
6. The test circuit according to 6. 8. The control means receives the control signal as an input.
And the output of the input control means is the second logical value and
Only when the control signal is a condition for selecting the normal operation
The first logic value is output.
Outputs the logical value of 2, The output means outputs a signal when the selection signal has the first logical value.
In this case, the first logical value is output by the driving capability I1 and the selection is performed.
When the select signal has the second logical value, the drive capability I1
Outputs the second logical value with sufficiently small driving capability I2
First output means for outputting the output signal from the control means.
A force control signal as an input, and the output control signal
In the case of a logical value, the second logic is determined by the driving capability (I1-I2).
And outputting a value when the output control signal has the second logical value.
The second output means which does not contribute to the output if The first output means and the second output means are connected to the output means.
By driving the outputs of the stages together, the control signal and the
The output signal is output with the driving ability according to the selection signal.
The test circuit according to claim 3, wherein 9. The control means further comprises the control signal
Receiving the second control signal as an input, Receiving the selection signal, the control signal, and the second control signal;
And the control signal is a selection of the normal operation.
Output an inverted logical value of the logical value of the selection signal,
If the control signal is a selection of the test operation, the second
The second logical value when the control signal is at the first logical value.
And when the second control signal has the second logical value,
A first control for outputting an inverted logical value of a logical value of the selection signal;
Means, Receiving the selection signal, the control signal, and the second control signal;
And the control signal is a selection of the normal operation.
Output an inverted logical value of the logical value of the selection signal,
If the control signal is a selection of the test operation, the second
When the control signal is at the first logical value,
Output the inverted logical value of the logical value, and the second control signal
A second system for outputting the first logical value when the logical value is 2.
Means Prepared, The output means receives the selection signal as an input and outputs a driving capability I2
Output means for outputting the same logical value as the selection signal
When, The output of the first control means is input and the first control
When the output of the means is the first logical value, the driving capability I
2 with the driving capability I1 that is sufficiently larger than the second logical value.
And the output of the first control means is the second logical value.
A second output means that does not contribute to the output in the case of The output of the second control means is input and the second control
When the output of the means is the second logical value, the driving capability I
The first logical value with a driving capability I1 that is sufficiently larger than
And the output of the second control means is the first logical value.
In the case of, there is provided third output means that does not contribute to the output, The first output means, the second output means, and the third
Output means for driving the output of the output means together.
The control signal, the second control signal, and the selection signal
The output signal is output with the driving ability according to the signal.
4. The test circuit according to claim 3, wherein