JP2012059340A - Test method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a test method capable of testing a device to be tested by using a simple tester.SOLUTION: The method of testing a plurality of devices to be tested (211-214) each having a storage circuit, with a test pattern divided and stored in the storage circuits of the plurality of devices to be tested, includes a test pattern read-out step where test patterns (DT0-DT3) are read out from the storage circuits of the plurality of devices to be tested and are merged, and the same test patterns (PTN0-PTN3) are supplied to the plurality of devices to be tested; and a test step where the plurality of devices to be tested are simultaneously tested with the use of the same test patterns that are supplied.

Description

  The present invention relates to a test method.

  One semiconductor chip includes a semiconductor chip having a memory circuit and a logic circuit. When testing such a semiconductor chip, the memory circuit and the logic circuit are tested using different testers, and the cost increases due to the replacement of the tester.

  In addition, the logic circuit has a larger number of pins used for the test than the memory circuit. For this reason, the logic circuit test by the logic circuit tester has a smaller number of devices to be tested at the same time than the memory circuit test by the memory circuit tester, and the test cost per semiconductor chip increases. It has become.

  Further, the storage capacity of the nonvolatile memory circuit of the device under test is limited, and it is difficult to store the contents of all the steps of the test pattern in a lump.

  Further, there is known an LSI capable of performing a function test at an actual operation speed of a functional block inside the LSI using a memory built in the LSI (see, for example, Patent Document 1).

  There is also known a semiconductor integrated circuit including a semiconductor memory and a test circuit for the semiconductor memory, that is, a test pattern generation circuit for generating a test pattern (see, for example, Patent Document 2).

JP 2001-91586 A Japanese Patent No. 3867862

  An object of the present invention is to provide a test method capable of testing a device under test using a simple tester.

  The test method is a test method for a plurality of devices under test each having a memory circuit, and a test pattern is divided and stored in the memory circuits of the plurality of devices under test. A test pattern reading step of reading a test pattern from the storage circuit, merging the read test patterns of the plurality of devices under test to supply the same test pattern to the plurality of devices under test, and the same test pattern supplied And testing the plurality of devices under test simultaneously using

  A large-capacity test pattern can be stored by dividing the test pattern and storing it in a plurality of devices under test. Further, by storing the test pattern in the device under test, a plurality of devices under test can be simultaneously tested with a simple tester.

3 is a flowchart illustrating a test method for a device under test according to an embodiment. It is a figure which shows the structural example of a to-be-tested device and its test apparatus. It is a figure which shows the structural example of a device under test. It is a flowchart which shows the detail of the 1st test step of a non-volatile memory circuit. It is a figure which shows the 1st test of a non-volatile memory circuit. 6A to 6C are diagrams illustrating a first test of the nonvolatile memory circuit. FIG. 7A is a diagram showing a configuration example of the device under test, and FIG. 7B is a timing chart showing a data write processing example. It is a flowchart which shows the detail of the test step of a logic circuit. It is a figure which shows the test of a logic circuit. It is a figure which shows the structural example of a device under test. It is a timing chart which shows the example of a process of a logic test. It is a figure which shows the structural example of a non-volatile memory circuit controller and a non-volatile memory circuit. It is a figure which shows the structural example of an expected value comparison circuit. It is a flowchart which shows the detail of the 2nd test step of a non-volatile memory circuit. 15A to 15C are diagrams illustrating a second test of the nonvolatile memory circuit. FIG. 16A is a diagram illustrating a configuration example of a device under test, and FIG. 16B is a timing chart illustrating a processing example of logic test result determination. It is a figure which shows the other example of a structure of a to-be-tested device and its test apparatus.

  FIG. 1 is a flowchart illustrating a test method for a device under test according to an embodiment. The device under test is a semiconductor chip on which a nonvolatile memory circuit and a logic circuit are mounted. In step S101, the tester performs a first test of the nonvolatile memory circuit in the device under test. Then, the tester writes a test pattern for testing the logic circuit in the device under test into the nonvolatile memory circuit in the device under test. Next, in step S102, the tester tests the logic circuit in the device under test, and writes the test result in the nonvolatile memory circuit in the device under test. Next, in step S103, the tester performs a second test of the nonvolatile memory circuit in the device under test. Then, the tester reads the test result written in the nonvolatile memory circuit in the device under test, and determines whether the test result is acceptable or not.

  FIG. 2 is a diagram illustrating a configuration example of a device under test and a test apparatus thereof. The devices under test (DUT) 211 to 214 are a plurality of semiconductor chips on the same semiconductor wafer or a plurality of semiconductor chips in a package state, and are semiconductor chips having the same configuration. The devices under test 211 to 214 have a nonvolatile memory circuit and a logic circuit. The tester 201 is connected to the four devices under test 211 to 214 via the test jig 202 and can test the four devices under test 211 to 214 simultaneously. The tester 201 supplies a control signal 221 to the devices under test 211 to 214. The control signal 221 includes a clock signal, a reset signal, and a signal for instructing writing / reading of the nonvolatile memory circuit in the devices under test 211 to 214. The tester 201 reads data DT0 to DT3 from the nonvolatile storage circuits in the four devices under test 211 to 214, respectively, and supplies them to the four devices under test 211 to 214 as test patterns PTN0 to PTN3, respectively. Different test pattern data DT0 to DT3 are written in the nonvolatile memory circuits in the four devices under test 211 to 214. Test patterns PTN0 to PTN3 are the same test patterns obtained by merging data DT0 to DT3. The test patterns PTN0 to PTN3 supplied to the four devices under test 211 to 214 are all the same. As a result, the tester 201 can simultaneously test four devices under test 211 to 214 using the same test patterns PTN0 to PTN3. For example, the storage capacity of the nonvolatile memory circuit of each of the devices under test 211 to 214 is smaller than the capacity for storing all the test patterns PTN0 to PTN3. Therefore, all the test patterns cannot be stored in the nonvolatile memory circuit of one device under test 211. Therefore, the test pattern is divided into a plurality of devices under test 211 to 214 and stored as data DT0 to DT3. In the test, the data DT0 to DT3 are merged to generate test data PTN0 to PTN3, and the four devices under test 211 to 214 are tested simultaneously. The test data PTN0 to PTN3 are each composed of, for example, 4 bits and are the same test data. The data DT0 is the 0th bit data of the test data PTN0 to PTN3, the data DT1 is the 1st bit data of the test data PTN0 to PTN3, the data DT2 is the second bit data of the test data PTN0 to PTN3, and the data DT3 is the test data This is the third bit data of PTN0 to PTN3.

  FIG. 3 is a diagram illustrating a configuration example of the device under test 211. The devices under test 212 to 214 also have the same configuration as the device under test 211. The device under test 211 includes a nonvolatile memory circuit 301, a test circuit 302, and a logic circuit 303. As shown in FIG. 2, the device under test 211 receives the control signal 221 and the test pattern PTN0 and outputs data DT0. The control signal 221 is a control signal from the tester 201, and includes an input fixing signal due to power connection of the signal terminal. The test circuit 302 reads the data DT0 from the nonvolatile memory circuit 301 in response to the read instruction of the control signal 221. Further, the test circuit 302 receives the test pattern PTN0 and outputs the test pattern 321 to the logic circuit 303. The logic circuit 303 operates using the test pattern 321 as an input signal, and outputs an operation result signal 322 to the test circuit 302. The test circuit 302 determines whether or not the operation result signal 322 matches the expected value, and writes the test result signal 313 into the nonvolatile memory circuit 301.

  FIG. 5 is a diagram showing a first test of the nonvolatile memory circuit in step S101 of FIG. On the semiconductor wafer, a plurality of devices under test 211 are arranged in the first column, a plurality of devices under test 212 are arranged in the second column, and a plurality of devices under test 213 are arranged in the third column. Are arranged, and a plurality of devices under test 214 are arranged in the fourth column. The devices under test 211 to 214 may be packages instead of semiconductor wafers. The tester 201 stores a test pattern for a nonvolatile memory circuit and a test pattern for a logic circuit. 2 has a path for connecting the devices under test 211 to 214, but the jig 202 of FIG. 5 does not need to connect the devices under test.

  First, the tester 201 simultaneously tests two devices under test 211 using the test pattern for the nonvolatile memory circuit via the jig 202. In an actual test, several to several hundreds are tested simultaneously. In the semiconductor wafer test, the handler moves the jig to an appropriate position on the semiconductor wafer, and in the package test, the handler moves the device under test 211 to an appropriate position on the jig. FIG. 5 shows an example of a semiconductor wafer test, but the same can be realized by a package test. Next, the tester 201 writes the data DT0 of the 0th bit among the test patterns PTN0 to PTN3 for the logic circuit to the two devices under test 211 via the jig 202. Similarly, in the device under test 211, the nonvolatile memory circuit is tested and the 0th bit data DT0 is written in units of two. Further, the device under test 212 performs a test of the nonvolatile memory circuit and writing of the first bit data DT1 in units of two. In addition, the device under test 213 performs the test of the nonvolatile memory circuit and the writing of the second bit data DT2 in units of two. The device under test 214 performs a test of the nonvolatile memory circuit and writing of the third bit data DT3 in units of two. The same data DT0 is written to all the plurality of devices under test 211 in the first column, and the same data DT1 is written to all the plurality of devices under test 212 in the second column. The same data DT2 is written to all the test devices 212, and the same data DT3 is written to all the plurality of devices under test 213 in the fourth column. A method in which the tester 201 sequentially tests the devices under test 211 to 214 will be described with reference to FIGS.

  6A to 6C are diagrams illustrating a first test of the nonvolatile memory circuit in step S101 of FIG. FIG. 6A shows a case where the jig position j is 0 and the write bit n is 0. Since the write bit n is 0, the device under test 211 to which the data DT0 of the 0th bit is written is selected. Since the jig position j is 0, the jig 202 moves to the positions of the two devices under test 211 on the upper side of the drawing. Thereafter, the tester 201 performs the test of the nonvolatile memory circuit and the writing of the test data DT0 of the 0th bit to the two devices under test 211 on the upper side of the drawing via the jig 202.

  FIG. 6B shows a case where the jig position j is 1 and the write bit n is 0. Since the write bit n is 0, the device under test 211 to which the data DT0 of the 0th bit is written is selected. Since the jig position j is 1, the jig 202 moves to the positions of the two devices under test 211 in the center of the figure. Thereafter, the tester 201 performs a test of the nonvolatile memory circuit and writing of the test data DT0 of the 0th bit to the two devices under test 211 in the center part of the figure via the jig 202.

  Similarly, when the jig position j is 2 and the write bit n is 0, the tester 201 tests the nonvolatile memory circuit with respect to the two devices under test 211 on the lower side of the figure via the jig 202. And the test data DT0 of the 0th bit is written.

  When the jig position j is 0 to 2 and the write bit n is 1, the tester 201 performs the test of the nonvolatile memory circuit and the first bit with respect to the device under test 212 via the jig 202 in units of two. The test data DT1 is written.

  When the jig position j is 0 to 2 and the write bit n is 2, the tester 201 tests the nonvolatile memory circuit and the second bit with respect to the device under test 213 via the jig 202 in units of two. The test data DT2 is written.

  When the jig position j is 0 to 2 and the write bit n is 3, the tester 201 performs a nonvolatile memory circuit test and third bit on the device under test 214 via the jig 202 in units of two. The test data DT3 is written.

  FIG. 6C shows the case where the jig position j is 2 and the write bit n is 3. Since the write bit n is 3, the device under test 214 to which the third bit data DT3 is written is selected. Since the jig position j is 2, the jig 202 is moved to the positions of the two devices under test 214 on the lower side of the figure. Thereafter, the tester 201 performs the test of the nonvolatile memory circuit and the writing of the test data DT3 of the third bit to the two devices under test 214 on the lower side of the drawing through the jig 202.

  FIG. 4 is a flowchart showing details of the first test step of the nonvolatile memory circuit in step S101 of FIG. In step S401, the tester 201 and the handler set 0 to the jig position j and the write bit n, respectively. Next, in step S402, the jig 202 is selected as the positions of the two devices under test 211 to 214 corresponding to the jig position j and the write bit n. Next, in step S403, the tester 201 tests the nonvolatile memory circuit with respect to the two selected devices under test 211 to 214. Next, in step S404, the tester 201 writes the nth bit test pattern data DTn to the nonvolatile memory circuits of the two selected devices under test 211-214. Next, in step S405, the tester 201 and the handler increment the jig position j. Next, in step S406, the tester 201 and the handler check whether the jig position j is larger than the maximum jig position J (for example, 2). If it is equal to or smaller than the maximum jig position J, the process returns to step S402. If it is larger than the maximum jig position J, the process proceeds to step S407. In step S407, the tester 201 and the handler increment the write bit n. Next, in step S408, the tester 201 and the handler check whether or not the write bit n is larger than the maximum bit N (for example, 3). If it is less than or equal to the maximum bit N, the process returns to step S402, and if it is greater than the maximum bit N, the process ends. By the above processing, the test pattern can be divided and written in the nonvolatile memory circuits of the devices under test 211 to 214.

  As described above, in the first test of the nonvolatile memory circuit, the nonvolatile memory circuit is first tested. Thereafter, a test pattern for logic test is written in the nonvolatile memory circuit. A plurality of bits (N bits) are required to input the test pattern of the logic circuit. Which data DT0 to DT3 is written to which device under test 211 to 214 is stored in the tester 201 and the handler.

  7A is a diagram showing a configuration example of the device under test 211, and FIG. 7B is a timing chart showing a processing example of step S404 in FIG. Although the device under test 211 will be described as an example, the same applies to the devices under test 212 to 214. The device under test 211 includes a nonvolatile memory circuit (macro) 701 and a sequential circuit (internal circuit) 702. The nonvolatile memory circuit 701 receives a write address ADD, test data DT0, a clock signal CLK, and a mode signal TM from the tester 201. A signal 711 is an output signal of the tester 201, and a signal 712 is an input signal of the device under test 211. The nonvolatile memory circuit 701 has a storage capacity of 16 words, for example. One word is 4 bits. That is, the nonvolatile memory circuit 701 can store 16 × 4 = 64 bits of test data DT0. Since each test data PTN0 to PTN3 is 4 bits, a test of 4 bits × 64 cycles can be performed. The signal 711 output from the tester 201 is input as a signal 712 to the device under test 211 after a predetermined time delay. Test data DT0 is written in the nonvolatile memory circuit 701 in synchronization with the clock signal CLK. The test data DT0 and the address ADD to which it is written are output from the tester 201 to the device under test 211 in accordance with the timing when the mode signal TM changes from the read mode to the write mode. In the write mode, test data DT0 is written to the nonvolatile memory circuit 701 based on the write address ADD.

  9A to 9C are diagrams showing the test of the logic circuit in step S102 of FIG. FIG. 9A shows a case where the jig position k is zero. Since the jig position k is 0, the jig 202 is moved to the positions of the four devices under test 211 to 214 in the first row. Thereafter, the tester 201 simultaneously performs a logic test on the four devices under test 211 to 214 in the first row via the jig 202. Specifically, as shown in FIG. 2, the test data DT0 to DT3 are read from the four devices under test 211 to 214, and the same test patterns PTN0 to PT3 are supplied to the four devices under test 211 to 214, respectively. And test the logic circuit.

  FIG. 9B shows a case where the jig position k is 1. Since the jig position k is 1, the jig 202 moves to the positions of the four devices under test 211 to 214 in the second row. Thereafter, the tester 201 simultaneously performs a logic test on the four devices under test 211 to 214 in the second row via the jig 202. Similarly, when the jig position k is 2 to 4, the tester 201 simultaneously performs a logic test on the four devices under test 211 to 214 in the third to fifth rows via the jig 202, respectively.

  FIG. 9C shows the case where the jig position k is 5. Since the jig position k is 5, the jig 202 moves to the positions of the four devices under test 211 to 214 in the sixth row. Thereafter, the tester 201 simultaneously performs a logic test on the four devices under test 211 to 214 in the sixth row via the jig 202.

  FIG. 8 is a flowchart showing details of the logic circuit test step in step S102 of FIG. In step S801, the tester 201 and the handler set 0 to the jig position k. Next, in step S802, the jig 202 is selected as the position of the four devices under test 211 to 214 corresponding to the jig position k. Next, in step S803, the tester 201 reads and merges the 4-bit test data DT0 to DT4 from the selected four devices under test 211 to 214, and selects the same 4-bit test patterns PTN0 to PTN3, respectively. Are supplied to the four devices under test 211 to 214, and the logic circuits of the selected four devices under test 211 to 214 are tested. Next, in step S804, the tester 201 and the handler increment the jig position k. Next, in step S805, the tester 201 and the handler check whether the jig position k is larger than the maximum jig position K (for example, 5). If it is below the maximum jig position K, the process returns to step S802, and if it is larger than the maximum jig position K, the process is terminated.

  As described above, in the test of the logic circuit, the test pattern written in the non-volatile memory circuit is read, and the logic circuit is tested with the read test pattern. The tester 201 may be a simple tester having only the clock signal CLK and some control signals (logic test simple pattern). Therefore, a tester dedicated to the logic circuit is not required, and the tester 201 for testing the logic circuit can be the same as the tester 201 for testing the nonvolatile memory circuit.

  FIG. 10 is a diagram illustrating a configuration example of the device under test 211. The devices under test 212 to 214 also have the same configuration as the device under test 211. The device under test 211 includes a nonvolatile memory circuit 701, a nonvolatile memory circuit controller (test circuit) 1001, an expected value comparison circuit (test circuit) 1002, flip-flops 1011 to 1013, and a combinational logic circuit (internal circuit) 1014. The clock signal CLK, the reset signal RS, and the mode signal TM are input from the tester 201.

  In the above description, the case where the test patterns PTN0 to PTN3 are configured by the 4-bit data DT0 to DT3, respectively, for the four devices under test 211 to 214 has been described as an example. An example in which the test patterns PTN0 to PTN2 are composed of 3-bit data DT0 to DT2 will be described with respect to 211 to 213, respectively. The test pattern PTN0 is composed of 3-bit data DT0 to DT2. Data DT 0 is data read from the device under test 211, data DT 1 is data read from the device under test 212, and data DT 2 is data read from the device under test 213.

  Here, a scan (SCAN) test circuit is shown. Generally, the number of data bits is increased, and a test circuit is configured by scanning, BIST (built-in self test), or the like.

  The nonvolatile memory circuit controller 1001 receives the mode signal TM, the clock signal CLK, and the reset signal RS, reads 1 word (4 bits) of data from the nonvolatile memory circuit 701, and sequentially reads the data of 1 word bit by bit. Output as data DT0 for each cycle. When the reset signal RS is input, the values of the nonvolatile memory circuit controller 1001 and the flip-flops 1011 to 1013 are initialized. The nonvolatile memory circuit 701 enters a read mode by the mode signal TM. Data DT0 is read from the nonvolatile memory circuit 701 in synchronization with the clock signal CLK. The data DT1 and DT2 are also read from the devices under test 212 and 213 similarly to the data DT0.

  The test pattern PTN0 has test data DT0 to DT2. For example, the test data DT0 is scan control data, the test data DT1 is scan input data, and the test data DT2 is expected value data.

  Next, the operation of the scan test circuit will be described. First, 1 is input as the scan control data DT0. Then, the three flip-flops 1011 to 1013 are connected in series, and the scan input data DT1 is sequentially stored in the flip-flops 1011 to 1013. Specifically, data DT1 is stored in three flip-flops 1011 to 1013 in three cycles. Thereby, desired test data can be set in the three flip-flops 1011 to 1013.

  Thereafter, 0 is input as the scan control data DT0. Then, the three flip-flops 1011 to 1013 are connected to the combinational logic circuit 1014 as in the normal use state. The combinational logic circuit 1014 performs a logical operation according to the value of the flip-flop 1013 and writes the operation result in the flip-flop 1013.

  By this scan test, the test data of the scan input data DT1 can be set in the flip-flops 1011 to 1013, the test data can be input to the combinational logic circuit 1014, and the combinational logic circuit 1014 can be tested. The operation result of the combinational logic circuit 1014 is written into the flip-flop 1013. The expected value of the operation result of the combinational logic circuit 1014 when the test data of the scan input data DT1 is input is input as the expected value data DT2.

  The expected value comparison circuit 1002 compares the operation result data AC stored in the flip-flop 1013 and the expected value data DT2, and compares the comparison result data (test result data) AB indicating whether or not the two match with each other. The data is output to the memory circuit 701. Thereafter, the nonvolatile memory circuit 701 enters the write mode by the mode signal TM, and the comparison result data AB is written into the nonvolatile memory circuit 701. The comparison result data AB indicates normal (non-defective product) if the two match, and indicates abnormal (defective) if the two are different.

  FIG. 11 is a timing chart showing an example of processing in step S803 in FIG. A signal 1101 is an output signal of the tester 201 and includes a clock signal CLK and a mode signal TM. A signal 1102 is an input signal of the devices under test 211 to 213 and includes a clock signal CLK and a mode signal TM. The data DT0 is data read from the device under test 211, the data DT1 is data read from the device under test 212, and the data DT2 is data read from the device under test 213. The test pattern PTN0 is a pattern input to the device under test 211, the test pattern PTN1 is a pattern input to the device under test 212, and the test pattern PTN2 is a pattern input to the device under test 213.

  In the logic test, the clock signal CLK and the mode signal TM are input from the tester 201 to the devices under test 211 to 213. The clock signal CLK and the mode signal TM are delayed by the time for propagation between the tester 201 and the devices under test 211 to 213. When the initialization mode is input to the devices under test 211 to 213, the flip-flops 1011 to 1013 are initialized by the reset signal RS. When the device under test 211 to 213 is in the test mode and the clock signal CLK is input, the reset is released, the mode signal TM enters the read mode, the data in the nonvolatile memory circuit 701 is read, and the test pattern is read. Output as data DT0 to DT2. The devices under test 211 to 213 to be tested simultaneously output data DT0, DT1, and DT2 of 0, 1, and 2 bits of the test pattern, respectively. The devices under test 211 to 213 input test patterns PTN0 to PTN2, respectively. Test patterns PTN0 to PTN2 are the same pattern and have data DT0, DT1, and DT2. Data DT0 to DT2 output from the devices under test 211 to 213 are delayed by the time of propagation through the test jig 202 and input to the devices under test 211 to 213 as test patterns PTN0 to PTN2. All the devices under test 211 to 213 to be tested simultaneously read the 3-bit test patterns PTN0 to PTN2 at the timing of the next clock signal CLK. The input test patterns PTN0 to PTN2 of all the devices under test 211 to 213 are the same pattern. When the write mode is input as the test mode TM, the devices under test 211 to 213 write the logical test result data AB into the nonvolatile memory circuit 701 in the devices under test 211 to 213.

  FIG. 12 is a diagram illustrating a configuration example of the nonvolatile memory circuit controller 1001 and the nonvolatile memory circuit 701 in FIG. The nonvolatile memory circuit controller 1001 includes an incrementer 1201, a 6-bit counter 1202, a multiplexer 1203, and a frequency divider 1204. Under the control of the nonvolatile memory circuit controller 1001, data in the nonvolatile memory circuit 701 is read and written. The 6-bit counter 1202 is initialized by the reset signal RS, and the bit value counted up by the incrementer 1201 is updated in synchronization with the clock signal CLK. The upper 4 bits of the 6-bit counter 1202 are used as a read or write address for the nonvolatile memory circuit 701. For the lower 2 bits of the 6-bit counter 1202, 1-bit data is selected from the 4-bit output signal of the nonvolatile memory circuit 701 by the multiplexer 1203, and is output to the test jig 202 as the test pattern data DT0. Since the nonvolatile memory circuit 701 stores one word (4 bits) at one address, it outputs 4-bit data to the multiplexer 1203 for one address. Since the value of the 6-bit counter 1202 is counted up, the multiplexer 1203 sequentially outputs 4-bit data by 1-bit data by parallel-serial conversion. This 4-bit data corresponds to a test pattern of 4 cycles. The nonvolatile memory circuit 701 performs reading in units of 1 word (4 bits) according to a 4-bit address. When the test mode TM is the read mode, the non-volatile memory circuit 701 sequentially reads the test pattern data DT0 according to the clock signal that is ¼ cycle by the frequency divider 1204. When the mode signal TM is in the write mode, the comparison result data AB is written into the nonvolatile memory circuit 701.

  FIG. 13 is a diagram illustrating a configuration example of the expected value comparison circuit 1002 of FIG. The expected value comparison circuit 1002 includes an exclusive OR circuit 1301, an OR circuit 1302, and a flip-flop 1303. The value of the flip-flop 1303 becomes 0 upon initialization by the reset signal RS. The exclusive OR circuit 1301 outputs an exclusive OR signal of the operation result data AC and the expected value data DT2. The exclusive OR signal becomes 0 if the operation result data AC and the expected value data DT2 are the same, and becomes 1 if the operation result data AC and the expected value data DT2 are different. The OR circuit 1302 outputs a logical sum signal of the output signal of the exclusive OR circuit 1301 and the output signal of the flip-flop 1303 to the flip-flop 1303. The flip-flop 1303 outputs the comparison result data AB. If the exclusive OR circuit 1301 outputs 1 even in one of the multiple cycles of the logic test, the value of the flip-flop 1303 is replaced with 1. If the calculation result data AC and the expected value data DT2 match for all the test patterns, the comparison result data AB becomes 0, and if the calculation result data AC and the expected value data DT2 do not match for at least one test pattern. The comparison result data AB is 1. The comparison result data AB is finally written into the nonvolatile memory circuit 701.

  FIGS. 15A to 15C are diagrams showing a second test of the nonvolatile memory circuit in step S103 of FIG. The tester 201 has a logic test determination pattern and a nonvolatile memory circuit test pattern. This test may be a semiconductor wafer test or a package test. 2 has a path for connecting the devices under test 211 to 214, but the jig 202 of FIGS. 15A to 15C does not need to connect the devices under test.

  FIG. 15A shows a case where the jig position k is zero. Since the jig position k is 0, the jig 202 moves to the positions of the two devices under test 211 on the upper side of the drawing. Thereafter, the tester 201 determines the logical test result and tests the nonvolatile memory circuit for the two devices under test 211 on the upper side of the drawing via the jig 202. The logical test result is determined by comparing the comparison result data AB in the nonvolatile memory circuit 701.

  FIG. 15B shows a case where the jig position k is 1. Since the jig position k is 1, the jig 202 moves to the positions of the two devices under test 211 in the center of the figure. Thereafter, the test 201 performs determination of the logical test result and the test of the nonvolatile memory circuit with respect to the two devices under test 211 in the center portion of the drawing via the jig 202.

  Similarly, when the jig position k is 2, the determination of the logical test result of the two devices under test 211 on the lower side of the figure and the test of the nonvolatile memory circuit are performed. Similarly, when the jig position k is 3 to 5, the tester 201 determines the logical test result of the device under test 212 and tests the nonvolatile memory circuit. Similarly, when the jig position k is 6 to 8, the tester 201 determines the logical test result of the device under test 213 and tests the nonvolatile memory circuit. Similarly, when the jig position k is 9 to 11, the tester 201 determines the logical test result of the device under test 214 and tests the nonvolatile memory circuit.

  FIG. 15C shows a case where the jig position k is 11. Since the jig position k is 11, the jig 202 moves to the positions of the two devices under test 214 on the lower side of the figure. Thereafter, the test 201 determines the logical test result and tests the nonvolatile memory circuit for the two devices under test 214 on the lower side of the drawing via the jig 202.

  FIG. 14 is a flowchart showing details of the second test step of the nonvolatile memory circuit in step S103 of FIG. In step S1401, the tester 201 and the handler set 0 to the jig position k. Next, in step S1402, the jig 202 is selected as the position of the two devices under test 211 to 214 corresponding to the jig position k. Next, in step S1403, the tester 201 reads the comparison result data AB from the two selected devices under test 211 to 214, and determines the logical test result. If the comparison result data AB is 0, it is determined to be normal, and if the comparison result data AB is 1, it is determined to be abnormal. If the test result is normal, the process proceeds to step S1404. In step S1404, the tester 201 tests the nonvolatile memory circuit 701 for the two selected devices under test 211 to 214. For example, the test in step S403 in FIG. 4 is a low temperature test, and the test in step S1404 in FIG. 14 is a high temperature test. Alternatively, the test in step S403 in FIG. 4 is a semiconductor wafer test, and the test in step S1404 in FIG. 14 is a package test. Next, in step S1405, the tester 201 and the handler increment the jig position k. Next, in step S1406, the tester 201 and the handler check whether the jig position k is larger than the maximum jig position K (for example, 11). If it is below the maximum jig position K, the process returns to step S1402, and if it is larger than the maximum jig position K, the process is terminated.

  FIG. 16A is a diagram illustrating a configuration example of the device under test 211, and FIG. 16B is a timing chart illustrating a processing example of step S1403 in FIG. Although the device under test 211 will be described as an example, the same applies to the devices under test 212 to 214. The device under test 211 includes a nonvolatile memory circuit 701 and a sequential circuit (internal circuit) 702. The nonvolatile memory circuit 701 inputs the 4-bit read address ADD, the clock signal CLK, and the mode signal TM from the tester 201, and reads the comparison result data AB. A signal 1601 is an output signal of the tester 201, and a signal 1602 is an input signal of the device under test 211. The nonvolatile memory circuit 701 has a storage capacity of 16 words, for example. One word is 4 bits. The signal 1601 output from the tester 201 is input as a signal 1602 to the device under test 211 after a certain time delay. The nonvolatile memory circuit 701 reads the comparison result data AB in synchronization with the clock signal CLK. When the mode signal TM enters the read mode, the read address ADD is output from the tester 201 to the device under test 211. In the read mode, the nonvolatile memory circuit 701 reads the comparison result data AB based on the read address ADD. The tester 201 determines whether the logical test result is normal or abnormal based on the read comparison result data AB.

  Next, the configuration of the tester 201 will be described. The control signal 221 given from the tester 201 to the devices under test 211 to 214 at the time of the logic test is limited to only the clock signal CLK and a part of the control signals, thereby reducing the cost of the tester 201 for the logic test. And can also be used as the tester 201 of the nonvolatile memory circuit. At this time, unused input pins of the devices under test 211 to 214 are fixed to a high level or a low level by the test jig 202.

  Note that the second test of the nonvolatile memory circuit in step S103 of FIG. 1 may be deleted. Hereinafter, the logic circuit test is referred to as a logic test. When the test of the logic circuit in step S102 in FIG. 1 is performed, the tester 201 has the expected value data DT2, and the comparison result data AB output from the devices under test 211 to 214 is compared with the expected value data DT2. / Determine defective products. Thereby, it is not necessary to determine the logical test result in the second test of the nonvolatile memory circuit in step S103 of FIG.

  FIG. 17 is a diagram showing another configuration example of the device under test and its test apparatus. FIG. 17 is obtained by adding a device under test 215 that performs only a logical test without storing a logical test pattern to FIG. Hereinafter, the points of FIG. 17 different from FIG. 2 will be described. The devices under test 211 to 214 are the same as those in FIG. 2 and store logic test patterns. The device under test 215 does not store the logic test pattern, and performs the logic test by inputting the logic test pattern read from the devices under test 211 to 214. The logic test method for the device under test 215 is the same as the logic test method for the devices under test 211 to 214. That is, the tester 201 reads the same logical test pattern read and merged from the devices under test 211 to 214 into the device under test 215 that does not store the logical test pattern in addition to the devices under test 211 to 214 that store the logical test pattern. Supply. Then, the tester 201 uses the same logical test pattern read from the devices under test 211 to 214 and merges the devices under test 211 to 214 that store the logical test pattern and the devices under test 215 that do not store the logical test pattern at the same time. test. As a result, the number of devices under test 211 to 215 that perform logical tests simultaneously can be increased. Also, a plurality of devices under test 215 that do not store logic test patterns are provided, and in the package test, a device under test 211 that stores logic test patterns by replacing only the device under test 215 that does not store logic test patterns and performing a logic test. The number of ~ 214 can be reduced.

  As described above, since the capacity of the logical test pattern is larger than the capacity of the nonvolatile memory circuit 701, the logical test pattern is divided and stored in the nonvolatile memory circuits 701 of the plurality of devices under test 211 to 214. A large-capacity test pattern can be stored by dividing the test pattern and storing it in a plurality of devices under test 211 to 214. The tester 201 reads and merges the logic test patterns from the devices under test 211 to 214 via the test jig 202, and performs a logic test of the devices under test 211 to 215 based on the same logic test pattern merged. By storing test patterns in the devices under test 211 to 214, a plurality of devices under test 214 to 215 can be simultaneously tested with a simple tester 201. Accordingly, the tester 201 may be a simple tester, and the same tester 201 as the nonvolatile memory circuit 701 can be used. Therefore, the tester for the nonvolatile memory circuit 701 and the tester for the logic test can be used. Compared with the case of using different ones, the cost of changing the tester can be reduced. In addition, since the number of devices under test 211 to 215 to be logically tested can be increased at the same time, the test cost per device under test 211 to 215 can be reduced.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

201 Tester 202 Test jig 211 to 215 Device under test 701 Nonvolatile memory circuit 1001 Nonvolatile memory circuit controller 1002 Expected value comparison circuit 1011 to 1013 Flip-flop 1014 Combinational logic circuit

Claims (4)

A test method for a plurality of devices under test each having a memory circuit,
A test pattern is divided and stored in the memory circuits of the plurality of devices under test, the test patterns are read from the memory circuits of the plurality of devices under test, and the test patterns of the plurality of devices under test are merged A test pattern reading step for supplying the same test pattern to the plurality of devices under test;
And a test step of simultaneously testing the plurality of devices under test using the same supplied test pattern.   2. The test method according to claim 1, further comprising a test pattern writing step of dividing and writing the test pattern into the memory circuits of the plurality of devices under test before the test pattern reading step.   3. The test according to claim 1, further comprising a test result writing step of writing test results of the plurality of devices under test into storage circuits of the plurality of devices under test, respectively, after the test step. Method. The test pattern reading step supplies the merged same test pattern to a device under test that does not store the test pattern, in addition to a plurality of devices under test that store the test pattern,
The test step is characterized by simultaneously testing a plurality of devices under test storing the test pattern and a device under test not storing the test pattern using the merged same test pattern. The test method according to any one of the above.

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