JP2004146612A - Semiconductor integrated circuit and method for measuring amount of supply voltage drop - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To measure the supply voltage drop by a simple method with high accuracy without appreciably increasing the chip size of an integrated circuit. <P>SOLUTION: This integrated circuits includes oscillation circuits 4A to 4E which are arranged in prescribed positions of the integrated circuit 1 to measure the supply voltage drop, and in which oscillation frequencies f of output signals SOA to SOE change according to the drop of the supply voltage Vdd at a prescribed position in the operation time of the integrated circuit 1, and an output part (e.g., an I/O pad for measurement arranged at an I/O circuit part 3) which outputs an output signal of the oscillation circuit or a signal SO according to the output signal to the external to measure the supply voltage drop. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit having means for measuring a power supply voltage drop at a predetermined position in an integrated circuit, and a method for measuring a power supply voltage drop.
[0002]
[Prior art]
In recent large-scale semiconductor integrated circuits in which the power supply voltage is reduced, it is important to predict in advance the amount of power supply voltage drop during operation in order to guarantee reliable circuit operation.
Conventionally, the drop amount of the power supply voltage inside a semiconductor integrated circuit has been obtained by simulation using various CADs (Computer Aided Designs). When the predicted power supply voltage drop is determined, it is reflected in the design of the semiconductor integrated circuit, and the wiring is designed so that the power supply voltage drop is suppressed at important points, or even the low power supply voltage operates reliably. To determine the characteristics of the integrated circuit.
[0003]
[Problems to be solved by the invention]
The above-mentioned power supply voltage drop amount is a simulation value to the last, and is only a guide when an integrated circuit is ideally formed under an assumed process. Therefore, in a recent high-speed, large-scale semiconductor integrated circuit (hereinafter, LSI) having a low power supply voltage, it is necessary to actually measure a power supply voltage drop amount and feed it back to a design.
[0004]
The following two methods are conceivable as a method for measuring the amount of drop of the power supply voltage at a necessary portion of the actually formed semiconductor integrated circuit.
[0005]
First, a pad for setting up a probe for measurement is prepared beforehand at a position in the LSI chip where the amount of power supply voltage drop is to be checked, and the operation test is performed by setting up a probe on the above-mentioned pad for the LSI in a wafer state. A method of examining how much the power supply voltage supplied at a location in the wafer has decreased can be considered.
Second, a comparator for voltage measurement to which a reference voltage is externally provided is prepared at a necessary place in advance at the time of design, and the comparator for voltage measurement is prepared after the LSI is assembled in a wafer state or in a package. A method of examining how much the supplied power supply voltage has been reduced by using this method is also conceivable.
[0006]
However, the method of forming the first measurement pad in advance requires a measurement pad. In forming the measurement pad, it is necessary to secure an extra empty area near a predetermined functional circuit block for obtaining the amount of power supply voltage drop in order to eliminate the influence of the voltage drop of the wiring when measuring a minute voltage difference. . In particular, a pad for setting up a probe occupies a considerably large area, so that a useless area which is not actually used as a semiconductor circuit in an LSI logic circuit or the like is formed. Further, the contact resistance of the probe is large, and it is difficult to accurately measure a minute voltage drop. Further, in a test in a wafer state, it is mainly necessary to individually examine each functional test, and in many cases, the test is not performed in a state similar to that when an LSI is used. In this case, the amount of drop of the power supply voltage in actual use cannot be measured.
[0007]
Further, in the second method using a comparator cell for measuring voltage, since this cell is constituted by an analog circuit, in a digital LSI, adding an analog circuit process only for this purpose requires a process cost. Is not realistic. In an analog circuit, a transistor size for improving accuracy is increased, a cell area is increased, and a large area penalty is incurred. Further, since the determination is made as to whether or not the reference voltage is higher than the given reference voltage, it is necessary to change the reference voltage and perform the measurement many times, which increases the measurement time.
[0008]
These methods are not practical for the above-described reasons, and a technique for accurately measuring a small amount of power supply voltage drop by a simple method without significantly increasing the area of the LSI has been required.
[0009]
The present invention has been made in response to such a demand, and an object of the present invention is to accurately measure a small amount of power supply voltage drop by a simple method without significantly increasing the area of a semiconductor integrated circuit. Is to do.
[0010]
[Means for Solving the Problems]
A semiconductor integrated circuit according to the present invention achieves the above object and is arranged at a predetermined position in an integrated circuit, and outputs an output signal due to a drop in a power supply voltage at the predetermined position during operation of the integrated circuit. An oscillation circuit for measuring the power supply voltage drop amount at which the oscillation frequency changes, and an output unit for measuring the power supply voltage drop amount for outputting the output of the oscillation circuit or a signal corresponding to the output to the outside.
[0011]
In the present invention, preferably, the oscillation circuit includes a so-called ring oscillator.
In the present invention, preferably, the plurality of oscillation circuits are dispersedly arranged at predetermined positions in the integrated circuit, and each of the plurality of oscillation circuits has a control input for controlling start and stop of oscillation, There is further provided a decoder connected to the control inputs of the plurality of oscillation circuits, for selecting and oscillating a specific oscillation circuit among the plurality of oscillation circuits in accordance with the input selection signal.
[0012]
A method for measuring a power supply voltage drop amount according to the present invention is intended to achieve the above-described object, and is a measurement method for measuring a power supply voltage drop amount at a predetermined position in a semiconductor circuit. The oscillation circuit for measuring the power supply voltage drop amount arranged at the position is oscillated by changing the applied power supply voltage value in a non-operating state in which the other parts of the semiconductor circuit are not operated, and the oscillation frequency and the power supply voltage value are Determining the relationship, measuring the oscillation frequency of the oscillation circuit in an operating state of the semiconductor circuit to which a predetermined power supply voltage value is applied, and determining the relationship between the oscillation frequency and the power supply voltage value determined in the non-operational state. Calculating the amount of drop in the power supply voltage at the oscillation frequency in the operating state from the above.
[0013]
According to the semiconductor integrated circuit of the present invention, the oscillation circuit is provided in advance at a position where the amount of drop in the power supply voltage is to be obtained. A ring oscillator suitable as an oscillation circuit has a configuration in which a plurality of logic gate circuits including an odd number of inverted logic gate circuits (inverters) are connected in a ring shape, and is formed by a so-called digital integrated circuit process. Further, the semiconductor integrated circuit has an output section for measuring a power supply voltage drop amount for outputting an output of the oscillation circuit or a signal corresponding to the output to the outside.
[0014]
According to the method of measuring the power supply voltage drop amount of the present invention, the oscillation circuit is oscillated while changing the power supply voltage in a non-operation state in which other circuit parts around the oscillation circuit are not operated, and the oscillation frequency and the power supply voltage are Measure the relationship. Thereafter, the semiconductor circuit is operated while a predetermined power supply voltage is applied, and the oscillation frequency of the oscillation circuit is measured in this operation state. In the operating state, a power supply voltage drop occurs because circuits around the oscillation circuit are operating dynamically, and a deviation occurs from the relationship between the oscillation frequency and the power supply voltage obtained in the non-operating state. That is, normally, when the state shifts from the non-operation state to the operation state, the oscillation frequency decreases, and the power supply voltage value actually applied to the circuit differs. The power supply voltage difference between the operating state and the non-operating state at the predetermined oscillation frequency is the required power supply voltage drop amount during the operation.
In this measurement, the frequency or cycle of the output signal of the oscillation circuit output from the output unit for measuring the power supply voltage drop is measured. Even if the output unit is separated from the oscillation circuit and a signal delay occurs, the measurement of the frequency and the period can be accurately performed.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of the present invention, in which a ring oscillator (hereinafter, referred to as a ROSC circuit) is used as an oscillation circuit, will be described with reference to the drawings.
[0016]
FIG. 1 is a conceptual diagram of a semiconductor integrated circuit according to an embodiment of the present invention in which five ROSC circuits are distributed and arranged.
A semiconductor integrated circuit (hereinafter, LSI) 1 illustrated in FIG. 1 is a digital IC, and is roughly composed of an internal logic circuit unit 2 and an input / output circuit unit 3 therearound.
Although not shown, the input / output circuit unit 3 includes I / O pads to which various I / O pins are connected, input / output circuits (such as buffers), and power supply circuits.
Although not shown, the internal logic circuit unit 2 is provided with necessary functional blocks including a CPU and the like according to the type of the LSI, and a memory unit such as a ROM and a RAM is provided as necessary. I have.
[0017]
In the LSI according to the present embodiment, a plurality of oscillation circuits, for example, a plurality of ROSC circuits are provided in the internal logic circuit unit 2.
The number, location, and oscillation frequency of the oscillation circuits are arbitrary. An oscillation circuit that oscillates at a specific frequency can be arranged near a block where the amount of drop of the power supply voltage is to be measured. Further, when it is desired to simply examine the distribution of the power supply voltage drop amount in the LSI, a plurality of oscillation circuits which oscillate at a predetermined frequency can be evenly arranged in the internal logic circuit unit 2.
[0018]
The example illustrated in FIG. 1 has five ROSC circuits 4A, 4B, 4C, 4D, and 4E. For example, the ROSC circuit 4C is disposed near the center of the internal logic circuit unit 2 and the other four ROSC circuits 4A, 4B, 4D, and 4E are disposed near four corners of the internal logic circuit unit 2. .
A decoder 5 for operating any one of the five ROSC circuits at an arbitrary position in the internal logic circuit unit 2 and a selector for selecting an output signal of the operating ROSC circuit and outputting the selected signal to the outside. 6 are provided. When the decoder 5 operates any one of the five ROSC circuits as in this example, the selector 6 can be omitted. The decoder 5 may operate a plurality of ROSC circuits simultaneously, and in this case, the selector 6 is indispensable. Hereinafter, a case where one of the ROSC circuits is operated by the decoder 5 and the output is selected by the selector 6 will be described as an example.
[0019]
The output of the decoder 5 is connected to each input of the five ROSC circuits 4A to 4E, and each output of the ROSC circuits 4A to 4E is connected to the input of the selector 6. A selection signal S1 for selecting one of the ROSC circuits and outputting the oscillated output signal (hereinafter also referred to as an oscillation output) S0 to the outside is input to the input of the decoder 5 and the control input of the selector 6. .
The decoder 5 selects one of the ROSC circuits 4A to 4E based on the control signal S1 and oscillates at a predetermined frequency. The selector 6 permits the output of the output signal S0 of the selected ROSC circuit (oscillation circuit) or the signal S0 corresponding to the output signal to the outside based on the control signal S1. Here, the “signal corresponding to the output signal of the oscillation circuit” is, as described later, a signal obtained by lowering the frequency of the output signal of the oscillation circuit by a predetermined frequency division ratio, or a predetermined period of time of the output signal of the oscillation circuit. It refers to the output signal of the counter when counting the number of pulses.
[0020]
FIG. 2 is a diagram showing the arrangement position of the ROSC circuit in more detail. FIGS. 3 and 4 are explanatory diagrams of an LSI composed of a general standard cell array.
Normally, a standard cell has a pair of wirings 10d and 11d called "bench" for supplying a power supply voltage Vdd and a reference voltage Vss. In a state where the standard cells are arranged in the LSI, the benches 10d and 11d are formed as parallel wirings long in the horizontal direction in the entire array, for example, as shown in FIG.
A main power supply voltage supply line 10b for supplying the power supply voltage Vdd and a basic reference voltage supply line 11b for supplying the reference voltage Vss are formed around the internal logic circuit section 2 of the LSI. The main power supply voltage supply line 10b is connected to each bench 10d for supplying the power supply voltage Vdd and the power supply voltage supply pad 10a, and the main reference voltage supply line 11b is connected to each bench 11d for supplying the reference voltage Vss and the reference voltage supply pad 11a. Have been. These voltage supply lines (hereinafter, referred to as main lines) 10b and 11b are thick wires having sufficiently low wiring resistance to prevent a voltage drop.
In particular, a large-scale LSI has a reinforcing line for preventing a voltage drop at a position far from the main lines 10b and 11b around the internal logic circuit unit 2 as shown in FIG. 4, for example. In the example shown in FIG. 4, as the reinforcement lines, a power supply voltage reinforcement line 10c that connects the main power supply voltage supply line 10b in the horizontal or vertical direction, and a reference voltage that connects the main reference voltage supply line 11b in the horizontal or vertical direction. And a reinforcing wire 11c. The reinforcing wires 10c and 11c may be arranged only in a direction intersecting with the wiring direction of the bench, that is, in a vertical direction. The reinforcing wires 10c and 11c are usually thinner than the trunk lines 10b and 11b, but are sufficiently thicker than the benches 10d and 11d to reduce wiring resistance. In FIG. 4, illustration of the bench is omitted.
[0021]
The five ROSC circuits 4A to 4E are preferably arranged near the main power supply voltage supply line 10b and the main reference voltage supply line 11b, as illustrated in FIG. Alternatively, the ROSC circuit is arranged near the reinforcement lines 10c and 11c as in the center ROSC circuit 4C shown in the figure. This is a desirable requirement for the purpose of making the voltage drop due to the wiring included in the power supply voltage drop amount to be negligibly small. This is not the case when the circuit scale is small or the resistance of the wiring in a cell called a bench is sufficiently small and the voltage drop due to the wiring hardly affects the measurement accuracy. The arrangement of the oscillation circuit is not limited to the position shown in FIG. 2 as long as it is near the trunk lines 10b and 11b or the reinforcing lines 10c and 11c.
[0022]
ROSC circuits 4A to 4E that oscillate at a desired frequency have at least an odd number of inversion logic circuits. As the ROSC circuits 4A to 4E, for example, circuits in which odd-numbered inversion logic circuits and an arbitrary number of positive logic circuits are logically connected in a ring are used. The circuits connected in a logically circular fashion oscillate by applying a voltage to each logic circuit, and are measured in a semiconductor circuit by increasing or decreasing the number of stages (or the number of elements, signal delay value) of each circuit. An oscillation signal in which a pulse is repeated at a predetermined frequency at a desired position is generated.
[0023]
FIG. 5 is a circuit diagram showing an embodiment of the basic configuration of the ROSC circuits 4A to 4E.
The illustrated ROSC circuits 4A to 4E include cascaded odd-numbered n-stage inverters 41-1, 41-2,..., 41- (n-1), 41-n and one NAND gate circuit 42, And an enable circuit 43. The inverter and the NAND gate circuit are supplied with the power supply voltage Vdd from the main supply voltage supply line or the reinforcement lines 10b and 10c, and supplied with the reference voltage Vss from the reference voltage supply line main line or the reinforcement lines 11b and 11c.
The output of the enable circuit 43 is connected to one input of the NAND gate circuit 42. The enable circuit 43 receives the signal S2 from the decoder 5 that decodes the selection signal S1, and according to the signal S2, an enable signal of “H (high)” level when selected and “L (low)” level when not selected. S3 is output to one input of the NAND gate circuit 42.
[0024]
FIG. 6 is a chart showing an example of correspondence between the ROSC circuit selected by the decoder according to the signals S1 and S2 and the signals.
When the selection signal S1 is 3 bits, there are eight combinations of bits as shown in FIG. When the selection signal S1 is "001", the decoder 5 selects the ROSC circuit 4A. When the selection signal S1 is "010", the ROSC circuit 4B is selected. When the selection signal S1 is "011", the ROSC circuit 4C is selected. The ROSC circuit 4D is selected, and when "101", the ROSC circuit 4E is selected. The signal S2 output from the decoder 5 is a 5-bit signal, and the ROSC circuit 4A is selected when its least significant bit (LSB) becomes "1". Similarly, when "1" is set in the next bit of the LSB, the ROSC circuit 4B is selected, and thereafter, the ROSC circuits 4C, 4D, and 4E are similarly selected. The enable circuit 43 in FIG. 5 sets the output signal S3 to “H” only when the corresponding bit of the signal S2 is set to “1”, and sets the output signal S3 to “L” otherwise, and controls the start and stop of the oscillation. I do.
[0025]
FIG. 7 is a chart showing an example of the correspondence between the ROSC circuit whose output is permitted by the decoder in response to the signal S1 and its output.
As shown in FIG. 7, when the selection signal S1 is "001", the output of the oscillation output SOA of the ROSC circuit 4A is permitted by the selector 6, and the output unit of the present invention (for example, the I / O for measuring the power supply voltage drop amount) is used. Pad) to the outside. Similarly, when the selection signal S1 is “010”, the output of the oscillation output SOB of the ROSC circuit 4B is permitted. When the selection signal S1 is “011”, the output of the oscillation output SOC of the ROSC circuit 4C is permitted. Is "100", the output of the oscillation output SOD of the ROSC circuit 4D is permitted. When the selection signal S1 is "101", the output of the oscillation output SOE of the ROSC circuit 4E is permitted. Become.
[0026]
6 and 7, when the selection signal S1 is other than "000", "110" or "111", the decoder 5 does not select any ROSC circuit and the selector 6 does not permit the output. . In the normal use mode of the LSI, the selection signal S1 is set to “000”, “110” or “111”. On the other hand, in the test mode for measuring the drop amount of the power supply voltage, one of the other five combinations of bits is set.
[0027]
Next, a test method for measuring the drop amount of the power supply voltage will be described.
First, a non-operation state of the test mode is selected. Here, the non-operating state refers to a mode in which peripheral circuits other than the five ROSC circuits 4A to 4E, the decoder 5, and the selector 6 illustrated in FIG. In a non-operating state, the static characteristics (the power supply voltage dependence of the oscillation frequency) of each of the ROSC circuits 4A to 4E are measured.
[0028]
8 and 9 show examples of static characteristics. In the present invention, the term “oscillation frequency” equivalently includes the cycle of the oscillation signal.
FIG. 8 is a graph showing the dependence of the oscillation signal period T [ns] on the power supply voltage Vdd [V]. FIG. 9 is a graph in which the vertical axis of FIG. 8 is converted into the oscillation frequency f [MHz].
As the power supply voltage Vdd supplied to the ROSC circuits 4A to 4E is increased, the oscillation frequency f of the output signals of the ROSC circuits 4A to 4E increases, and accordingly, the cycle T of the pulses of the output signals decreases. In each of the ROSC circuits 4A to 4E, preferably, when a predetermined power supply voltage is applied, the number of stages of the inverter and the total delay amount are set so as to oscillate at the oscillation frequency of the closest functional block. Therefore, in this case, the static characteristics shown in FIG. 8 or FIG. 9 are measured for each of the ROSC circuits 4A to 4E while changing the applied power supply voltage Vdd. At this time, it is desirable to apply the power supply voltage Vdd such that the oscillation frequency changes at the required points of positive and negative with respect to each predetermined oscillation frequency. The measurement result is stored as a table or a characteristic expression in a storage unit in the LSI, for example, in a RAM. The measurement result may be output to the outside each time or collectively.
[0029]
Next, in the test mode, the LSI is operated from a non-operating state to an operating state in which all necessary circuits are normally operated, that is, under conditions such as a normally used power supply voltage and a temperature (for example, room temperature). Here, "all necessary circuits" are all circuits whose normal operation affects the power supply voltage drop during the operation of the ROSC circuit of interest, and is almost irrelevant to the power supply voltage drop. It is OK to stop the circuit function that seems to be.
In such an operation state, the oscillation frequency f (or the oscillation pulse period T) of each of the five ROSC circuits 4A to 4E is measured.
[0030]
In particular, the power supply voltage decreases due to the dynamic operation of the circuit portion connected to the main line having the same power supply voltage, and the ROSC circuit also oscillates at the reduced power supply voltage. Therefore, there is a shift in the operating point on the graph showing the correspondence between the oscillation frequency f and the power supply voltage Vdd, which is determined by the static characteristics. In each ROSC circuit, the unique oscillation frequency is f0, and the voltage applied to the power supply pad 10a (FIG. 2) is Vdd0. At this time, the oscillation frequency f (or cycle T) of the output signal SO of the selector 5 is measured by a tester connected to the pad of the output unit.
If the tester has a frequency counter function, the oscillation frequency f is obtained by counting the number of pulses. If this function is not provided, a counter for counting the number of pulses may be provided at the subsequent stage of the selector 5 or at the output stage of each of the ROSC circuits 4A to 4E. Further, when the oscillation frequency is high, in order to eliminate the necessity of using an expensive tester or to increase the measurement accuracy, a predetermined frequency division ratio is provided at the subsequent stage of the selector 5 or at the output stage of each of the ROSC circuits 4A to 4E. A frequency divider for lowering the frequency may be provided.
[0031]
As a result of this measurement, as shown in FIG. 9, it is assumed that the frequency ft of the output signal SO of the test has decreased from the inherent oscillation frequency f0 by Δf. At this time, the change amount ΔV of the power supply voltage Vdd corresponding to the frequency change amount Δf in the relational expression of FIG. 9 is the drop amount of the power supply voltage Vdd0 to be obtained.
When such measurement is repeated while switching the decoder 5 and the selector 6 according to the selection signal S1, the drop amount ΔV of the power supply voltage can be obtained in all of the five ROSC circuits 4A to 4E.
With the above-described circuit configuration and method, it is possible to measure the amount of drop of the power supply voltage in consideration of the actual operation in the semiconductor integrated circuit.
[0032]
If a process variation or the like is taken into consideration, a method of using a transistor that is resistant to the variation may be used.
For example, even if a circuit having the same configuration is used for each of the ROSC circuits 4A to 4E, depending on the surrounding wiring including the upper and lower layers and the arrangement of the surrounding transistors used for other than the ROSC circuit, or due to process variations. , The characteristics of the respective ROSC circuits 4A to 4E may be significantly different. Therefore, even if the ROSC circuits have the same configuration, the voltage dependency of the oscillation frequency may be different. When it is desired to suppress such characteristic fluctuation as much as possible, a transistor having a large gate length can be used.
[0033]
According to the embodiment of the present invention, the following advantages can be obtained.
First, it is possible to accurately measure the amount of power supply voltage drop in actual operation. That is, even if the output unit is separated from the oscillation circuit and a signal delay occurs, the frequency and the period can be measured accurately, and thus the obtained power supply voltage drop is highly accurate. Therefore, the output section can be provided in the input / output section provided around the integrated circuit in the same manner as a normal input / output (I / O) terminal, and a larger area is not required as much as a pad for setting up a probe.
Second, it is possible to previously form an oscillation circuit having an oscillation frequency equivalent to the operating frequency of a peripheral circuit therein, for example, a required number of ROSC circuits at required locations. For this reason, for example, it is possible to perform a test limited to a functional block whose oscillation frequency is particularly high, or a functional block whose charge / discharge frequency using the power supply voltage supply line is high. Usually, if the amount of drop of the power supply voltage in these limited functional blocks can be monitored, it is often sufficient from the viewpoint of ensuring the safe operation of the whole. Therefore, you don't have to do unnecessary tests.
Third, since the decoder 5 and the selector 6 are provided as means for switching a plurality of oscillation circuits, the number of pads for measurement can be minimized.
Fourth, an odd-stage connected inverter and a ring oscillator using one NAND gate circuit are used as the oscillation circuit. Such a ring oscillator (ROSC circuit) can be constructed as a set of normal standard cells by specially designing only the layers of the input / output lines, so that the design is easy and the occupied area is smaller than that of the comparator of the analog circuit. small. In addition, it can be formed together with other circuits by a digital circuit process. Therefore, an increase in chip cost including design cost and process cost is sufficiently suppressed.
As described above, by using the circuit configuration for measuring the amount of power supply voltage drop and the measuring method according to the present embodiment, it is possible to reduce the quality of the process particularly at the start of the semiconductor process or the result of the power supply wiring design. It is extremely easy to estimate a CAD error when obtaining from a simulation. Further, since the drop amount of the power supply voltage during operation can be accurately measured, this function can be incorporated into an actual semiconductor integrated circuit (product), and the added value can be increased as a product with a test mode.
[0034]
【The invention's effect】
According to the semiconductor integrated circuit and the method for measuring the power supply voltage drop amount according to the present invention, the power supply voltage drop amount can be accurately measured by a simple method without increasing the area of the integrated circuit so much.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a semiconductor integrated circuit according to an embodiment of the present invention having a plurality of oscillation circuits arranged in a dispersed manner.
FIG. 2 is a diagram illustrating an example of an arrangement position of an oscillation circuit (ROSC circuit) in more detail;
FIG. 3 is a diagram showing an example of supply lines of a power supply voltage and a reference voltage of an LSI constituted by a standard cell array.
FIG. 4 is a diagram showing another example of a power supply voltage and a reference voltage supply line of an LSI constituted by a standard cell array.
FIG. 5 is a circuit diagram showing an embodiment of a basic configuration of a ROSC circuit.
FIG. 6 is a table showing correspondence between signals S1 and S2 and a ROSC circuit selected by a decoder;
FIG. 7 is a table showing a correspondence between a ROSC circuit whose output is permitted by a decoder in response to a signal S1 and its output.
FIG. 8 is a graph showing, as an example of static characteristics, the dependency of the cycle of an oscillation signal on the power supply voltage.
FIG. 9 is a graph showing, as an example of static characteristics, the dependence of the oscillation frequency of an output signal on the power supply voltage.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Semiconductor integrated circuit, 2 ... Internal logic circuit part, 3 ... Peripheral circuit part, 4A-4E ... Oscillation circuit, 5 ... Decoder, 6 ... Selector, 10b ... Main line of power supply voltage supply line, 10c ... Power supply voltage supply line Reinforcement line, 11b: Main line of reference voltage supply line, 11c: Reinforcement line of reference voltage supply line, 41-1 etc. Inverted logic circuit, 42 ... Positive logic circuit, 43 ... Enable circuit.

Claims (5)

An oscillation circuit arranged at a predetermined position in the integrated circuit, for measuring a power supply voltage drop amount in which an oscillation frequency of an output signal changes due to a power supply voltage drop at the predetermined position during operation of the integrated circuit;
An output section for measuring a power supply voltage drop amount for outputting an output of the oscillation circuit or a signal corresponding to the output to the outside,
A semiconductor integrated circuit having: 2. The semiconductor integrated circuit according to claim 1, wherein the oscillation circuit has a configuration in which a plurality of logic gate circuits including an odd number of inverted logic gate circuits are connected in a ring. A plurality of the oscillation circuits having a unique oscillation frequency are dispersedly arranged at predetermined positions in the integrated circuit,
Each of the plurality of oscillation circuits has a control input for controlling start and stop of oscillation,
2. The semiconductor integrated circuit according to claim 1, further comprising a decoder connected to the control inputs of the plurality of oscillation circuits, for selecting and oscillating a specific oscillation circuit among the plurality of oscillation circuits in accordance with an input selection signal. If there are a plurality of the specific oscillation circuits to oscillate, further comprising a selector for selecting one of the oscillation circuits according to the selection signal and outputting an output of the selected oscillation circuit or a signal corresponding to the output. 4. The semiconductor integrated circuit according to 3. A measurement method for measuring a drop amount of a power supply voltage at a predetermined position in a semiconductor circuit,
The oscillation circuit for measuring the power supply voltage drop amount arranged at the predetermined position is oscillated by changing the applied power supply voltage value in a non-operating state in which the other parts of the semiconductor circuit are not operated, and the oscillation frequency and the power supply voltage are changed. Determining the relationship with the value;
Measuring an oscillation frequency of the oscillation circuit in an operation state of the semiconductor circuit to which a predetermined power supply voltage value is applied;
A step of obtaining a drop amount of the power supply voltage at the oscillation frequency in the operation state from the above relationship between the oscillation frequency and the power supply voltage value obtained in the non-operation state;
A method for measuring a power supply voltage drop amount including:

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