JP2833537B2 - Integrated circuit test equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an integrated circuit test apparatus, and more particularly to an integrated circuit test apparatus for evaluating the operation of an integrated circuit in a state of a chip or a wafer.

[0002]

2. Description of the Related Art In order to evaluate an integrated circuit on a semiconductor chip or wafer, a conventional integrated circuit test apparatus receives power supplies, clock signals, address signals and input data for the required number of chips and the number of inputs and outputs. 2. Description of the Related Art There is known an LSI tester which supplies a chip or a wafer and determines the output of the chip or the wafer by a determination circuit.

[0003] Known techniques relating to this LSI tester are disclosed, for example, in JP-A-62-243335 and JP-A-2-5.
No. 6947 and JP-A-2-239641. Further, for such a measurement, a device in which a test circuit is provided on a chip or a wafer to be measured is also known.

Hereinafter, a memory tester for measuring a storage element will be described as an example of the LSI tester.

FIG. 5 shows an example of measurement of a wafer to be measured by a conventional memory tester. Conventional memory tester is 100
A memory tester main body 51 operating at MHz and a memory tester measurement station 52 are provided. The memory tester measurement station 52 is provided with a driver comparator 62 and a signal cable 57. The wafer to be measured 55 is placed on a vacuum chuck table 56 on a wafer prober 53 and measured via a probe card 54.

FIG. 6 shows a block configuration of a measurement system of the memory tester. The memory tester main body 51 includes a central processing unit 61 therein, and a memory tester measuring station 52.
A driver / comparator 62 is provided therein. The memory under test 63 is connected to the driver / comparator 62 via signal lines 64, 65 and 66. The driver comparator 62 supplies a high-precision and high-speed clock as the RAS signal and the CAS signal to the memory 63 via the signal lines 64 and 65, and supplies test data via the signal line 66. The driver comparator 62 also determines the data output from the memory under measurement 63 to the signal line 66 with high accuracy.

[0007]

However, the conventional LSI
The tester needs to supply and measure clock signals, address signals, data, etc. with high accuracy and high speed according to the number of chips and the number of inputs and outputs of the integrated circuit under test.
There is a problem that the device becomes complicated and its control becomes difficult. For example, 16M-DRAM with input / output of 8 bits
The control of a memory tester capable of measuring 16 pieces in parallel at 100 MHz has become technically sophisticated, and high-precision parts have to be used, and the price is very expensive. .

An object of the present invention is to provide an integrated circuit test apparatus capable of solving such a problem and measuring an integrated circuit on a chip or a wafer with high accuracy with a small hardware configuration.

[0009]

SUMMARY OF THE INVENTION An integrated circuit test apparatus according to the present invention inputs a power supply and a signal necessary for the operation of an integrated circuit under test formed on a substrate and measures the output. An integrated circuit test apparatus , comprising: a test means, and a semiconductor chip or a wafer on which at least a part of the test means is electrically connected to the integrated circuit to be measured via a contact material , wherein the semiconductor chip Alternatively, the wafer is an integrated circuit test device including a counter receiving a clock signal supplied from the test means ,
The counter receives the clock signal and outputs in synchronization with the clock signal
A first counter for inverting a signal;
In sync with this and in up / down mode
Invert the output signal in synchronization with each of the input clock signals
And a second counter for receiving the clock signal.
Synchronize and receive carry prediction signal from lower bits
And a third counter for inverting the output signal.
Setting the least significant bit (LSB) of the counter to the first count
And the other bits are assigned to the second or third counter.
It is composed of

[0010]

Further, the counter of the integrated circuit test apparatus of the present invention, when counted from the lower bit to the upper bit, ranges from a unit constituted by other than the third counter to a unit constituted by the third counter. May be configured to have the same number of stages.

[0012]

[0013]

[0014]

[0015]

In the following description, a technology using silicon as a semiconductor is assumed, and a semiconductor chip or a wafer on which at least a part of the test means is formed is referred to as a “silicon tester”.

This silicon tester uses n bits (n) for each of m chips (m is a positive integer) from one bit of data for one chip of the integrated circuit under test.
Means for generating data of a positive integer) The integrated circuit under test formed on one wafer is divided into a blocks (a is a positive integer), and one of the blocks is selected for measurement. Means, means for selecting and measuring one chip of the integrated circuit to be measured, and the like.

A part or all of the function of the LSI tester is provided on a semiconductor chip or a wafer to form a silicon tester, which is electrically contacted with the integrated circuit to be measured via a contact material. This eliminates the need to extract all the signals required for the test from the LSI tester via the signal lines. In particular, the hardware of the LSI tester can be simplified by incorporating the functions of a high-precision and high-speed driver and comparator for multiple inputs and outputs in parallel with multiple chips in a silicon tester. Since the silicon tester and the integrated circuit under test are in contact with each other, there is no need to route signal lines,
No expensive drivers are required for silicon testers.

[0019]

FIG. 1 is a view showing an integrated circuit test apparatus according to a first embodiment of the present invention, showing a specific example at a wafer level. In this case, a memory tester 1 operating at 25 MHz and a driver 6 having only one I / O are used to input a power supply and a signal necessary for the circuit to operate to the measured wafer 14 and measure the output. , A signal line cable 7, and a silicon tester wafer 12.

Further, the memory tester 1 has a pattern
A generator 2, input means 3 for determination results of 16 chips having 16 I / O numbers, and an external pattern generator (not shown) other than the memory tester 1 different from the pattern generator 2 are set. Or, there are provided control means 4 for controlling and interlocking means 5 for operating the silicon tester wafer 12 in conjunction with the memory tester 1.

The silicon tester wafer 12 and the wafer 14 to be measured are mounted on separate measuring jigs 11 and are electrically connected to each other via a piezoelectric conductive rubber 13 as a contact material. Silicon tester wafer 24
Is provided with some or all functions for testing.

FIG. 3 shows an example of the configuration of a silicon tester.
Here, an example is shown in which data of only one input is supplied and determination results for the number of memories to be measured are output. This silicon tester includes a multi-chip / bit control circuit 31, a block selection decoder 32, a chip selection decoder 33, p
Double speed control circuit 34, P double speed algorithm circuit 35, self-overcurrent protection circuit 36, alignment circuit 37, on-chip test circuit 38, fail memory circuit 39, current control circuit 40, comparator circuit 41, on-chip capacitor 42, and pad 43 is provided.

The multi-chip / bit conversion control circuit 31 converts the data of one bit (or one input / output) of one chip supplied from the memory tester into a decoder circuit and an exclusive OR circuit for input / output and address. Is used to generate data of m chips (m is a positive integer) and n bits (n is a positive integer). The block select decoder 32 divides the measured wafer into a blocks (a is a positive integer) when the silicon tester measures at the wafer level,
One block is selected as a measurement target. When measuring at the wafer level, the chip selection decoder 33 selects an arbitrary chip on the wafer to be measured. The p-times control circuit 34 includes an up / down counter, and makes the clock frequency supplied from the memory tester p times (p is an integer of 2 or more) using a phase locked loop. When the p-times control circuit 34 operates, the p-times speed algorithm circuit 35 uses the up / down counter and the latch circuit to generate a test pattern after the second cycle of the p-times speed operation that is not supplied from the memory tester. . The self-overcurrent protection circuit 36 uses a flip-flop having a reset function to stop supplying current to a chip in which an overcurrent exceeding the rating flows. Alignment circuit 37
In order to align the pads of the silicon tester and the pads of the chip under test, b pads (b is a positive integer) arranged for arbitrary pads of the chip under test are A DC signal is supplied from the memory tester via the signal switching circuit. The on-chip test circuit 38
A dummy chip circuit corresponding to a part of the function of the chip under test is built in, and the operation of the memory tester is self-diagnosed by measuring the dummy chip circuit. When the measurement result of the chip to be measured is defective, the fail memory circuit 39 holds the contents of the defect by a flip-flop circuit. The current control circuit 40 divides the clock frequency from the memory tester to 1 / c (c is an integer of 2 or more) by a frequency dividing circuit when performing multi-chip parallel measurement of the wafer to be measured at the wafer level. The current is controlled by reducing the speed or by dividing the wafer to be measured into arbitrary blocks and sequentially selecting the blocks. The comparator circuit 41 determines the measurement result of the chip to be measured. The on-chip capacitor 42 operates as a bypass capacitor with the chip to be measured.

All of the above circuits need not be provided on a silicon tester. For example, some circuits can be omitted when measurement is performed on a chip basis.

Next, the P-times speed control circuit 34 of this embodiment
The up / down counter will be described.

The counter of this embodiment is composed of three types of units. That is, a first counter composed of a monostable multivibrator that inverts an output signal in synchronization with the basic clock CLK, and a component of the first counter includes an input clock (the basic clock CLK or the preceding stage) according to the up / down mode. A second counter having an output inversion function based on an output signal from a unit) and a third counter having an output inversion function added to the components of the second counter in accordance with the carry prediction signal CYN from the lower bits. And a counter.

Referring to FIG. 2, the counter of this embodiment includes a first counter 101 as an LSB, a second bit 102 as a second bit, a third counter 103 as a third bit, and a second bit thereafter. , A third counter,..., And a second counter 106 as the MSB.

Next, the operation of this counter will be described. The first counter 101 receives the basic clock CLK as an input clock, and the output signal Cn becomes the input clock of the counter 102 at the next stage. The second counter among the counters of the second and subsequent bits receives the output signal of the preceding stage counter (third counter) as an input clock, and is controlled by the identification signal UPC for switching between the up / down mode. Further, the third counter receives the basic clock CLK and is controlled by the carry prediction signal CYN, and functions as a counter unit only when the carry signal is predicted.

Next, the function of predicting the carry signal will be described.

When the lower bits of the predetermined third counter are all "1" (at the time of the up mode) or all "0" (at the time of the down mode) at a certain time, the next input is performed. The clock predicts carry from the lower bits (at the time of the up mode) or borrows from the upper bits (at the time of the die mode). By utilizing this, it is possible to directly invert the predetermined third counter directly by the input clock. That is, the predetermined third counter can be incremented / decremented without receiving the bit inversion signal of the preceding unit. As a result, the delay time due to the counter unit communication can be reduced because the input clock is handled directly instead of the signal of the state transition transmission to the previous stage as the counter, so that the operation time of the entire counter is improved.

In the generation of the carry prediction signal and the carry information, first, in the up mode, the carry information output from the nearest third counter located at the lower position is "0".
And the carry prediction signal CYN is validated when all the output signals of the units arranged between the third counter outputting the carry signal and itself are "1".
At this time, the carry information is set to “0” and output to the third counter that appears next.

Next, in the down mode, the carry information output from the nearest third counter located at the lower position and the output of the unit disposed between itself and the third counter outputting the carry information. When the signals are all “0”, the carry prediction signal CYN is made valid. Also,
At this time, the carry information is set to “0”, and the third
Output to the counter.

FIG. 4 is a timing chart for explaining the operation of the silicon tester shown in FIG. Time t in the measurement cycle of 40 ns (time t1 to t5) from the memory tester
When each signal is set for 10 ns from 1 to t2, p
Double speed control circuit 34 and p double speed algorithm circuit 35
Copies the waveforms at times t1 to t2 by a phase locked loop, an up / down counter and a latch circuit, and copies the waveforms at times t2 to t3, times t3 to t4, and times t4 to t5.
Generates and outputs a copy waveform. The times t1 to t2 are the read “H” portion of the marking increment, the write “L” at the times t2 to t3, the read “H” at the address [A + 1] at the times t3 to t4, and the time t.
The change between the "L" level and the "H" level of each signal of the write "L" from 4 to t5 and the address change are performed by the p-times speed algorithm circuit 35, and the "H" level of each signal is changed.
Level to "L" level or "L" level to "H"
The setting of the time of the transition point to the level is performed by the p-times speed control circuit 34.

Next, the operation of the integrated circuit test apparatus according to this embodiment will be described. In this case, the number of chips to be measured is not one, but a part of all the chips of the wafer 14 to be measured, for example, 16 out of 96 chips.

In this case, a signal for one input of one chip is supplied from the memory tester 1 to the silicon tester wafer 14. In the silicon tester wafer 14, 8 input data for 16 chips is generated by an exclusive OR circuit of a latch circuit of a multi-chip / bit control circuit, and 96 chips are divided into 6 blocks by a block selection decoder. Each signal is supplied by selecting 16 chips of the one block.

First, the wafer to be measured 14 is a non-defective 16M-D
The case of a RAM chip will be described as an example. In this case, a signal for the test is supplied from the silicon tester chip 12 to the wafer 14 to be measured via the piezoelectric conductive rubber 13.
The output of the chip to be measured is transmitted to the silicon tester chip 12 via the piezoelectric conductive rubber 13, judged as non-defective by the comparator circuit, and transmitted to the memory tester 1 via the signal line cable 7.

The measured wafer 14 has a marking defect 16
Similarly, in the case of an M-DRAM chip,
A test signal is supplied from the tester chip 12 to the wafer under test 14 via the piezoelectric conductive rubber 13, and the output of the chip under test is supplied to the silicon wafer via the piezoelectric conductive rubber 13.
It is transmitted to the tester chip 12. At this time, the comparator circuit in the silicon tester chip 12 determines that the chip to be measured is defective because, for example, the output at the “L” level arrives at the place where the expected value is at the “H” level. , A defective signal is transmitted to memory tester 1 via signal line 7. The failure result is also held in the fail memory circuit.

If the wafer under test 14 has a defect in which an overcurrent flows during standby, the self-overcurrent protection circuit operates when the chip is set and power is applied. As a result, the current supply to the chip to be measured is stopped, and a defective standby current is transmitted to the memory tester.

The silicon tester shown in FIGS. 3 and 4 is intended for measurement at the wafer level.
Modifications for chip-by-chip measurements are also possible.

In the above description, the integrated circuit to be measured is a DRAM
Although the description has been given of the case of a wafer on which a chip or a DRAM chip is formed, the present invention can be similarly applied to measurement of other integrated circuits.

[0041]

As described above, the integrated circuit test apparatus of the present invention has at least a part of the functions of the LSI tester.
It is provided on a silicon tester made of a semiconductor chip or a wafer capable of electrically contacting the integrated circuit to be measured via a contact material. In particular, by providing a silicon tester with a high-precision and high-speed driver and comparator function for multi-chip parallel and multi-input / output of an LSI tester, the configuration can be greatly simplified.

For example, one 16M-DRAM with 8 inputs / outputs
A conventional memory tester capable of performing 16 parallel measurements at 00 MHz requires 138 devices only with a driver board. On the other hand, in the present invention, the functions of the driver and the comparator are performed by the silicon tester, so that the LSI tester main body only needs to have one piece of I / O hardware, and 25 MHz operation is sufficient. In this case, the required number of driver boards is 22 which is 1/6 or less of the conventional one, and the basic clock is also slow. Therefore, the same measurement as the conventional one can be performed by using a memory tester whose function is simplified. On the other hand, for silicon testers, 16M-D
It can be manufactured by a process similar to a RAM.

[0043]

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an integrated circuit test apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a counter of the integrated circuit test apparatus according to one embodiment of the present invention.

FIG. 3 is a diagram showing a configuration example of a silicon tester.

FIG. 4 is a timing chart illustrating the operation of the silicon tester.

FIG. 5 is a diagram showing a measurement example using a conventional memory tester.

FIG. 6 is a diagram showing a block configuration of a measurement system of the memory tester.

[Explanation of symbols]

Reference Signs List 1,51 Memory tester 2 Pattern generator 3 Input means for judgment result 4 Control means for setting or controlling 5 Interlocking means for operating silicon tester wafer 12 in conjunction with memory tester 1, 6,62 Driver comparator 7 , 57 Signal line cable 11 Fixing jig 12 Silicon tester wafer 13 Piezoelectric conductive rubber 14 Wafer to be measured 15 Double speed specifying function 16 Pattern name specifying function 17 Line name specifying function 31 Multi-chip / bit control circuit 32 Blockon Selection decoder 33 chip selection decoder 34 p-times speed control circuit 35 p-times speed algorithm circuit 36 self-overcurrent protection circuit 37 positioning circuit 38 in-chip test circuit 39 fail memory circuit 40 current control circuit 41 comparator circuit 42 on-chip capacitor 43 Head 52 memory tester measuring station 53 a wafer prober 54 probe card 55 to be measured wafer 56 vacuum Fuchaku base 56 61 central processing unit 63 to be measured memory 64, 65, 66 signal lines 101 to 106 Counter

──────────────────────────────────────────────────続 き Continuation of the front page (51) Int.Cl. ⁶ Identification symbol FI H01L 27/04 H01L 27/04 T (56) References JP-A-5-275504 (JP, A) JP-A-62-263475 ( JP, A) JP-A-54-150051 (JP, A) JP-A-5-288808 (JP, A) JP-A-4-133443 (JP, A) JP-A-3-44949 (JP, A) (58) ) Surveyed field (Int.Cl. ⁶ , DB name) G01R 31/28-31/3193 H01L 21/66 G01R 31/26 H01L 27/04

Claims (2)

(57) [Claims] 1. A test means for inputting a power supply and a signal necessary for the operation of a circuit to be measured formed on a substrate and measuring an output thereof, and contacting the integrated circuit to be measured with a contact material. An integrated circuit test apparatus comprising a semiconductor chip or a wafer on which at least a part of the test means is formed so as to be electrically contactable through the semiconductor chip or the wafer , wherein the semiconductor chip or the wafer includes a clock signal supplied from the test means. Circuit tester equipped with a counter for receiving
The counter receives the clock signal and synchronizes with it.
A first counter for inverting the output signal to
Receive the sync signal and the up / down mode
Output signal in synchronization with each of the input clock signals
A second counter for inverting the clock signal;
Carry prediction synchronously and from the lower bit
And a third counter for receiving the signal and inverting the output signal.
The least significant bit (LSB) of the counter is
And the other bits are stored in the second or
An integrated circuit test device comprising a third counter . 2. The system according to claim 1, wherein the counter has a lower bit to an upper bit.
If it is counted toward
From the unit to be configured to the third counter.
2. The number of stages up to the number of cuts is equal.
An integrated circuit test apparatus according to claim 1.