JPH0989991A - Integrated circuit testing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an integrated circuit testing device for precisely measuring an integrated circuit on a chip or wafer with little hardware structure. SOLUTION: A part or all of the function of LSI test 1 is provided on a semiconductor chip or wafer 72, this is electrically brought into contact with an integrated circuit 74 to be measured through a contact member 73. The semiconductor chip or wafer 72 has an electric characteristic matching means for the LSI tester 1 and the integrated circuit 74. Since the drawing of a signal necessary for test from the LSI test 1 is thus dispensed with to simplify the hardware, a highly precise and high speed measurement for multiple chip parallel and multiple input and output of the LSI tester 1 can be performed.

Description

Detailed Description of the Invention

[0001]

The present invention relates to an integrated circuit test apparatus, and more particularly to an integrated circuit test apparatus for evaluating the operation of an integrated circuit in a state of a chip or a wafer.

[0002]

2. Description of the Related Art In order to evaluate an integrated circuit on a semiconductor chip or wafer, a conventional integrated circuit test apparatus receives power supplies, clock signals, address signals and input data for the required number of chips and the number of inputs and outputs. 2. Description of the Related Art There is known an LSI tester which supplies a chip or a wafer and determines the output of the chip or the wafer by a determination circuit.

[0003] Known techniques relating to this LSI tester are disclosed, for example, in JP-A-62-243335 and JP-A-2-5.
No. 6947 and JP-A-2-239641. In addition, a chip or a wafer to be measured provided with a test circuit for such measurement is also known.

Hereinafter, a memory tester for measuring a storage element will be described as an example of the LSI tester.

FIG. 5 shows an example of measurement of a wafer to be measured by a conventional memory tester. Conventional memory tester is 100
A memory tester main body 51 operating at MHz and a memory tester measurement station 52 are provided. The memory tester measurement station 52 is provided with a driver comparator 62 and a signal cable 57. The wafer to be measured 55 is placed on a vacuum chuck table 56 on a wafer prober 53 and measured via a probe card 54.

FIG. 6 shows a block configuration of a measurement system of the memory tester. The memory tester main body 51 has a central processing unit 61 therein, and a memory tester measurement station 52
A driver / comparator 62 is provided inside. The memory under test 63 is connected to the driver / comparator 62 via signal lines 64, 65 and 66. The driver comparator 62 supplies a high-precision and high-speed clock as the RAS signal and the CAS signal to the memory 63 via the signal lines 64 and 65, and supplies test data via the signal line 66. The driver / comparator 62 also highly accurately determines the data output from the memory under test 63 to the signal line 66.

[0007]

In the conventional LSI tester, it is necessary to supply and measure a clock signal, an address signal, data and the like with high accuracy and high speed in accordance with the number of chips and the number of inputs and outputs of an integrated circuit to be measured. . But LS
When a plurality of integrated circuits to be measured are simultaneously driven by one driving unit of the I tester, there is a problem that the driving waveform is ringed due to the mismatching of the wiring impedances on the board and the accurate measurement cannot be performed. For example, the input / output is 1 with 8 bits
There is a problem that the control of a memory tester capable of measuring 16 6M-DRAMs in parallel at 100 MHz is technically advanced.

An object of the present invention is to solve the above problems and to provide an integrated circuit test apparatus capable of highly accurately measuring an integrated circuit on a chip or a wafer with a small hardware configuration.

[0009]

An integrated circuit test apparatus of the present invention inputs a power supply and a signal necessary for operating the integrated circuit to be measured formed on a substrate (chip or wafer) to the circuit. In an integrated circuit test apparatus having a test means for measuring the output, a semiconductor chip or wafer that can be electrically contacted with a measured integrated circuit via a contact material is provided, and the semiconductor chip or wafer is the test means. The configuration includes a waveform shaping means for the integrated circuit under test and a skew adjusting means for the test means and the integrated circuit under test.

Further, in the following description, a technique using silicon as a semiconductor is assumed, and a semiconductor chip or wafer on which at least a part of the test means is formed is referred to as a "silicon tester".

In this silicon tester, 1 bit of data for one chip of the integrated circuit to be measured to n bits (n is a positive integer) of n chips (m is a positive integer) are included.
Means for generating data of a positive integer) The integrated circuit under test formed on one wafer is divided into a blocks (a is a positive integer), and one of the blocks is selected for measurement. Means, means for selecting and measuring one chip of the integrated circuit to be measured, and the like.

A part or all of the functions of the LSI tester is provided on a semiconductor chip or a wafer to form a silicon tester, which is electrically contacted to the integrated circuit to be measured through a contact material. This eliminates the need to extract all the signals required for the test from the LSI tester via the signal lines. In particular, the hardware of the LSI tester can be simplified by incorporating the functions of a high-precision and high-speed driver and comparator for multi-chip parallel and multi-input / output in a silicon tester.

[0013]

FIG. 1 is a diagram showing the configuration of a silicon tester of an integrated circuit test apparatus according to an embodiment of the present invention, showing an example at a wafer level.

Referring to each of FIGS. 1 and 3,
The silicon tester 11 of this embodiment includes a multi-chip / bit control circuit 31, a block selection decoder 32, a chip selection decoder 33, a p-speed control circuit 34, a P-speed algorithm circuit 35, a self-overcurrent protection circuit 36, and a position. Matching circuit 37, in-chip test circuit 38, fail memory circuit 39, current control circuit 40, comparator circuit 41
And a pad 13 and a signal from the measuring circuit 30, and an electric characteristic matching means 12 between the memory tester and the integrated circuit to be measured.

Further, referring to FIG. 2, the electrical characteristic matching means 12 between the memory tester and the integrated circuit under test 12 includes a waveform shaping circuit 22 for the memory tester and the integrated circuit under test, and timing of the integrated circuit under test. And a skew adjusting circuit 23 for adjusting the skew.

FIG. 3 shows the measuring circuit 3 of the silicon tester 11.
An example of the configuration of 0 is shown. Here, an example is shown in which data of only one input is supplied and the determination results for the number of memories under measurement are output. The measurement circuit 30 of the silicon tester 11 includes a multi-chip / bit conversion control circuit 31, a block selection decoder 32, a chip selection decoder 33, a p-speed control circuit 34, a P-speed algorithm circuit 35, and a self-overcurrent protection circuit 36. , A positioning circuit 37, an in-chip test circuit 38, a fail memory circuit 39, a current control circuit 40, a comparator circuit 41 and an on-chip capacitor 42.

The multi-chip / bit conversion control circuit 31 uses a decoder circuit and an exclusive OR circuit for input / output and address from the data of 1 bit (or 1 input / output) of one chip supplied from the memory tester. Is used to generate data of m chips (m is a positive integer) and n bits (n is a positive integer). The block selection decoder 32 divides the measured wafer into a number of blocks (a is a positive integer) when the silicon tester measures at the wafer level,
Select that one block as the measurement target. The chip selection decoder 33 selects an arbitrary chip of the wafer to be measured when measuring at the wafer level. The p-times speed control circuit 34 multiplies the clock frequency supplied from the memory tester by p times (p is an integer of 2 or more) using a phase locked loop. When the p-times control circuit 34 operates, the p-times speed algorithm circuit 35 uses the up / down counter and the latch circuit to generate a test pattern after the second cycle of the p-times speed operation that is not supplied from the memory tester. . The self-overcurrent protection circuit 36 uses a flip-flop having a reset function to stop current supply to a chip in which an overcurrent exceeding the rating flows. The alignment circuit 37 is arranged on any pad of the chip under test so that the pad of the silicon tester and the pad of the chip under test can be aligned.
The direct current signal from the memory tester is supplied to the individual pads (b is a positive integer) via the signal switching circuit. The in-chip test circuit 38 measures the dummy chip circuit 12 corresponding to a part of the functions of the chip under test, and stores the memory
Self-diagnosis of tester operation. Fail memory circuit 39
When the measurement result of the chip under test is defective, the content of the defect is held by the flip-flop circuit. The current control circuit 40 divides the clock frequency from the memory tester to 1 / c (c is an integer of 2 or more) by a frequency dividing circuit when performing multi-chip parallel measurement of the wafer to be measured at the wafer level. The current is controlled by reducing the speed or by dividing the wafer to be measured into arbitrary blocks and sequentially selecting the blocks. The comparator circuit 41 determines the measurement result of the chip to be measured. The on-chip capacitor 42 operates as a bypass capacitor with the chip under measurement.

All of the above circuits do not have to be provided on a silicon tester, and some circuits can be omitted, for example, when measuring on a chip basis.

Further, the waveform shaping circuit 22 and the skew adjusting circuit 23 may be composed of known circuits.

FIG. 4 is a timing diagram illustrating the operation of the silicon tester shown in FIG. Time t in the measurement cycle of 40 ns (time t1 to t5) from the memory tester
When each signal is set for 10 ns from 1 to t2, p
Double speed control circuit 34 and p double speed algorithm circuit 35
Copies the waveforms at times t1 to t2 by a phase locked loop, an up / down counter and a latch circuit, and copies the waveforms at times t2 to t3, times t3 to t4, and times t4 to t5.
Generates and outputs a copy waveform. Times t1 to t2 are portions of the read "H" of the marking increment, and the write "L" at the time t2 to t3, the read "H" at the address [A + 1] at the time t3 to t4, and the time t.
The change between the "L" level and the "H" level of each signal of the write "L" from 4 to t5 and the address change are performed by the p-times speed algorithm circuit 35, and the "H" level of each signal is changed.
Level to "L" level or "L" level to "H"
The setting of the time of the transition point to the level is performed by the p-times speed control circuit 34.

Further, since these outputs are supplied to the chip to be measured through the waveform shaping circuit 22 provided on the silicon tester, the operation waveform thereof does not have drooling such as ringing.

FIG. 7 shows a silicon layer according to an embodiment of the present invention.
It is a figure which shows the integrated circuit test device which applied the tester, and shows the specific example in a wafer level. In this case, 25 MHz for inputting the power supply and signals necessary for the circuit to operate to the wafer under measurement 74 and measuring the output thereof.
Piezoelectricity of the contact material between the memory tester 1 that operates in the above, the driver 6 for only 1 I / O, the signal line cable 7, the silicon tester wafer 72, and the silicon tester wafer 72 and the wafer to be measured 74. Conductive rubber 73 and measuring jig 7 for supporting silicon tester wafer 72, wafer under measurement 74, and piezoelectric conductive rubber 73, respectively.
1 is provided. Further, the memory tester 1 includes a pattern generator 2, input means 3 for inputting determination results for 16 chips having 16 I / O counts, and external patterns other than the memory tester 1 different from the pattern generator 2. A control means 4 for setting or controlling a generator (not shown) and an interlocking means 5 for operating the silicon tester wafer 72 in conjunction with the memory tester 1 are provided.

The silicon tester wafer 72 and the wafer to be measured 74 are attached to the measuring jig 71, respectively.
They are electrically connected to each other via a piezoelectric conductive rubber 73 as a contact material. The silicon tester wafer 74 is provided with some or all functions for testing.

Next, the operation of the embodiment of the present invention will be described. In this case, the number of chips to be measured is not one, but a part of all the chips of the wafer 14 to be measured, for example, 16 out of 96 chips.

In this case, a signal for one input of one chip is supplied from the memory tester 1 to the silicon tester wafer 72. In the silicon tester wafer 72, 8 input data for 16 chips is generated by the exclusive OR circuit of the latch circuit of the multi-chip / bit conversion control circuit, and 96 chips are divided into 6 blocks by the block selection decoder. The 16 chips in one block are selected and each signal is supplied.

First, the measured wafer 74 is a non-defective 16M-D.
A case of a RAM chip will be described as an example. In this case, a signal for testing is supplied from the silicon tester chip 72 to the wafer to be measured 74 via the piezoelectric conductive rubber 73.
The output of the chip to be measured is transmitted to the silicon tester chip 72 via the piezoelectric conductive rubber 73, judged to be non-defective by the comparator circuit, and transmitted to the memory tester 1 via the signal line cable 7.

The wafer to be measured 74 has 16 marking defects.
Similarly, in the case of an M-DRAM chip, silicon
A signal for testing is supplied from the tester chip 72 to the wafer to be measured 74 via the piezoelectric conductive rubber 73, and the output of the chip to be measured is transferred to the silicon wafer via the piezoelectric conductive rubber 73.
It is transmitted to the tester chip 72. At this time, in the comparator circuit in the silicon tester chip 72, since the output of the “L” level arrives at the place where the expected value is the “H” level, it is determined that the measured chip is a defective product. The defective signal is transmitted to the memory tester 1 via the signal line 7. Further, the result of the failure is held in the fail memory circuit.

If the wafer to be measured 74 has a defect in which an overcurrent flows during standby, the self-overcurrent protection circuit operates when the chip is set and power is applied. As a result, the current supply to the chip to be measured is stopped, and a defective standby current is transmitted to the memory tester.

Although the silicon tester shown in FIGS. 3 and 4 is intended for measurement at the wafer level,
It can also be modified for chip-by-chip measurements.

In the above description, the integrated circuit under test is the DRAM.
Although the case of a wafer having chips or DRAM chips formed thereon has been described, the present invention can be similarly applied to the measurement of other integrated circuits.

[0031]

As described above, the integrated circuit test apparatus of the present invention has at least a part of the function of the LSI tester.
It is provided in a silicon tester composed of a semiconductor chip or a wafer that can be electrically contacted with a measured integrated circuit through a contact material. In particular, since the silicon tester has a waveform shaping function and skew adjustment function with the LSI tester,
High-accuracy and high-speed measurement is possible for multi-chip parallel and multi-input / output of the LSI tester.

In the present invention, the functions of the driver and the comparator are performed by the silicon tester, so that the LSI tester main body may be provided with one 1-input / output hardware.
Moreover, it is possible to perform the same measurement as the conventional one by using the memory tester whose operation is 25 MHz with high accuracy and whose function is simplified.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an integrated circuit test apparatus according to an embodiment of the present invention.

FIG. 2 is an L diagram of an integrated circuit test apparatus according to an embodiment of the present invention.
The figure which shows the structure of the electrical characteristic matching means of SI tester and a to-be-measured integrated circuit.

FIG. 3 is a diagram showing a configuration example of a silicon tester.

FIG. 4 is a timing diagram illustrating the operation of the silicon tester.

FIG. 5 is a diagram showing an example of measurement by a conventional memory tester.

FIG. 6 is a diagram showing a block configuration of a measurement system of a memory tester.

FIG. 7 is a diagram showing a configuration of application of an integrated circuit test apparatus according to an embodiment of the present invention.

[Explanation of symbols]

1,51 Memory tester 2 Pattern generator 3 Input means of judgment result 4 Control means for setting or controlling 5 Silicon silicon tester Wafer 12 is operated in conjunction with memory tester 1 Moving means 6,62 Driver comparator 7 , 57 signal line cable 11 silicon tester wafer 12 electrical characteristic matching means between LSI tester and integrated circuit under test 13 pad 22 waveform shaping circuit 23 skew adjustment circuit 31 multi-chip / bit conversion control circuit 32 block select decoder 33 Chip selection decoder 34 p double speed control circuit 35 p double speed algorithm circuit 36 Self overcurrent protection circuit 37 Positioning circuit 38 In-chip test circuit 39 Fail memory circuit 40 Current control circuit 41 Comparator circuit 42 On-chip capacitor 43 Pad 52 Mem Re-tester measurement station 53 Wafer prober 54 Probe card 55 Measured wafer 56 Vacuum chuck table 56 61 Central processing unit 63 Measured memory 64, 65, 66 Signal line 71 Fixing jig 72 Silicon tester wafer 73 Piezoelectric conductive Rubber 74 Wafer to be measured

Claims (4)

[Claims] 1. A test means for inputting a power supply and a signal necessary for the circuit to operate to an integrated circuit to be measured formed on a substrate and measuring an output thereof, and a contact material for the integrated circuit to be measured. In an integrated circuit test device including a semiconductor chip or wafer which is electrically contactable via the semiconductor chip or wafer in which at least a part of the test means is formed, the semiconductor chip or wafer receives a signal of at least a part of the test means. An integrated circuit test apparatus comprising: a waveform shaping means for the test means and the integrated circuit under test; and a skew adjusting means for the test means and the integrated circuit under test. 2. The integrated circuit under test includes a plurality of chips on one wafer, and the semiconductor chip or the wafer is m chips (where m is a positive number) based on 1-bit data for one chip of the integrated circuit under test. N for each)
2. The integrated circuit testing device according to claim 1, further comprising means for generating bit (n is a positive integer) data, and each of the waveform shaping means and the skew adjusting means receives a signal from the means for generating the data. 3. An integrated circuit to be measured formed on the wafer of the semiconductor chip or one wafer is divided into a blocks (a).
Is a positive integer), and means for selecting and measuring one of the blocks is provided, and each of the waveform shaping means and the skew adjusting means receives a signal from the means for selecting and measuring the block. 1. The integrated circuit test device according to 1. 4. The integrated circuit under test includes a plurality of chips on one wafer, and the semiconductor chip or wafer is provided with means for selecting and measuring one chip of the integrated circuit under test, and the waveform shaping means. 2. The integrated circuit test apparatus according to claim 1, wherein each of the skew adjusting means receives a signal from a means for selecting and measuring one chip of the integrated circuit under test.