US20050229067A1

US20050229067A1 - Semiconductor integrated circuit

Info

Publication number: US20050229067A1
Application number: US10/990,430
Authority: US
Inventors: Yasukazu Kai; Yoshihiro Nakatake
Original assignee: Oki Electric Industry Co Ltd
Current assignee: Oki Electric Industry Co Ltd
Priority date: 2004-04-01
Filing date: 2004-11-18
Publication date: 2005-10-13
Also published as: US20050229065A1; JP2005291996A; JP4332056B2; US20080126894A1; US7480841B2; US7334168B2

Abstract

A semiconductor integrated circuit capable of accurately measuring a time lag difference in operation test wiring is disclosed. It is provided with nMOS transistors in which each control terminal is connected to a signal terminal of a memory macro. Since the nMOS transistors are turned off when the test signals TCLK, TWE, and TRE are all at a low level, the potential of a pad which is connected to a drain is pulled up by a current generator. When the signal TCLK is changed to a high level, the transistor is turned on and the potential of the pad is changed to a low level. Then, a time lag from the moment at which the signal TCLK is changed to a high level to the moment at which the pad is changed to a low level is measured. Similarly, a time lag from the moment at which the signal TWE is changed to a high level to the moment at which the pad is changed to a low level and a time lag from the moment at which the signal TRE is changed to a high level to the moment at which the pad is changed to a low level are respectively measured. A difference of the measurement times corresponds to a difference of the time lags taken for the signals TCLK, TWE, and TRE to arrive at the memory macro.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention
The present invention relates to a technique for performing an operation test of a semiconductor integrated circuit. The invention can be applied to a semiconductor integrated circuit including a plurality of integrated circuit blocks, for example, a system LSI (Large Scale Integrated circuit).
2. Description of the Related Art
With advance in design, manufacturing technique and the like, in these days, a parallel processing RAM including a small-sized logic and a memory circuit (for example, DRAM (Dynamic Random Access Memory)) and a system LSI including a plurality of integrated circuits such as DRAM, SRAM (Static Random Access Memory), ROM (Read Only Memory), and CPU (Central Processing Unit) are being developed.
The circuits (macro blocks) installed on this semiconductor integrated circuit may include such a circuit that is not accessible directly from the outside at a using time. For example, in a parallel processing RAM 1300 shown in FIG. 1, a memory macro 1310 is not directly connected to pads 1330, 1330, . . . . Namely, signals input from the outside are all entered into a logic 1320 and then a signal based on the input signal is created in the logic 1320 and supplied to the memory macro 1310. Similarly, a signal output from the memory macro 1310 is not directly supplied to each of the pads 1330, 1330, . . . .
When performing an operation test only on the memory macro 1310, a test signal entered from a pad has to be supplied to the memory macro 1310 as it is. Therefore, a general semiconductor integrated circuit is designed to directly connect a signal input/output terminal of the memory macro 1310 with the pad 1330 by switching selectors (not illustrated) provided within the logic 1320. For example, in an example shown in FIG. 2, through selectors (not illustrated) provided within circuits 1321, 1321, . . . and through wirings 1322, 1322, . . . , signal terminals 1311, 1312, and 1313 of the memory macro 1310 are directly connected to the pads 1331, 1332, and 1333 respectively.
Here, in a semiconductor integrated circuit of FIG. 2, the number of logic elements and the length of wiring intervening between the signal terminals 1311, 1312, and 1313 and the pads 1331, 1332, and 1333 differ from one another. Therefore, each timing lag of input test signals TCLK, TWE, and TRE differs from one another. Even when the test signals TCLK, TWE, and TRE are entered at a timing designed for the memory macro 1310, each of input signals iCLK, iWE, and iRE arrives at the memory macro 1310 at a timing deviated from one another. This timing deviation becomes a nuisance when performing an operation test of a semiconductor integrated circuit. In order to solve this problem, each timing of entering these test signals TCLK, TWE, and TRE into the pads 1331, 1332, and 1333 respectively has to be adjusted in accordance with each time lag among the input test signals TCLK, TWE, and TRE. In order to enhance reliability of the operation test, it is necessary to measure each time lag among the test signals TCLK, TWE, and TRE accurately.
As the technique for measuring a time lag of a test signal, for example, the following technique is known.
(1) A first technique is to directly measure a time lag by using a picoprobe, an oscilloscope and the like. In this technique, a picoprobe is brought into contact with the pads 1331, 1332, and 1333 and the signal terminals 1311, 1312, and 1313, and a voltage waveform at each contact position is observed by the oscilloscope, hence to measure a time lag of each wiring.
(2) A second technique is that one disclosed in Japanese Patent Kokai No. 2001-153930 (Patent Document 1). In this technique, wiring is designed so that a test signal input from a test signal input pad is supplied from a test signal output pad after arriving at a macro to be inspected. By measuring a difference between the output timings of the test signals, each time lag of the test signals is detected (refer to the paragraphs 0036 to 0042 in the same article).
The above technique (1), however, has such a disadvantage that a required time of an operation test is prolonged because an operator has to conduct a picoprobe into a semiconductor integrated circuit chip manually. Further, it is difficult to do an operation test under a high temperature because measurement is manually done, and measurement result cannot be always accurate.
The above technique (2) has such a disadvantage that the circuit size of a semiconductor integrated circuit is enlarged because of requiring a large-scaled test circuit (test controller 5B in the same article) and wiring for a test line (common test bus 2 in the same article).
On the other hand, as an operation test of a semiconductor integrated circuit, measurement of electric current consumption is requested in some cases. Hitherto, as the technique of measuring electric current consumption, a technique as disclosed in, for example, Japanese Patent Kokai No. 2003-256495 (Patent Document 2) is well known. In the technique of Patent Document 2, an RT net list and a test pattern are used to detect the electric current consumption of a semiconductor integrated circuit.
In the technique of Patent Document 2, however, it is not possible to measure the electric current consumption of the memory macro 1310 only in a semiconductor integrated circuit as shown in FIG. 1.

SUMMARY OF THE INVENTION

An object of the invention is to provide a semiconductor integrated circuit capable of accurately measuring a time lag difference in operation test wiring and further accurately measuring the current consumption of only a circuit that is an object of an operation test.
A first aspect of the invention relates to a semiconductor integrated circuit comprising a circuit to be checked through an operation test, a plurality of pads for receiving test signals from the outside, and a plurality of signal paths formed within another circuit in order to lead the test signals entered from the pads to a signal input terminal of the checked circuit in an operation test mode.
It further comprises a first test pad to which a first pull-up potential is supplied and a time lag measuring circuit including a plurality of first transistors in each of which one end is connected to the first test pad, the other end is connected to a power source line, and a control terminal is connected to the corresponding signal input terminal.
A second aspect of the invention relates to a semiconductor integrated circuit comprising a circuit to be checked through an operation test and another circuit for creating an operation control signal of the checked circuit according to a signal entered from the outside.
It further comprises an input switch for supplying the operation control signal to the checked circuit at a time of measuring the current consumption of the whole semiconductor integrated circuit and for making the output high impedance at a time of measuring the current consumption of the circuit excepting the checked circuit, an output switch for supplying an output signal of the checked circuit to the other circuit at a time of measuring the current consumption of the whole semiconductor integrated circuit and for making the output high impedance at a time of measuring the current consumption of the circuit excepting the checked circuit, and a pseudo signal supplying circuit for supplying a pseudo output signal of the checked circuit to the other circuit at a time of measuring the current consumption of the circuit excepting the checked circuit.
According to the first aspect of the invention, it is possible to accurately measure a relative time lag difference in every signal path, by measuring a time lag from the moment at which the test signal is changed in level to the moment at which the potential of the first test pad is changed, in every test signal.
According to the second aspect of the invention, it is possible to detect the current consumption of only the checked circuit, by calculating a difference between the measurement result of the current consumption of the whole semiconductor integrated circuit and the measurement result of the current consumption of the circuit excepting the checked circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram schematically showing the structure of an important portion of the conventional semiconductor integrated circuit.
FIG. 2 is a schematic view for use in describing an operation of the conventional semiconductor integrated circuit.
FIG. 3 is a block diagram schematically showing the structure of an important portion of a semiconductor integrated circuit according to a first embodiment.
FIGS. 4A to 4G show each signal waveform for use in describing an operation of the semiconductor integrated circuit according to the first embodiment.
FIG. 5 is a block diagram schematically showing the structure of an important portion of a semiconductor integrated circuit according to a second embodiment.
FIGS. 6A to 6G show each signal waveform for use in describing an operation of the semiconductor integrated circuit according to the second embodiment.
FIG. 7 is a block diagram schematically showing the structure of an important portion of a semiconductor integrated circuit according to a third embodiment.
FIGS. 8A to 8H show each signal waveform for use in describing an operation of the semiconductor integrated circuit according to the third embodiment.
FIG. 9 is a block diagram schematically showing the structure of an important portion of a semiconductor integrated circuit according to a fourth embodiment.
FIGS. 10A to 10B are circuit views each showing the structure of an input switch and an output switch according to the fourth embodiment.
FIG. 11 is a block diagram schematically showing the structure of an important portion of a semiconductor integrated circuit according to a fifth embodiment.
FIG. 12 is a circuit view showing the structure of a pseudo signal switch according to the fifth embodiment.
FIG. 13 is a block diagram schematically showing the structure of an important portion of a semiconductor integrated circuit according to a sixth embodiment.
FIG. 14 is a circuit view showing the structure of a pseudo signal generator according to the sixth embodiment.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, preferred embodiments of the invention will be described by using the drawings. In the drawings, size, shape, and positional relationship of each component is schematically shown only for the sake of understanding the invention, and the numerical condition described below is indicated only by way of example.

First Embodiment

A semiconductor integrated circuit according to a first embodiment of the invention will be described referring to FIG. 3 and FIG. 4.
FIG. 3 is a block diagram schematically showing the structure of an important portion of the semiconductor integrated circuit according to this embodiment.
As illustrated in FIG. 3, a semiconductor integrated circuit 100 according to this embodiment comprises a memory macro 110, a logic 120, pads 131 to 134, and a time lag measuring circuit 140.
The memory macro 110 is a usual memory integrated circuit, which receives the signals iCLK, iWE, and iRE from the signal terminals 111, 112, and 113. In this embodiment, an operation test is performed only on the memory macro 110.
The logic 120 is a logic circuit including some peripheral circuit of the memory macro 110. In the usual ordinary operation mode, the logic 120 creates signals iCLK, iWE, and iRE based on the signals input from the pads (they may be the pads 131, 132, and 133 of FIG. 3 or the other pads not illustrated) and supplies them to the signal terminals 111, 112, and 113 of the memory macro 110. On the other hand, during the test operation, the logic 120 supplies the test signals TCLK, TWE, and TRE respectively input through the pads 131, 132, and 133 to the signal terminals 111, 112, and 113 of the memory macro 110 as they are as the signals iCLK, iWE, and iRE. Where, similarly to the logic (refer to the logic 1320 in FIG. 2) in the conventional semiconductor integrated circuit, there may be some cases where each lag time in passing the test signals TCLK, TWE, and TRE differs from one another.
The pads 131 to 134 are signal input/output pads similarly to the conventional pads (refer to the pad 1330 in FIG. 1). The pads 131 to 133 respectively receive the test signals TCLK, TWE, and TRE from the outside and supply them to the logic 120, as mentioned above. While, the pad 134 supplies an output potential of the time lag measuring circuit 140 to the outside (described later).
The time lag measuring circuit 140 is a circuit for measuring a time lag between the pad 131 and the signal terminal 111, a time lag between the pad 132 and the signal terminal 112, and a time lag between the pad 133 and the signal terminal 113. The time lag measuring circuit 140 includes nMOS transistors 141 to 143 and a current generator 144. In the transistor 141, its source is grounded, drain is connected to the pad 134, and gate is connected to the signal terminal 111. In the transistor 142, its source is grounded, drain is connected to the pad 134, and gate is connected to the signal terminal 112. In the transistor 143, its source is grounded, drain is connected to the pad 134, and gate is connected to the signal terminal 113. The current generator 144 is a source for supplying a first pull-up potential to the pad 134. In the embodiment, although the current generator 144 is provided within the time lag measuring circuit 140, a current generator provided outside of the semiconductor chip may be used as the supply source of the first pull-up potential.
Thus, the time lag measuring circuit 140 of the embodiment is provided with the nMOS transistors 141 to 143 of open drain structure, and the drains of these transistors 141 to 143 are connected to the pad 134 in common, hence to pull up the pad 134. Thus, a wired NOR logical circuit is constituted in a very easy structure, in this embodiment.
An operation of the semiconductor integrated circuit 100 shown in FIG. 3 will be described by using FIGS. 4A to 4G. FIGS. 4A to 4G show each signal waveform for describing each time lag about the rising edge and the falling edge of each of the test signals TWE and TRE, with reference to the rising edge of the test signal TCLK.
Each potential of the signals TCLK, TWE, and TRE (namely, each potential of the pads 131 to 133) is fixed at a low level (refer to FIG. 4A, 4C, and 4E). According to this, each potential of the signals iCLK, iWE, and iRE (namely, each potential of the signal terminals 111 to 113) is turned to a low level and each gate potential of the transistors 141 to 143 also becomes a low level, and therefore, the transistors 141 to 143 are turned off. At this time, potential of a delay detecting signal TEST1 (potential of the output pad 134) is at a high level because of being pulled up by the current generator 144.
While the signals TWE and TRE are kept at a low level, the signal TCLK is changed from a low level to a high level (refer to FIG. 4A). The potential of the signal terminal 111 (iCLK) is changed from a low level to a high level (refer to FIG. 4B) after elapse of the time lag T01. As a result, the transistor 141 is turned on, and therefore, the potential of the delay detecting signal TEST1 is changed from a high level to a low level (refer to FIG. 4G). A time lag from the moment at which the signal TCLK becomes a high level to the moment at which the signal TEST1 becomes a low level is defined as T02.
The signal TCLK is changed to a low level after the time Ta has elapsed since the signal TCLK became a high level. According to this, since the signal iCLK becomes a low level (refer to FIG. 4B), the transistor 141 is again turned off and the signal TEST1 is returned to a high level (refer to FIG. 4G).
The signal TWE is changed from a low level to a high level (refer to FIG. 4C) while keeping the signals TCLK and TRE at a low level, after the time Tb has elapsed since the signal TCLK was returned to a low level. According to this, after elapse of the time lag T11, the potential of the signal terminal 112 (iWE) is changed to a high level (refer to FIG. 4D). When the signal iWE becomes a high level, the transistor 142 is turned on and the potential of the delay detecting signal TEST1 is changed to a low level (refer to FIG. 4G). A time lag from the moment at which the signal TWE becomes a high level to the moment at which when the signal TEST1 becomes a low level is defined as T12.
The signal TWE is changed to a low level (refer to FIG. 4C) after the time Tc has elapsed since the signal TWE became a high level. The potential of the signal terminal 112 (iWE) is changed to a low level (refer to FIG. 4D) after elapse of the time lag T13 since the signal TWE has become a low level. Further, when the signal iWE becomes a low level, the transistor 142 is turned off and the potential of the delay detecting signal TEST1 is changed to a high level (refer to FIG. 4G). A time lag from the moment at which the signal TWE becomes a low level to the moment at which the signal TEST1 becomes a high level is defined as T14.
The signal TRE is changed to a high level (refer to FIG. 4E) while keeping the signals TCLK and TWE at a low level, after the time Td has elapsed since the signal TWE became a low level. The potential of the signal terminal 113 (iRE) is changed to a high level after elapse of the time lag T21 (refer to FIG. 4F). When the signal iRE becomes a high level, the transistor 143 is turned on and the potential of the delay detecting signal TEST1 is changed to a low level (refer to FIG. 4G). A time lag from the moment at which the signal TRE becomes a high level to the moment at which time when the signal TEST1 becomes a low level is defined as T22.
The signal TRE is changed to a low level (refer to FIG. 4E) after a predetermined time Te has elapsed since the signal TRE was changed to a high level. According to this, the potential of the signal terminal 113 (iRE) is changed to a low level (refer to FIG. 4F) after elapse of the time lag T23 since the signal TRE became a low level. Further, when the signal iRE becomes a low level, the transistor 143 is turned off and the potential of the delay detecting signal TEST1 is changed to a high level (refer to FIG. 4G). A time lag from the moment at which the signal TRE becomes a low level to the moment at which the signal TEST1 becomes a high level is defined as T24.
As mentioned above, each time lag has been measured.
The time lag between the pad 131 and the signal terminal 111 at the rising edge of the test signal TCLK agrees with the T01. The time lag between the pad 132 and the signal terminal 112 at the rising edge of the test signal TWE agrees with the T11. Accordingly, a difference between the time lag of the test signal TCLK and the time lag of the test signal TWE is given by T11−T01. The time lag difference T11−T01 approximates to the difference T12−T02 between the above mentioned measurement values T02 and T12. A difference of time T02−T01 between the rising edge of the signal iCLK and the falling edge of the test signal TEST1 approximates to a difference of the time T12−T11 between the rising edge of the signal iWE and the falling edge of the test signal TEST1. Accordingly, a difference of the time lag on the rising edge between the signals iCLK and iWE is given by a difference T12−T02 between the measured value T12 and the measured value T02. For this reason, a difference of the time lag on the rising edge between the signals iCLK and iWE can be given by measuring the time T02 and T12. Similarly, a difference of the time lag on the rising edge between the test signals TCLK and TRE can be given by measuring the time T02 and T22.
As apparent from FIGS. 4A to 4G, an elapse time from the rising edge of the signal iCLK (potential of the signal terminal 111) to the falling edge of the signal iWE (potential of the signal terminal 112) is given by Ta−T01+Tb+Tc+T13. The time T14−T13 from the falling edge of the signal iWE (potential of the signal terminal 112) to the rising edge of the signal TEST1 (potential of the pad 134) approximates to the above T02−T01. That is, T14−T13≈T02−T01. Accordingly, −T01+T13≈−T02+T14. Therefore, the above mentioned time Ta−T01+Tb+Tc+T13 approximately agrees with Ta−T02+Tb+Tc+T14. For this reason, the elapse time from the rising edge of the signal iCLK to the falling edge of the signal iWE can be given by measuring the time T02 and T14. Similarly, the elapse time from the rising edge of the signal iCLK to the falling edge of the signal iRE can be given by measuring the time T02 and T24.
It is needless to say that each time lag between the rising edge of the signal iCLK to each falling edge of the signals iWE and iRE can be measured in the same way.
As mentioned above, according to the semiconductor integrated circuit 100 of this embodiment, a difference of each time lag when the test signals TCLK, TWE, and TRE respectively arrive at the signal terminals 111, 112, and 113 of the memory macro 110 can be given by measuring each time period during which each of the test signals TCLK, TWE, and TRE is respectively supplied to each of the pads 131, 132, and 133, hence to change the potential of the pad 134.
As mentioned above, in this embodiment, the transistors 141 to 143 for controlling the potential of the pad 134 are formed into open drain structure. When using a transistor of open drain structure, it is not necessary to provide power source in every transistor like in the case of a transistor of source follower structure, and it is possible to connect the respective drains of the transistors 141 to 143 to the pad 134 in common and obtain a NOR logic output only by pulling up the pad 134. Accordingly, the embodiment can measure a time lag with a very small circuit.
Further, an operator's manual probing work is not necessary and the measuring process of each time lag difference can be easily automated. Therefore, a required time in an operation test can be shortened and the operation test becomes easy at a high temperature.

Second Embodiment

A semiconductor integrated circuit according to a second embodiment of the invention will be described by using FIG. 5 and FIGS. 6A to 6G. This embodiment provides a semiconductor integrated circuit capable of measuring an access time of a memory macro (time period from the clock input to the memory macro to the output of the reading data from the memory macro).
FIG. 5 is a block diagram schematically showing the structure of an important portion of the semiconductor integrated circuit according to the embodiment. In FIG. 5, each component with the same reference numeral attached indicates the same component as in the case of FIG. 3.
As shown in FIG. 5, the semiconductor integrated circuit 300 of the embodiment comprises a logic 310, pads 321, 322, and 323, and a time lag measuring circuit 330.
The logic 310 is one portion of the logic 120. In the usual operation mode, the logic 310 creates an output signal based on the signal iDout entered from the signal terminal 114 of the memory macro 110 and supplies it to the pad 321. While, in the test operation mode, the logic 310 supplies the signal iDout entered from the signal terminal 114 to the pad 321 as it is as the signal TDout.
The pads 321, 322, and 323 are signal input/output pads similarly to the conventional pads (refer to the pad 1330 of FIG. 1). The pad 321 supplies the test signal TDout supplied by the logic 310 to the outside, as mentioned above. The pad 322 supplies the output potential TEST2 of the time lag measuring circuit 330 to the outside. The pad 323 receives a gate potential for controlling the off/on operation of the transistors 332 and 333 (described later).
The time lag measuring circuit 330 comprises nMOS transistors 331 to 333 of open drain connection and a current generator 334, in addition to the same transistors 141 to 143 and the same current generator 144 as those of the time lag measuring circuit 140 of the first embodiment. In the transistor 331, its source is grounded, its drain is connected to the pad 322, and its gate is connected to the signal terminal 114. In the transistor 332, its source is grounded, its drain is connected to the pad 322, and its gate is connected to the pad 323. In the transistor 333, its source is grounded, its drain is connected to the pad 134, and its gate is connected to the pad 323. The current generator 334 is a power source for supplying a second pull-up potential to the pad 322. In the embodiment, although the current generators 144 and 334 are provided within the time lag measuring circuit 330, the current source provided outside of the semiconductor chip may be used as a power source of the first and second pull-up potentials.
The operation of the semiconductor integrated circuit 300 shown in FIG. 5 will be described by using FIGS. 6A to 6G. FIG. 4 is a signal waveform showing a way of measuring the access time of the memory macro 110.
At first, each potential of the signals TCLK, TWE, TRE, and TEST3 (namely, each potential of the pads 131 to 133 and 323) is fixed at a low level (signals TWE and TRE are not illustrated). At this time, level of the signal iDout becomes low. Accordingly, the transistors 141 to 143 and 331 to 333 are turned off. Since each potential of the delay detecting signals TEST1 and TEST2 (each potential of the output pads 134 and 322) is pulled up by the current generators 144 and 334, it is at a high level.
While keeping the signals TWE and TRE at a low level, the signal TCLK is changed to a high level (refer to FIG. 6A). According to this, after elapse of the time lag T01, the potential of the signal terminal 111 (iCLK) is changed to a high level (refer to FIG. 6C). Thus, since the transistor 141 is turned on, the potential of the delay detecting signal TEST1 is changed to a low level (refer to FIG. 6F). The time T02 from the moment at which the test signal TCLK becomes a high level to the moment at which the signal TEST1 becomes a low level is measured.
When the signal iCLK becomes a high level, the signal iDout (potential of the signal terminal 114) becomes a high level (FIG. 6D) and therefore, the test signal TDout (potential of the pad 321) also becomes a high level (refer to FIG. 6E). In the embodiment, the time T03 from the moment at which the test signal TCLK becomes a high level to the moment at which the test signal TDout becomes a high level is measured.
Thereafter, the test signal TCLK is returned to a low level. Thus, since all the test signals TCLK, TWE, TRE, TDout, and TEST3 become a low level, the transistors 141 to 143 and 331 to 333 are turned off. Therefore, the pads 134 and 322 become a high level by puling up of the current generators 144 and 334.
While keeping the signals TCLK, TWE, and TRE at a low level, the signal TEST3 is turned to a high level (refer to FIG. 6B). According to this, since the transistors 332 and 333 are turned on, the pads 134 and 322 become a low level. At this time, the time T04 from the rising edge of the signal TEST3 to the falling edge of the potential of the pad 134 (refer to FIG. 6G) and the time T05 from the rising edge of the signal TEST3 to the falling edge of the potential of the pad 322 are measured.
According to this, measurement has been completed.
The measurement time T04 approximately agrees with the time T06 from the rising edge of the signal iCLK to the falling edge of the signal TEST1 (refer to FIG. 6C). Accordingly, the time lag T01 between the pad 131 and the signal terminal 111 (namely T02−T06) approximately agrees with T02−T04.
The measurement time T05 approximates to the time T07 (refer to FIG. 6D) from the moment at which the signal iDout becomes a high level to the falling edge of the signal TEST2. Namely, the time lag T07 between the signal terminal 114 and the pad 321 approximates to the measurement time T05.
As mentioned above, an access time of the memory macro 110 is a time from the rising edge of the signal iCLK to the rising edge of the signal iDout. As apparent from FIGS. 6A to 6G, access time is given by T03−T01−T07. As mentioned above, T01 approximates to T02−T04 and T07 approximates to T05. Accordingly, access time of the memory macro 110 is given by T03−T02+T04−T05.
As mentioned above, according to the semiconductor integrated circuit 300 of this embodiment, it is possible to measure an access time of the memory macro 110 accurately only by adding the time lag measuring circuit 330 of simple structure.
According to this embodiment, an operator's manual probing work is not necessary and the measuring process of the access time can be automated easily, thereby shortening a required time in an operation test and making easy the operation test under a high temperature.
Although the description has been made by taking the measurement of the access time as an example, since the semiconductor integrated circuit 300 of the embodiment can directly measure the time from each level change of the signals iCLK, iWE, iRE, and iDout to each level change of the signals TEST1 and TEST2, it is also possible to measure the absolute time lag of each of the signals TCLK, TWE, and TRE.

Third Embodiment

A semiconductor integrated circuit according to a third embodiment of the invention will be described by using FIG. 7 and FIGS. 8A to 8H.
FIG. 7 is a block diagram schematically showing the structure of an important portion of the semiconductor integrated circuit according to this embodiment. In FIG. 7, each component with the same reference numeral attached is the same as in the case of FIG. 1.
As illustrated in FIG. 7, a semiconductor integrated circuit 500 of this embodiment comprises an nMOS transistor 501 within the time lag measuring circuit 140.
The transistor 501 is provided between the drain of the transistors 141 to 143 and the pad 134, which receives a test mode signal iTEST from a gate. The test mode signal iTEST may be entered from the outside or may be created within the logic 120.
In the embodiment, a pad connected to the logic 120 is used as the pad 134 for supplying the signal TEST1. Namely, the pad 134 is used for signal input and output to and from the logic 120 in the usual operation mode and it is used for supplying the signal TEST1 in the test operation mode.
The operation of the semiconductor integrated circuit 500 shown in FIG. 7 will be described by using the signal waveforms of FIGS. 8A to 8H.
When performing the operation test, at first, the test mode signal iTEST is set at a high level (refer to FIG. 8H). Thus, the transistor 501 is turned on, hence to electrically connect the drain of the transistors 141 to 143 with the pad 134, which enables the measurement of time lag difference. Since the detail of the time lag measurement (refer to FIGS. 8A to 8G) is the same as in the case of the above-mentioned first embodiment, its description is omitted.
When finishing the operation test, the test mode signal iTEST is returned to a low level.
As mentioned above, according to the semiconductor integrated circuit 500 of this embodiment, it is possible to measure a difference between each time lag accurately only by adding the time lag measuring circuit 140 of simple structure, similarly to the semiconductor integrated circuit 100 according to the first embodiment.
Further, an operator's manual probing work is not required and the measuring process of each time lag difference can be automated easily, thereby shortening a required time of an operation test and making easy the operation test under a high temperature.
Additionally, according to this embodiment, since a pad can be shared both in a test and in the usual operation mode, it is possible to restrain an increase in the number of pads and to restrain an increase in size of chip. Further, by using a pad for test and a pad in the usual operation mode in common, the pad can be estimated at the test operation time.

Fourth Embodiment

A semiconductor integrated circuit according to a fourth embodiment of the invention will be described by using FIG. 9 and FIGS. 10A and 10B. This embodiment provides a semiconductor integrated circuit capable of detecting a current consumption of the memory macro only.
FIG. 9 is a block diagram schematically showing the structure of an important portion of the semiconductor integrated circuit according to the embodiment.
As illustrated in FIG. 9, a semiconductor integrated circuit 700 of this embodiment comprises a memory macro 710, a logic 720, and pads 731 to 736.
The memory macro 710 receives the signals iCLK, iWE, iRE, iDIN, and iTEST from the signal terminals 711, 712, 713, 714, and 715 respectively and further supplies the data signal iDout from the signal terminal 716. The memory macro 710 is connected to power source lines VCC and VSS. The memory macro 710 includes an input switch 717 and an output switch 718. The detail of the input switch 717 and the output switch 718 will be described by using FIG. 8.
The logic 720 creates an input signal of the memory macro 710. The logic 720 creates the respective signals iCLK, iWE, iRE, and iDIN based on the respective signals CLK, WE, RE, and DIN entered from the respective pads 731 to 734 and supplies them to the signal terminals 711 to 714 of the memory macro 710. Additionally, the logic 720 sets the mode signal iTEST at a low level when measuring the current consumption of the whole semiconductor integrated circuit 700 and sets the mode signal iTEST at a high level when measuring the current consumption of only the logic 720. The logic 720 creates the output signal Dout based on the signal iDout entered from the memory macro 710 and supplies it to the pad 735. The logic 720 is connected to the power source lines VCC and VSS.
The pads 731 to 736 are signal input/output pads similarly to the conventional pads (refer to the pad 1330 in FIG. 13). The pads 731 to 734 receive the signals CLK, WE, RE, and DIN respectively from the outside as mentioned above and supply them to the logic 720. The pad 735 receives the signal Dout created by the logic 720 and supplies it to the outside. Further, the pad 736 receives a pseudo test signal TESTDIN from the outside and supplies it to the logic 720.
FIG. 10A is a circuit view showing the internal structure of the input switch 717. As illustrated in FIG. 10A, the input switch 717 includes an inverter 801 and four gates 802 to 805.
The inverter 801 inverts the mode signal iTEST and supplies it as a signal/iTEST.
The gate 802 supplies the inverted value of the signal iCLK to a posterior circuit when the inversion mode signal/iTEST is at a high level and makes the output high impedance when the inversion mode signal/iTEST is at a low level.
The gate 803 supplies the inverted value of the signal iWE to a posterior circuit when the inversion mode signal/iTEST is at a high level and makes the output high impedance when the inversion mode signal/iTEST is at a low level.
The gate 804 supplies the inverted value of the signal iRE to a posterior circuit when the inversion mode signal/iTEST is at a high level and makes the output high impedance when the inversion mode signal/iTEST is at a low level.
The gate 805 supplies the inverted value of the signal iDIN to a posterior circuit when the inversion mode signal/iTEST is at a high level and makes the output high impedance when the inversion mode signal/iTEST is at a low level.
According to the structure, when the mode signal iTEST is at a low level, the input switch 717 can invert the signals iCLK, iWE, iRE, and iDIN and send them to a posterior circuit, and when the mode signal iTEST is at a high level, it can make the output high impedance.
FIG. 10B is a circuit view showing the internal structure of the output switch 718. As illustrated in FIG. 10B, the output switch 718 includes an inverter 811, pMOS transistors 812 and 813, and nMOS transistors 814 and 815.
The inverter 811 inverts the mode signal iTEST and supplies it as the inversion mode signal/iTEST.
In the pMOS transistor 812, its source is connected to the power source line VCC and the mode signal iTEST is entered from its gate.
In the pMOS transistor 813, its source is connected to the drain of the pMOS transistor 812 and the reading data D is entered from its gate.
In the nMOS transistor 814, its drain is connected to the drain of the pMOS transistor 813 and the reading data D is entered from its gate.
In the nMOS transistor 815, its drain is connected to the source of the nMOS transistor 814, its source is grounded, and the inversion mode signal/iTEST is entered from its gate.
According to this structure, when the mode signal iTEST is at a low level, the output switch 718 can send the inversion signal iDout of the data D to a posterior circuit and when the mode signal iTEST is at a high level, it can make the output high impedance.
The operational principle of the semiconductor integrated circuit 700 according to this embodiment will be described.
The logic 720 is controlled so as to set the mode signal iTEST at a low level. According to this, the input switch 717 is in a position to pass the signals iCLK, iWE, iRE, and iDIN and the output switch 718 is in a position to supply the signal iDout.
Continuously, the same signals CLK, WE, RE, and DIN as in the usual operation mode are entered from the pads 731 to 734. At this time, the pad 736 is set in a floating state. Accordingly, the logic 720 creates the signals iCLK, iWE, iRE, and iDIN according to the logic of the signals CLK, WE, RE, and DIN, and creates the signal Dout according to the logic of the signal iDout. The memory macro 710 operates according to the logic of the signals iCLK, iWE, iRE, and iDIN and supplies the signal iDout.
Thus, when the mode signal iTEST is at a low level, the memory macro 710 and the logic 720 perform a usual operation. The current consumption In when the mode signal iTEST is at a low level is the total of the current I1 consumed by the memory macro 710 and the current I2 consumed by the logic 720.
The logic 720 is controlled so as to change the mode signal iTEST into a high level signal. According to this, the input switch 717 sets the signals iCLK, iWE, iRE, and iDIN at a high impedance and the output switch 718 sets the signal terminal 716 at a high impedance.
Continuously, the same signals CLK, WE, RE, and DIN as in the usual operation mode are entered from the pads 731 to 734. The logic 720 creates the signals iCLK, iWE, iRE, and iDIN according to the logic of the signals CLK, WE, RE, and DIN, in the same way as in the usual operation mode.
As mentioned above, since the output of the output switch 718 has high impedance and the pseudo test signal TESTDIN is entered from the pad 736, the logic 720 creates the signal Dout by using the pseudo test signal TESTDIN. On the other hand, since the signals iCLK, iWE, iRE, and iDIN are fixed at high impedance, the operation of the memory macro 710 is completely suspended.
Thus, when the mode signal iTEST is at a high level, the logic 720 performs the usual operation and the operation of the memory macro 710 is completely suspended. Accordingly, the current consumption It at this time agrees with the current consumption I2 of the logic 720.
For this reason, the current consumption I1 of the memory macro 710 can be obtained by calculating a difference In−It between the current consumption In of the whole semiconductor integrated circuit 700 and the current consumption It in the test operation mode.
As mentioned above, according to the semiconductor integrated circuit of this embodiment, the current consumption of only the memory macro 710 can be easily and accurately measured.
Since the pseudo test signal TESTDIN is entered to the pad 736 and further supplied to the logic 720, any output signal from the memory macro 710 can be created falsely and arbitrarily and therefore, degree of freedom in the operation test can be enhanced.

Fifth Embodiment

A semiconductor integrated circuit according a fifth embodiment of the invention will be described by using FIG. 11 and FIG. 12. This embodiment provides a semiconductor integrated circuit capable of detecting the current consumption of only the memory macro.
FIG. 11 is a block diagram schematically showing the structure of an important portion of the semiconductor integrated circuit according to this embodiment. In FIG. 11, each component with the same reference numeral as in FIG. 9 attached is the same as in the case of FIG. 9.
As illustrated in FIG. 11, a semiconductor integrated circuit 900 according to this embodiment comprises a pseudo signal switch 910.
The pseudo signal switch 910 supplies the potential of the pad 921 to the signal terminal 716 of the memory macro 710 as the pseudo test signal TESTDIN when the mode signal iTEST is at a high level. On the other hand, when the mode signal iTEST is at a low level, the pseudo signal switch 910 makes the output high impedance.
Although the pad 921 is not illustrated in the semiconductor integrated circuit 700 according to the above-mentioned fourth embodiment (refer to FIG. 9), it is a pad used for inputting and outputting any signal in the usual operation mode (refer to the pad 1330 in FIG. 1).
FIG. 12 is a circuit view showing the internal structure of the pseudo signal switch 910. As illustrated in FIG. 12, the pseudo signal switch 910 comprises an inverter 1001, a pMOS transistor 1002, and an nMOS transistor 1003.
The inverter 1001 inverts the mode signal iTEST entered from the signal terminal 715 and supplies it.
In the transistor 1002, its source is connected to the pad 921, its drain is connected to the signal terminal 716, and its gate is connected to the output terminal of the inverter 1001.
In the transistor 1003, its drain is connected to the pad 921, its source is connected to the signal terminal 716, and its gate is connected to the signal terminal 715.
When the mode signal iTEST is at a high level, the circuit shown in FIG. 12 can apply the potential of the pad 921 to the signal terminal 716 of the memory macro 710 and when the mode signal iTEST is at a low level, it can make the output high impedance.
The operation of the semiconductor integrated circuit 900 of this embodiment is the same as the operation of the semiconductor integrated circuit 700 according to the above-mentioned fourth embodiment, except that the pad 921 is used as a pad for receiving the pseudo test signal TESTDIN.
According to the semiconductor integrated circuit according to this embodiment, the current consumption of only the memory macro 710 can be easily and accurately measured, similarly to the above-mentioned fourth embodiment and any output signal of the memory macro 710 can be created falsely and arbitrarily, thereby enhancing the degree of freedom in the operation test.
Additionally, according to this embodiment, it is not necessary to provide a pad for exclusive use of receiving the pseudo test signal TESTDIN, thereby decreasing the chip size of the semiconductor integrated circuit.
Further, according to this embodiment, it is possible to measure the current consumption after assembling the semiconductor integrated circuit.

Sixth Embodiment

A semiconductor integrated circuit according to a sixth embodiment of the invention will be described by using FIG. 13 and FIG. 14. This embodiment provides a semiconductor integrated circuit capable of detecting the current consumption of only the memory macro.
FIG. 13 is a block diagram schematically showing the structure of an important portion of the semiconductor integrated circuit according to this embodiment. In FIG. 13, each component with the same reference numeral as in FIG. 9 attached is the same as in the case of FIG. 9.
As illustrated in FIG. 13, a semiconductor integrated circuit 1100 according to this embodiment includes a pseudo signal generator 1110.
The pseudo signal generator 1110 supplies the potential (namely, signal iDIN) of the signal terminal 714 to the signal terminal 716 of the memory macro 710 as the pseudo test signal TESTDIN when the mode signal iTEST is at a high level. On the other hand, when the mode signal iTEST is at a low level, the pseudo signal generator 1110 makes the output high impedance.
FIG. 14 is a circuit view showing the internal structure of the pseudo signal generator 1110. As illustrated in FIG. 14, the pseudo signal generator 1110 includes inverters 1201 and 1202 and pMOS transistors 1203 and 1204, and nMOS transistors 1205 and 1206.
The inverter 1201 inverts the mode signal iTEST and supplies it.
The inverter 1202 inverts the signal iDIN and supplies it.
In the pMOS transistor 1203, its source is connected to the power source line VCC and its gate is connected to the output terminal of the inverter 1201.
In the pMOS transistor 1204, its source is connected to the drain of the pMOS transistor 1203 and its gate is connected to the output terminal of the inverter 1202.
In the nMOS transistor 1205, its drain is connected to the drain of the pMOS transistor 1204 and its gate is connected to the output terminal of the inverter 1202.
In the nMOS transistor 1206, its drain is connected to the source of the nMOS transistor 1205, its source is grounded, and the mode signal iTEST is entered from its gate.
When the mode signal iTEST is at a high level, the circuit as shown in FIG. 14 can apply the test signal iDIN to the signal terminal 716 as the pseudo test signal TESTDIN and make the output high impedance when the mode signal iTEST is at a low level.
The operation of the semiconductor integrated circuit 1100 according to this embodiment is the same as the operation of the semiconductor integrated circuit 700 according to the above-mentioned fourth embodiment, except that the test signal iDIN is used as it is as the pseudo test signal TESTDIN.
According to the semiconductor integrated circuit of this embodiment, the current consumption of only the memory macro 710 can be measured easily and accurately and any output signal of the memory macro 710 can be falsely and arbitrarily created, similarly to the forth embodiment above mentioned, thereby enhancing the degree of freedom in the operation test.
Additionally, according to this embodiment, it is not necessary to provide with a pad for exclusive use of receiving the pseudo test signal TESTDIN, thereby decreasing the chip size of the semiconductor integrated circuit.
According to this embodiment, it is possible to measure the current consumption after assembling the semiconductor integrated circuit.
This application is based on Japanese Patent Application No. 2004-109086 which is herein incorporated by reference.

Claims

1. A semiconductor integrated circuit having a circuit to be checked through an operation test, a plurality of pads for receiving test signals from outside, and a plurality of signal paths formed within another circuit in order to lead the test signals entered from the pads to a signal input terminal of the checked circuit in an operation test mode, comprising

a first test pad to which a first pull-up potential is supplied, and

a time lag measuring circuit including a plurality of first transistors in each of which one end is connected to the first test pad, the other end is connected to a power source line, and a control terminal is connected to the corresponding signal input terminal.

2. The semiconductor integrated circuit according to claim 1, comprising

a second test pad to which a second pull-up potential is supplied, and

the time lag measuring circuit including

a second transistor in which one end is connected to the second test pad, the other end is connected to the power source line, and a control terminal is connected to a signal output terminal of the checked circuit,

a third transistor in which one end is connected to the second test pad, the other end is connected to the power source line, and a control terminal is connected to a third test pad, and

a fourth transistor in which one end is connected to the first test pad, the other end is connected to the power source line, and a control terminal is connected to the third test pad.

3. The semiconductor integrated circuit according to claim 2, in which

the first test pad is a pad for use in receiving or supplying another signal in a usual operation mode,

a switch transistor is provided between the first test pad and the one end of the first transistor as well as a power source of the first pull-up potential, and

the switch transistor is turned off in the usual operation mode and turned on in the operation test mode.

4. The semiconductor integrated circuit according to claim 1, in which

5. A semiconductor integrated circuit having a circuit to be checked through an operation test and another circuit for creating an operation control signal of the checked circuit according to a signal entered from outside, comprising

an input switch for supplying the operation control signal to the checked circuit at a time of measuring a current consumption of the whole semiconductor integrated circuit and making output high impedance at a time of measuring a current consumption of the circuit excepting the checked circuit,

an output switch for supplying an output signal of the checked circuit to the other circuit at a time of measuring a current consumption of the whole semiconductor integrated circuit and making output high impedance at a time of measuring a current consumption of the circuit excepting the checked circuit, and

a pseudo signal supplying circuit for supplying a pseudo output signal of the checked circuit to the other circuit at a time of measuring a current consumption of the circuit excepting the checked circuit.

6. The semiconductor integrated circuit according to claim 5, in which

the pseudo signal supplying circuit is wiring for supplying the pseudo output signal entered from a test pad to the other circuit.

7. The semiconductor integrated circuit according to claim 5, in which

the pseudo signal supplying circuit is a pseudo signal switch for making output high impedance at a time of measuring a current consumption of the whole semiconductor integrated circuit and supplying the pseudo output signal entered from a predetermined pad to the other circuit at a time of measuring a current consumption of the circuit excepting the checked circuit.

8. The semiconductor integrated circuit according to claim 5, in which

the pseudo signal supplying circuit is a pseudo signal generator for making output high impedance at a time of measuring a current consumption of the whole semiconductor integrated circuit and supplying one or all of the operation control signal to the other circuit at a time of measuring a current consumption of the circuit excepting the checked circuit.