JP2001153930A - Test circuit for macro cell and test method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable the operation timing in connection to inside to be guaranteed without addition of an extra terminal and function to a macro cell itself by enabling the testing precise timing relation between a clock signal and an input/output data signal or the other control signal to be performed. SOLUTION: The circuit comprises an input terminal T13 of a testing input clock signal CK1 connected to an end of a common bus circuit 2 and a test input/output circuit 3A with an output terminal T32 of an output clock signal CKO retuned from the other end of the common bus circuit 2 in test operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a macro cell test circuit and a test method thereof, and more particularly, to an A / D converter and a D / A built in a large-scale semiconductor integrated circuit (LSI).
The present invention relates to a macrocell test circuit for testing a delay time characteristic of an analog macrocell such as a converter and a test method thereof.

[0002]

2. Description of the Related Art A large-scale LSI of this kind is composed of an analog macrocell such as an A / D converter or a D / A converter designed as a relatively large standard function block, and a logic circuit including a logic macrocell and a standard basic cell. It is configured by combining with blocks.

However, a macrocell such as an analog macrocell cannot directly measure an input / output signal of a connection portion between the macrocell and an internal circuit, that is, an interface portion when performing a characteristic test. The test must be performed by supplying a signal from an external terminal.

Japanese Patent Laid-Open No. 2-1184 shows an example of a test circuit for a macro cell of a large-scale LSI including such a macro cell.
Referring to FIG. 7 which shows a block diagram of a test circuit of a conventional first macro cell described in Japanese Patent Application Publication No. 75 (Reference 1), the test circuit of the conventional first macro cell includes an A / A
A macro cell 1 as a D converter, a common test bus 2 for transmitting input / output signals for testing the macro cell 1, and a test input / output unit 3 for input / output signals for testing the macro cell 1
And a test control circuit 5 for controlling the test of the macro cell 1 and interfacing with the internal circuit 10 of the LSI.

The macro cell 1 has an input terminal for an analog input signal A supplied from the outside and a reference voltage V output to the outside.
An external terminal 11 including an R output terminal is provided.

The test input / output unit 3 includes an input buffer 31 at an input terminal T31 for a test input clock signal CKI,
An output buffer 33 of a plurality of output terminals T33 of a plurality of test output data DT from the macro cell 1 and an input buffer 3 of an input terminal T34 of an external test control signal CT.
4 is provided.

A test control circuit 5 selectively switches a clock signal source of the macrocell 1 to be connected to either the internal circuit 10 or the common test bus 2 in accordance with the selection of the operation mode. Circuit 51
And a data selection circuit 52 for selectively switching input / output destinations of the control signal and the data output signal to one of the internal circuit 10 and the common test bus 2 in accordance with the selection of the operation mode. .

Next, referring to FIG. 7, FIG. 8 showing a time chart of waveforms of respective parts, and FIG. 9 showing a flowchart of a test procedure by the test circuit, operation of the conventional first macro cell test circuit and its operation will be described. The test method will be described. First, at the time of normal operation, the test control circuit 5 switches to connect the macrocell 1 to the internal circuit 10 by setting the normal operation mode. As a result, the control signal C and the clock signal CK are supplied from the internal circuit 10 to the macro cell 1, and by supplying the analog input signal A to the external terminal 11 of the macro cell 1, the macro cell 1 outputs the corresponding output data D to the internal circuit 10. Perform the normal operation of supplying to the.

Next, at the time of testing, the test control circuit 5 switches to connect the macro cell 1 to the common test bus 2 by setting a test mode (step P1). As a result, the control signal CT and the input clock signal CKI are supplied from the test input / output unit 3 to the macro cell 1 via the common test bus 2 and the analog input signal A is supplied to the external terminal 11 of the macro cell 1 (step P
2), the macro cell 1 performs a test operation of supplying the corresponding output data DT to the test input / output unit 3 via the common test bus 2. The output data DT is monitored, the timing at which the expected value is output to the output data is searched, and the delay time t
d is obtained (step P3).

During the test operation, the test input / output unit 3
The input buffer 31 of the input terminal T31 of the test input clock signal CKI of FIG.
One delay has occurred. The test input / output unit 3
The common test bus 2 from the test control circuit 5 to the test control circuit 5 causes a delay of the wiring delay time t2 at a point b which is a connection point of the selection circuit 51 of the test control circuit 5 with the common test bus 2.

Further, for an output data signal from the macro cell 1, a wiring delay time due to the macro common test bus 2 similar to the input signal at a point c which is a connection point between the common test bus 2 and the test input / output unit 3. A delay of t3 has occurred. Furthermore, the test data DT of the test input / output unit 3
The output test data DT at point d, which is the output terminal T33, is delayed by the output buffer 33 of the output terminal T33.
4 delays have occurred.

That is, when measuring the macrocell 1, delay times t1 and t2 are always added to a test input signal, and delay times t3 and t4 are always added to an output signal. Therefore, the conventional test circuit of the first macrocell cannot test an accurate timing relationship between the clock signal and the input / output data signal or another control signal.

Therefore, the test in this case is a test based on a standard having a margin for confirming the operation, that is, a judgment of only the operation confirmation (step P4).

Therefore, even if the operation of the macro cell alone can be confirmed, the operation timing in connection with the internal circuit cannot be guaranteed, and if a memory block that cannot be simulated by timing simulation is directly connected inside the LSI, the The timing at the connection becomes completely unknown. As a recent trend, the operation has become faster, and these timing problems have become a major problem. If this kind of problem occurs in mass production, it is impossible to distinguish whether the macro cell is bad or the timing design of the entire LSI is bad.

Japanese Patent Application Laid-Open No. 4-34 for solving the above problem
No. 383, the conventional test circuit for a second macro cell and the test method therefor include a macro cell in addition to an input / output terminal for an original function, a delay time measurement mode switching signal,
A dedicated terminal for inputting a test signal dedicated to delay time measurement, and a switching circuit for switching between an output for an original function and an input test signal in response to a delay time measurement mode switching signal; Is input to a test circuit for characteristic test. At the time of delay time measurement, the test signal is supplied to a macro cell from a dedicated input terminal in accordance with the delay time measurement mode switching signal, and the macro cell outputs the test signal to an output terminal of the test circuit, and inputs and receives the test signal. The delay time of the test circuit is measured by comparing the output timings.
However, the second conventional test circuit for a macro cell and the test method thereof are provided with at least two input terminals dedicated to testing that are not required for the macro cell itself, and a circuit for switching between an output for an original function and an input test signal. Therefore, it becomes a factor of increasing the complexity and area of the macro cell, and also complicates the test procedure.

[0016]

The above-described first conventional macrocell test circuit and its test method cannot measure the delay time due to the wiring and the input / output buffer inside the test circuit, so that the clock signal and the input / output data signal cannot be measured. However, there is a drawback that the operation timing cannot be guaranteed in connection with the inside even though the operation can be confirmed by the macro cell alone because the accurate timing relationship with the control signal and other control signals cannot be tested.

The second conventional test circuit for a macro cell which solves the above-mentioned drawbacks is provided with at least two test-dedicated input terminals which are originally unnecessary in the macro cell itself, and further comprises an output for an original function and an input test signal. It is necessary to provide such a switching circuit, which causes the complexity and the area of the macro cell to increase, and also has the disadvantage that the test procedure becomes complicated.

An object of the present invention is to make it possible to test an accurate timing relationship between a clock signal and an input / output data signal or another control signal without adding an extra terminal or function to the macrocell itself, thereby enabling the internal and external macro cells to be tested. It is an object of the present invention to provide a macro cell test circuit capable of guaranteeing the operation timing at the connection of.

[0019]

According to a first aspect of the present invention, a test circuit for a macro cell includes an A / D converter or a D / D converter to be measured.
The macro cell via test signal transmission means for transmitting an input / output signal for testing the macro cell of a large-scale semiconductor integrated circuit configured by combining an analog macro cell which is an A converter and an internal circuit comprising a logic circuit block A test circuit connected to one end of the test signal transmission means and an input terminal of a test clock signal, and the test clock returned from the other end of the test signal transmission means during a test operation. And a test input / output circuit having a signal output terminal.

The test signal transmitting means may include a common test bus for transmitting input / output signals for testing the macro cell.

Further, the macro cell is an A / D converter, and is arranged near an input / output terminal of the macro cell to the internal circuit, to which an input / output signal of the macro cell is connected in accordance with each mode of a normal operation and a test operation. And selecting and connecting one of the internal circuit and the other end of the test signal transmitting means, and branching the test clock signal transmitted to the input terminal of the macro cell during a test mode operation, thereby dividing the macro cell A test control circuit for supplying to the other end of the test signal transmission means together with the output data of the test signal transmission means, wherein the test input / output circuit outputs output data from the macro cell output from one end of the test signal transmission means during a test. A test data output terminal may be provided.

Further, the macro cell is a D / A converter, and is arranged near an input / output terminal of the macro cell to the internal circuit, to which an input / output signal of the macro cell is connected in accordance with each mode of a normal operation and a test operation. And selecting and connecting one of the internal circuit and the other end of the test signal transmission means, and branching the test clock signal transmitted to the input terminal of the macro cell during a test mode operation to perform the test. A test control circuit for supplying to the other end of the signal transmission means and receiving supply of input data for testing the macro cell from the other end of the test signal transmission means, wherein the test input / output circuit is configured so that the macro cell And a test data input terminal for inputting the test input data to one end of the test signal transmission means.

Further, the test input / output circuit may include an input buffer connected to an input terminal of the test clock signal, and an output buffer connected to an output terminal of the test clock signal.

Further, the test input / output circuit may include an input buffer connected to the test data input terminal.

Further, the input buffer and the output buffer may be three-state buffers having control terminals for activating and deactivating the buffers.

According to a second aspect of the present invention, there is provided a method for testing a macro cell.
Via a common test bus for transmitting input / output signals for testing the macrocell of a large-scale semiconductor integrated circuit configured by combining an analog macrocell that is an A / D converter to be measured and an internal circuit composed of a logic circuit block A first step of setting a test operation mode; and a second step of receiving a test clock signal and supplying a predetermined analog input signal to the macro cell. And measuring the output data delay time by comparing the timing of test output data output from the macro cell and output to the test data output terminal via the common test bus with the input timing of the analog input signal. Step and input from test clock input terminal A fourth step of measuring the clock delay time by comparing the input timing of the test clock signal and the output timing of the test clock signal output to the test clock output terminal reciprocating on the common test bus. And a fifth step of obtaining a delay time of the macro cell from a difference between the output data delay time and the clock delay time.

According to a third aspect of the invention, there is provided a method for testing a macro cell,
Via a common test bus for transmitting input / output signals for testing the macro cell of a large-scale semiconductor integrated circuit configured by combining an analog macro cell which is a D / A converter to be measured and an internal circuit comprising a logic circuit block A first step of setting a test operation mode; and inputting a test clock signal, and transmitting predetermined test input data from a test data input terminal to the macro cell test circuit for testing timing characteristics of the macro cell. A second step of supplying the macro cell via the common test bus, and comparing an output analog signal timing output from the macro cell with an input timing of the test input data to measure an output analog signal delay time. 3rd step and test clock input terminal A clock delay time is measured by comparing the input timing of the input test clock signal with the output timing of the test clock signal output to the test clock output terminal while reciprocating on the common test bus. A fourth step of calculating a correction delay time by halving the time, and a fifth step of obtaining a delay time of the macro cell from a difference between the output data delay time and the correction delay time. It is a feature.

[0028]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

The macrocell test circuit of the present embodiment combines an analog macrocell such as an A / D converter or a D / A converter to be measured with an internal circuit composed of a logic circuit block such as a logic macrocell or a standard basic cell. The macro cell of the large-scale semiconductor integrated circuit (LSI) configured as described above is tested, and a test input / output terminal of a test input / output signal of the macro cell is provided with an output terminal of a test output clock signal. By comparing the input timing (time) of the input clock signal at the test input / output terminal with the output timing of the corresponding output clock signal, the delay time of the test circuit including the common test bus and the associated input / output buffer is measured. It is characterized by the following.

Next, referring to FIG. 1 which shows the first embodiment of the present invention, in which constituent elements common to those in FIG. The macrocell test circuit of the present embodiment includes a macrocell 1 which is an A / D converter to be measured in common with a conventional one, and a common test bus 2 for transmitting input / output signals for testing the macrocell 1 and a test circuit. An output terminal T32 for outputting a test output clock signal CKO instead of the input / output unit 3
And a test input / output unit 3A for a clock input / output signal for testing the macro cell 1 having the following configuration. The test input / output unit 3A is arranged in the vicinity of the input / output terminal to the internal circuit 10 of the macro cell 1 in place of the test control circuit 5, and operates in the normal operation mode and the test operation mode. According to the setting, one of the internal circuit 10 of the LSI and the common test bus 2 is selected as the connection destination of the input / output signal of the macro cell 1 and the test signal transmitted to the input terminal of the macro cell 1 during the test mode operation. Control of test of macro cell 1 including supply of output clock signal CKO obtained by branching clock signal CKI and output test data DT from macro cell 1 to common macro test bus 2 and test control for interfacing with internal circuit 10 of this LSI Circuit 5A.

The macro cell 1 has an external terminal 11 including an input terminal for an analog input signal AI supplied from the outside and an output terminal for a reference voltage VR to be output to the outside.

The test input / output unit 3A is connected to the input buffer 31 of the input terminal T31 of the test input clock signal CKI.
An output buffer 32 of an output terminal T32 for outputting a test output clock signal CKO, and a plurality of output terminals T33 of a plurality of test output data DT from the macrocell 1.
Output buffer 33 and an external test control signal CT
And an input buffer 34 of an input terminal T34.

The input buffers 31, 34 and the output buffers 32, 33 of the test input / output unit 3A are necessary only when the test input / output signal is used for the test, and are not needed during the normal operation. And a three-state buffer having control terminals for activation and deactivation, and activated only when the operation mode is the test mode.

The test control circuit 5A selectively connects the clock signal supply source of the macro cell 1 to one of the internal circuit 10 and the common test bus 2 according to the selection of the operation mode. A clock selection circuit 51 for switching, and a data selection circuit for selectively switching input / output destinations of a control signal and a data output signal to one of the internal circuit 10 and the common test bus 2 according to the selection of the operation mode. In addition to the selection circuit 52 of
A switch circuit 53 is connected to return the input test clock signal CKI branched at the output end of the selection circuit 51 as a test output clock signal CKO in the test mode and outputs the same to the common test bus 2.

Next, referring to FIG. 1, FIG. 2 showing a time chart of the waveforms of the respective parts, and FIG. 3 showing a test procedure by the test circuit in a flow chart, the operation of the test circuit of the macro cell of this embodiment and its operation will be described. The test method will be described. First, during normal operation, the test control circuit 5A switches the macrocell 1 to connect to the internal circuit 10 by setting the normal operation mode. Thus, the control signal C and the clock signal CK for normal operation are supplied from the internal circuit 10 to the macro cell 1 via the selection circuits 52 and 51, respectively, and the analog input signal AI is supplied to the external terminal 11 of the macro cell 1. Accordingly, the macro cell 1 performs a normal operation of supplying the corresponding output data D to the internal circuit 10. At this time, the switch circuit 53 is off.

Next, at the time of testing, by setting the test mode, the test control circuit 5A switches the macro cell 1 so as to be connected to the common test bus 2 and also outputs the input clock signal CKI input via the common test bus 2 to the macro cell. 1 and the switch circuit 53 is turned on so that the signal is returned to the common test bus 2 again as the test output clock signal CKO (step S).
1).

Thus, the test input clock signal CKI is supplied from the test input / output unit 3A to the macro cell 1 via the common test bus 2, and the output selection circuit 5
1A, the input clock signal CKI reaches the macro cell 1
At the input end of the macrocell 1 and is returned to the test input / output unit 3A via the switch circuit 53 and the common test bus 2 again to be output to the output buffer 3A.
2 and output to a terminal T32 as a test output clock signal CKO. By supplying a predetermined analog input signal AI to the external terminal 11 of the macro cell 1, the macro cell 1 performs A / D conversion and supplies corresponding output data DT to the test input / output unit 3A via the common test bus 2. A test operation is performed (Step S2).

The output data DT at the terminal T33 of the test input / output section 3A is monitored, the timing at which the expected value is output as the output data is searched, and the data delay time td with respect to the input timing of the input analog signal AI is obtained (step S3). ).

The clock delay time tc, which is the difference between the output clock signal CKO at the terminal T32 of the test input / output unit 3A and the input clock signal CKI at the terminal T31, is measured (step S4).

The clock delay time tc is expressed by the following equation.

Tc = t1 + t2 + t3 + t4 (1) Here, t1 is from the test input / output unit 3A to the output end of the input buffer 31, that is, the input buffer 31 T2 is the wiring delay time of the common test bus 2 from the output end of the input buffer 31 to the output side of the selection circuit 51 of the test control circuit 5A, and t3 is the output side of the selection circuit 51 of the test control circuit 5A. Is the wiring delay time of the common test bus 2, and t4 is the delay time from the input end of the output buffer 32 to the terminal T32, that is, the delay time of the output buffer 32.

Next, a macro delay time t0 = td-tc, which is a true delay time of the macro cell 1, is determined, and it is determined whether or not the macro delay time t0 is within the standard (step S5).

As described above, the test circuit of the macro cell of this embodiment includes the delay time of each buffer of the test input / output unit 3A and the wiring delay time of the common test bus 2 due to the reciprocation of the test clock signal. Since the delay time of the test circuit can be accurately measured, the output through the same common test bus 2 and the output buffer 33 having the same characteristics as the input / output buffer for the clock signal CKI / CKO is provided without any additional circuit in the macrocell itself. By comparing the timing of the test data DT with each timing of the clock signals CKI / CKO, an accurate timing test of the macro cell 1 can be performed.

Next, a second embodiment of the present invention will be described with reference to FIG. 4 in which constituent elements common to those in FIG. The difference between the present embodiment and the first embodiment is that the macro cell 1A to be measured is a D / A converter, and accordingly, the test data DT is input instead of the test input / output unit 3A. Input / output unit 3B having an input buffer 33A for the macro cell 1 and a macro cell 1 arranged in the vicinity of the input / output terminal to the internal circuit 10 of the macro cell 1 in place of the test control circuit 5A in accordance with the setting of the normal operation mode and the test operation mode Is connected to the internal circuit 10 of this LSI.
And the common test bus 2 are selected and the output clock signal CKO obtained by branching the test clock signal CKI transmitted to the input terminal of the macro cell 1 during the test mode operation is supplied to the common test bus 2 and shared. A test control circuit 5B for controlling the test of the macro cell 1A including the input of the input test data DT from the macro test bus 2 to the macro cell 1 and for interfacing with the internal circuit 10 of the LSI is provided.

The macro cell 1A has an external terminal including an output terminal for an analog signal AO for D / A converting the input data supplied via the test control circuit 5B and outputting the converted data to the outside, and an input terminal for a reference voltage VR input from the outside. 11A.

The test control circuit 5B includes a selection circuit 51,
In addition to the switch circuit 53, the input destinations of the control signal and the data output signal are changed according to the selection of the operation mode.
And a data selection circuit 52A for selectively switching to be connected to either one of the common test bus 2 and the common test bus 2.

Next, FIG. 4 is a time chart showing waveforms of respective parts, and FIG. 3 shows a test procedure by this test circuit.
The operation of the test circuit of the macro cell according to the present embodiment and its test method will be described with reference to FIG. During normal operation, the test control circuit 5B switches the macrocell 1A to connect to the internal circuit 10 by setting the normal operation mode. As a result, the control signal C, the input data DI to be D / A converted, and the clock signal CK for normal operation are supplied to the macro cell 1 from the internal circuit 10 via the selection circuits 52A and 51, respectively. A / D of data DI
The normal operation of performing the conversion and outputting the analog output signal AO to the external terminal 11A is performed.

Next, at the time of testing, by setting the test mode, the test control circuit 5B switches the macro cell 1 so as to be connected to the common test bus 2 and also outputs the input clock signal CKI input via the common test bus 2 to the macro cell. It is set to branch at the input terminal of No. 1 and return to the common test bus 2 again as the test output clock signal CKO (step S1).

Thus, the test input clock signal CKI is supplied from the test input / output unit 3B to the macro cell 1 via the common test bus 2, and the input clock signal CKI reaching the test control circuit 5A is supplied to the macro cell 1
At the input end of the macrocell 1 and returned to the test input / output unit 3A via the common test bus 2 again, input to the output buffer 32, and
32 is output as a test output clock signal CKO. By inputting test input data DT from the data input terminal T33 of the test input / output unit 3B and supplying it to the macro cell 1A via the common test bus 2 and the selection circuit 52A of the test control circuit 5B, the macro cell 1A receives this input data. D / A conversion of DT and corresponding analog output signal A
A test operation of outputting O from the external terminal 11A is performed (step S2A).

That is, the difference between the timing of the test input data DT at the data input terminal T33 of the test input / output unit 3B and the timing of the analog output signal AO becomes the data delay time td (step S3A).

The clock delay time tc, which is the difference between the output clock signal CKO at the terminal T32 of the test input / output unit 3B and the input clock signal CKI at the terminal T31, is measured, and the correction time te is obtained from the following equation ( Step S
4A). te = tc / 2 = (t1 + t2 + t3 + t4) / 2 = t1 + t2 (2) In the case of the D / A converter, unlike the A / D converter,
Since the signal whose timing is to be compared is an analog output signal, it is not necessary to consider the delay time of this analog output signal AO. Therefore, when testing the timing relationship between the clock signal CKI / CKO and the analog output signal AO, the clock signal CKO is input from the input of the clock signal CKI.
Of the clock delay time tc up to the output, the clock delay time t1 + t2 required for the input is the above-described correction time te.

Next, a macro delay time t1 = td-te, which is a true delay time of the macro cell 1A, is determined, and it is determined whether or not the macro delay time t1 is within the standard (step S5).
A).

[0053]

As described above, the macrocell test circuit and the test method according to the present invention provide a test clock signal input terminal connected to one end of a test signal transmission means, and a test signal transmission means for performing a test operation. Since the test input / output circuit has an output terminal for the test clock signal returned from the other end, the delay time of each buffer of the test input / output terminal and the common test bus Since the delay time of the test circuit including the wiring delay time can be measured accurately, the timing of the output test data via the same common test bus and the output buffer with the same characteristics as each of the input / output buffers for each clock signal for input / output By comparing each timing of the input and output clock signals, the macro cell itself must have any additional circuits. Ku, there is an effect that it is the timing test accurate analog macro cell.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a test circuit for a macro cell according to the present invention.

FIG. 2 is a time chart showing an example of an operation in the test circuit of the macro cell of the present embodiment.

FIG. 3 is a flowchart illustrating an example of an operation in the test circuit of the macro cell according to the present embodiment;

FIG. 4 is a block diagram showing a second embodiment of a test circuit for a macro cell according to the present invention.

FIG. 5 is a time chart illustrating an example of an operation in the test circuit of the macro cell according to the present embodiment;

FIG. 6 is a flowchart showing an example of an operation in the macro cell test circuit of the present embodiment.

FIG. 7 is a block diagram showing an example of a conventional test circuit for a first macro cell.

FIG. 8 is a time chart showing an example of an operation in a test circuit of a conventional first macro cell.

FIG. 9 is a flowchart showing an example of an operation in a conventional test circuit of the first macro cell.

[Explanation of symbols]

 1, 1A macrocell 2 common test bus 3, 3A, 3B test input / output unit 5, 5A, 5B test control circuit 10 internal circuit 11, 11A external terminal 31, 34, 33A input buffer 32, 33 output buffer 51, 52, 52A Selection circuit 53 Switch circuit

Claims (10)

[Claims] 1. An A / D converter or D / A to be measured
An analog macrocell, which is a converter, and an internal circuit composed of a logic circuit block are combined with each other through a test signal transmission unit for transmitting an input / output signal for testing the macrocell of the large-scale semiconductor integrated circuit. In a test circuit of a macro cell for testing timing characteristics, an input terminal of a test clock signal connected to one end of the test signal transmission means, and the test clock signal returned from the other end of the test signal transmission means during a test operation And a test input / output circuit having an output terminal of the macro cell. 2. The test circuit for a macro cell according to claim 1, wherein said test signal transmission means includes a common test bus for transmitting an input / output signal for testing the macro cell. 3. The macrocell is an A / D converter, and is disposed near an input / output terminal of the macrocell to the internal circuit, to which an input / output signal of the macrocell is connected in accordance with each mode of a normal operation and a test operation. And selecting and connecting one of the internal circuit and the other end of the test signal transmitting means, and branching the test clock signal transmitted to the input terminal of the macro cell during a test mode operation, thereby dividing the macro cell A test control circuit for supplying to the other end of the test signal transmission means together with the output data of the test signal transmission means, wherein the test input / output circuit outputs output data from the macro cell output from one end of the test signal transmission means during a test 2. The test circuit for a macro cell according to claim 1, further comprising: a test data output terminal. 4. The macro cell is a D / A converter, and is arranged near an input / output terminal of the macro cell to the internal circuit, to which an input / output signal of the macro cell is connected according to each mode of a normal operation and a test operation. And selecting and connecting one of the internal circuit and the other end of the test signal transmission means, and branching the test clock signal transmitted to the input terminal of the macro cell during a test mode operation to perform the test. A test control circuit for supplying to the other end of the signal transmission means and receiving supply of input data for testing the macro cell from the other end of the test signal transmission means, A test data input terminal for inputting the test input data to one end of the test signal transmission means. Test circuit of the macrocell of 1, wherein the. 5. The test input / output circuit includes an input buffer connected to an input terminal of the test clock signal and an output buffer connected to an output terminal of the test clock signal. 2. The test circuit for a macro cell according to claim 1. 6. The test circuit according to claim 3, wherein the test input / output circuit includes an output buffer connected to the test data output terminal. 7. The test circuit according to claim 4, wherein the test input / output circuit includes an input buffer connected to the test data input terminal. 8. The test circuit for a macro cell according to claim 5, wherein the input buffer and the output buffer are three-state buffers having control terminals for activating and deactivating the buffers. . 9. An input / output signal for testing the macro cell of a large-scale semiconductor integrated circuit configured by combining an analog macro cell which is an A / D converter to be measured and an internal circuit composed of a logic circuit block is transmitted. In a macro cell test method for testing timing characteristics of the macro cell via a common test bus, a first step of setting a test operation mode, a test clock signal is input, and a predetermined analog input signal is transmitted to the macro cell And a timing of test output data output from the macro cell and output to a test data output terminal via the common test bus with an input timing of the analog input signal. The third step of measuring the test clock Measuring the clock delay time by comparing the input timing of the test clock signal input from the input terminal with the output timing of the test clock signal output to the test clock output terminal after reciprocating through the common test bus. 4. A macro cell test method, comprising: a fourth step; and a fifth step of obtaining a delay time of the macro cell from a difference between the output data delay time and the clock delay time. 10. An I / O signal for testing a macro cell of a large-scale semiconductor integrated circuit configured by combining an analog macro cell which is a D / A converter to be measured and an internal circuit comprising a logic circuit block is transmitted. In a macro cell test method for testing timing characteristics of the macro cell via a common test bus, a first step of setting a test operation mode, a test clock signal is input, and a predetermined test is performed from a test data input terminal. A second step of supplying test input data to the macro cell via the common test bus, and comparing a timing of an output analog signal output from the macro cell with an input timing of the test input data to output an analog signal. The third step of measuring the delay time, for testing A clock delay time is measured by comparing the input timing of the test clock signal input from the lock input terminal with the output timing of the test clock signal output to the test clock output terminal after reciprocating on the common test bus. A fourth step of calculating a correction delay time by halving the clock delay time, and a fifth step of obtaining a delay time of the macro cell from a difference between the output data delay time and the correction delay time. A method for testing a macro cell, comprising: