JPH0136597B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to integrated circuit chips suitable for testing. In particular, the present invention relates to an integrated circuit chip suitable for testing signal propagation delay times of large-scale integrated logic circuits.

Conventionally, two methods have been used to test propagation delay times in large scale integrated circuit chips of this type.

That is, the first method is to directly measure the propagation delay time along the signal propagation path of the integrated circuit chip under test. This has been a conventional method, but as the degree of integration and the number of input/output pins of integrated circuit chips improve, the number of signal propagation paths to be inspected increases rapidly, and the inspection time itself increases. Not only does this increase the amount of time required, but it also requires a large amount of time to generate the input signal sequence that activates the path under test. In order to solve this problem, an economical method of testing only representative routes to be tested may be considered. However, advances in integrated circuit technology are accompanied by improved performance of devices, so the propagation delay time of integrated circuit chips has become almost the same time domain as the measurement error of general-purpose integrated circuit testing machines, and the propagation delay time has become more accurate. is difficult to measure.

The second method is to place a test chip using the same basic circuit as that forming the integrated circuit on the wafer at a specific location on the wafer during the integrated circuit chip manufacturing process. By inspecting the propagation delay time characteristics of the chips, it is determined whether the propagation delay time of the integrated circuit chips of the entire wafer is acceptable. This method is based on the fact that variations in the characteristics of integrated circuit chips on the same wafer are generally very small. To test propagation delay time characteristics using this method, a multi-stage basic circuit array is formed on a test chip to an extent that allows the measurement accuracy of a general-purpose integrated circuit tester, and the propagation delay of the basic circuit array is This is done by measuring time. Alternatively, this can be done by forming a closed loop of a basic circuit in which the signal can run freely on a test chip and measuring its oscillation frequency.

Although this method is effective for determining pass/fail before assembly of integrated circuit chips, it is no longer applicable when classifying integrated circuit chips based on propagation delay time in the final product.

For this reason, the integrated circuit chip is equipped with a circuit that forms a closed loop that causes oscillation in the logic circuit by a control signal, and by observing the oscillation frequency from the outside, the signal propagation delay time can be measured indirectly. One possible method is to test the However, this method has the disadvantage that a general-purpose integrated circuit testing machine cannot test such a high oscillation frequency, and a dedicated frequency measuring device is required.

The present invention improves this point, and aims to provide an integrated circuit chip whose propagation delay time can be measured indirectly and with high accuracy using a general-purpose integrated circuit tester. .

The present invention provides a control input having a first state and a second state, and a control input that performs a normal logic function when the control input is in the first state and when the control input is in the second state. The present invention includes means for forming a closed loop in which the signal can run freely by applying a steady input signal of a specific pattern to an input other than the control input, and a frequency dividing circuit that receives the free-running signal as input. Features.

The present invention constructs a closed loop by applying a specific control signal to a part of a logic circuit formed in an integrated circuit during measurement, and separates a circuit in which free-running oscillation occurs and the frequency of this free-running oscillation. The device is characterized in that it includes a frequency-divided circuit and a terminal for measuring the frequency-divided output of this circuit.

An embodiment of the present invention will be described based on the drawings.
FIG. 1 is a block diagram of the main parts of the integrated circuit chip of the present invention. An internal signal a of a logic circuit 3 having an input terminal 1 and an output terminal 2 is guided to one input terminal of an AND circuit 5. This AND circuit 5
Control signals b, which are two types of state signals, are led to other input terminals of the . The output of this AND circuit 5 is led to the logic circuit 3 and also to the frequency divider circuit 6.

With this configuration, when the control input signal b is logic "0", the internal signal a is prevented from propagating by the AND circuit 5, and the output signal c of the AND circuit 5 is
is constantly at logic "0". In this case, the logic circuit 3 performs its original logic function between its input terminal 1 and output terminal 2.

On the other hand, when the control signal b is logic "1", the internal signal a passes through the AND circuit 5 and is propagated to the logic circuit 3. The signal c input to the logic circuit 3 is input to a position within the logic circuit 3 such that it has a path that allows it to reach the internal signal a, but in this case, the path is such that the control signal b is a logic "1". By applying a certain specific pattern input to the input terminal 1, a closed loop including the AND circuit 5 is formed. This closed loop is formed such that the signal polarity is reversed each time it propagates through the loop. Therefore,
Under the above conditions, the signal will run free in this closed loop. That is, it oscillates at a constant frequency, and this oscillation frequency is accurately associated with the signal propagation delay time of this closed loop.

This signal c is simultaneously connected to a frequency dividing circuit 6, and the frequency dividing circuit 6 divides the frequency of this input signal c and sends out the result as an output signal d.

Here, FIG. 2 shows a block diagram of the main part of the frequency dividing circuit 6. As shown in FIG. This frequency dividing circuit 6 is constructed by cascading N T-type flip-flops 8 ₁ to 8 _o .

FIG. 3 is an operation time chart showing the input or output waveforms at the points indicated by the x marks in FIG.

The input signal c to the frequency divider circuit 6 is divided into 1/2 by the output of the first flip-flop ₈₁ , and the output of the second flip-flop ₈₂ which receives this output is further divided into 1/2. Similarly, the Nth flip-flop 8 _N output d is frequency-divided by 1/2 _N with respect to the input signal c.

Here, the number N of flip-flops in the frequency divider circuit 6 is determined so that the frequency of the output d of the frequency divider circuit 6 is equal to or lower than the maximum operating frequency of a general-purpose integrated circuit testing machine. The period and pulse width of the output signal d of this frequency dividing circuit 6 are determined by the input signal c
It is clear that it corresponds exactly to the signal propagation delay time of the closed loop. Generally, general-purpose integrated circuit testers have a function that uses the oscillation signal as the basic clock of the integrated circuit tester when the integrated circuit chip under test has an oscillation frequency that is lower than the maximum operating frequency of the integrated circuit tester. There is. Therefore, the frequency divider circuit 6 of the integrated circuit chip of the present invention
It is possible to use the output signal d of the above-mentioned general-purpose integrated circuit tester as the basic clock. It is also possible to measure the pulse width of the transmitted signal using the built-in time measurement function.

The basic clock for general-purpose integrated circuit testing machines is currently 20M.
A frequency of approximately Hz (that is, a period of 50 ns) is normal, and the time measurement accuracy in this case is approximately ±1 ns. If the delay time in a high-performance large-scale integrated circuit is, for example, 2 ns, the accuracy will be ± ± even if it is directly measured.
50%, which is not practical. However, if the present invention is applied to form a closed loop with a delay time of, for example, 2 ns, the oscillation frequency of the closed loop will be 250 MHz (that is, a period of 4 ns), so if the number N of flip-flops is selected to be 4, the frequency will be divided. The resulting frequency is 250MHz/2 ⁴ = 15.625MHz (period 64ns). This frequency can be used as the basic clock for general-purpose integrated circuit testers. In this state,
When measuring the pulse width (32ns), the accuracy is ±
This is approximately 3.125%, which is equivalent to indirectly measuring the 2 ns delay time with an accuracy of ±3.125%.

It is also possible to further improve accuracy by increasing the value of N.

As explained above, according to the present invention, a closed loop is formed in which a control signal is given and the control signal causes oscillation in a logic circuit, and a frequency dividing circuit for the oscillation frequency is provided. Therefore, the propagation delay time of an integrated circuit chip can be indirectly
Moreover, it has the effect of being able to be measured with high precision using a general-purpose integrated circuit testing machine.

[Brief explanation of drawings]

FIG. 1 is a block diagram of essential parts of an embodiment of the present invention. FIG. 2 is a block diagram of the main parts of the frequency divider circuit. FIG. 3 is a diagram showing input or output waveforms at the points marked with an x in FIG. 2. DESCRIPTION OF SYMBOLS 1...Input terminal, 2...Output terminal, 3...Logic circuit, 5...AND circuit, 6...Frequency divider circuit, ₈₁ to _8o ...flip-flop.

Claims (1)

[Claims] 1 Construct a closed loop by applying a specific control signal to a part of the logic circuit formed in the integrated circuit during measurement, and divide the frequency of the circuit in which free-running oscillation occurs and the frequency of this free-running oscillation within the closed loop. An integrated circuit chip including a circuit and terminals for measuring the divided output of the circuit.