JP2000214223A - Method for measuring delay time - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make easily measurable the delay time by setting both of two latches constituting an FF to a slave mode during the time in a test mode. SOLUTION: A test mode signal is set to 1 and a clock input signal is set to 0. At this point, all latches 2 and 3 constituting an FF become a slave mode. Then, scan input is changed from 0 to 1. After passing the latch of the slave mode in all FFs 8, 9, and 10 on a scan chain, the signal is outputted from an output buffer 11. The difference between the input signal of an input buffer 1 and the output signal of an output buffer 11 is measured as the total of the delay time of the latch in all FFs 8, 9, and 10 on the scan chain. By this measurement, delay time in a semiconductor integrated circuit can be evaluated by a small-scale test circuit and a simple test pattern.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for measuring a delay time of a semiconductor integrated circuit.

[0002]

2. Description of the Related Art There is a scan test as a test method for a semiconductor integrated circuit. Since a test pattern with a high fault detection rate is generated and used by the ATPG, this is a very effective method for detecting a fault such as a bridge of a wiring in a semiconductor integrated circuit.

However, in the scan test mode, high-speed operation cannot be performed depending on the circuit configuration. Therefore, a test circuit is added using a dedicated test pattern capable of measuring the delay value of the critical path, and the output of the critical path is output to the outside. Remove and measure the delay time. In addition, as the scale of the integrated circuit increases, it becomes difficult to specify the critical path. Therefore, the critical path is specified using a static timing analysis tool, and a test pattern capable of observing the delay time is created.

FIG. 2 is a circuit diagram of a semiconductor integrated circuit for explaining a conventional delay time measuring method. In FIG. 2, 20 is an input buffer, 21 and 23 are flip-flops, 22 is a critical path, 24 is a selector, and 25 is an output buffer. 26 denotes a clock input, and 27 denotes a test input of the selector 24. In the selector 24, when the test input is “1”, the output of the critical path 22 is selected.
The data is output to the outside of the semiconductor integrated circuit.

FIG. 3 shows a timing chart of the operation of FIG.

In FIG. 3, reference numeral 28 denotes a signal corresponding to the test mode 27 shown in FIG. 2. Similarly, 29 denotes a D input of the flip-flop 21 of FIG. 2, 30 denotes a clock input of the flip-flop 21 of FIG. Output buffer 25 of FIG.
5 shows an output signal of the first embodiment.

The measuring method of the conventional semiconductor integrated circuit for measuring a delay time configured as described above will be described with reference to FIGS. 2 and 3. FIG.

In FIG. 3, first, the test mode 27 of FIG. 2 is set to “1” as shown at 28, and the output of the critical path 22 of FIG.
Set to output to the outside.

Next, as shown at 29, an initial value is set in the flip-flop 21 of FIG. 2 at the first rising edge of the clock input. Then, the second value is set in the flip-flop 21 at the second rising edge of the clock input. At this time, the initial value and the second value are set so that the delay of the critical path is maximized. Immediately after the setting of the second value, that is, the time Td from the second rising edge of the clock input to the time when the expected value is output from the output buffer is measured as the delay time, and the quality of the semiconductor integrated circuit is determined.

[0010]

The conventional method of measuring delay time measures the delay time of a critical path inside a semiconductor integrated circuit. However, in the above conventional example, it is necessary to extract a critical path,
Recently, the inside of a circuit is often not disclosed to a semiconductor maker. In this case, however, there is a problem that it is extremely difficult to create a test pattern that maximizes a critical path delay.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems, and it is possible to measure a delay time inside a semiconductor integrated circuit using a simple test pattern without adding a test circuit. The purpose is to provide a time measurement method.

[0012]

To achieve this object, a delay time measuring method according to the present invention sets both latches constituting a flip-flop on a scan chain to a slave mode in a test mode. Then, the delay time from the input to the output of the scan chain is measured.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS According to the above-described measuring method, it is possible to measure a delay time from an input to an output of a scan chain in which about 500 flip-flops are normally connected in series in a test mode setting.

Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a semiconductor integrated circuit for explaining a delay time measuring method according to a first embodiment of the present invention.

In FIG. 1, 1 is an input buffer, 2 and 3 are latches of positive polarity, 4 is a selector for selecting an inverted signal of a clock input in a test mode, 5 is an inverter for inverting a clock input, and 6 is a test mode. Signal input terminal, 7 is a clock signal input terminal, 8 is a flip-flop composed of latches 2 and 3 and selector 4, 9
And 10 are flip-flops having the same configuration as 8 and 11 is an output buffer.

FIG. 4 is a timing chart showing the operation of FIG. The signal 40 is a signal corresponding to the test mode 6 of FIG. 1, and similarly, the signal 41 is the signal of the input buffer 1 of FIG.
, The signal 42 indicates the clock input 7 of FIG. 1, and the signal 43 indicates the output signal of the output buffer 11 of FIG.

The operation of the delay time measuring method of the present embodiment configured as described above will be described below.

First, the flip-flop shown in FIG. 1 will be described. Normally, a flip-flop is composed of master and slave latches, and outputs a D input from a Q output at, for example, the rising edge of a clock.
In the flip-flop according to the present embodiment, the clock signal of the same polarity is input to both of the two latches constituting the flip-flop by setting the test mode signal to “1”, so that both the latches are in the slave mode. Become. As a result, the D input of the flip-flop is output from the Q output after the gate delay in the flip-flop, regardless of the timing of the edge of the clock signal.

Next, when the scan chain is constituted by the flip-flops, all the latches constituting the flip-flops 8, 9 and 10 on the scan chain are supplied from the external input of the input buffer 1 in the test mode setting. The total value of the delay times is output from the output buffer 11.

The operation of FIG. 1 will be specifically described with reference to the timing chart of FIG. First, the test mode signal 40
Is set to '1' and the clock input signal 42 is set to '1'.
Set to 0 '. At this point, all the latches constituting the flip-flops on the scan chains indicated by 8, 9 and 10 in FIG. 1 are in the slave mode. Next, the scan input 41 is changed from “0” to “1”. This signal is output as the output 43 of the output buffer after passing through the slave mode latches in all flip-flops on the scan chain. Input buffer input signal 41
And the output signal 43 of the output buffer is measured as the sum of the delay times of the latches in all the flip-flops on the scan chain.

As described above, by measuring the total delay time of all the latches constituting the flip-flops 8, 9, and 10 on the scan chain, a small test circuit and a simple test pattern can be obtained. This makes it possible to evaluate the delay time inside the semiconductor integrated circuit.

Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 5 is a circuit diagram of a semiconductor integrated circuit for explaining a delay time measuring method according to a second embodiment of the present invention.

In FIG. 5, 50 is an input buffer, 51 and 52 are positive latches, 53 is a clock signal input terminal, 54 is an inverted clock signal input terminal, and 55 is a clock signal input and inverted clock constituted by a latch. Flip-flops with both signal inputs, 56 and 57 are 55
And 58, an output buffer. FIG. 6 is a timing chart showing the operation of FIG. Signal 60 and signal 61 are signals corresponding to clock input 53 and inverted clock input 54 of FIG. 5, respectively. Similarly, signal 63 is the input of input buffer 50 of FIG.
Signal 63 indicates the output signal of output buffer 58 of FIG.

The operation of the delay time measuring method of the present embodiment configured as described above will be described below.

First, the flip-flop shown in FIG. 5 will be described.

Normally, the inverted signal of the clock input 53 is input to the inverted clock signal input 54 of the flip-flop. By making the inverted signal the same in polarity, a clock of the same polarity is supplied to both of the two latches constituting the flip-flop. Since the signal is input, both latches are in the slave mode. As a result, the D input of the flip-flop is output from the Q output after the gate delay in the flip-flop, regardless of the timing of the edge of the clock signal.

Next, when the scan chain is constituted by the flip-flops, the delay time of the latches constituting the flip-flops 55 to 58 on the scan chain is summed from the external input of the input buffer 50 in the test mode setting. The output delay time is output from the output buffer 58.

Referring to the timing chart of FIG.
The specific operation of the circuit will be described. First, the clock input 60 and the inverted clock input 61 are set to “1”.
At this point, all the flip-flops on the scan chain indicated by 55, 56 and 57 in FIG. 5 are in the slave mode. Next, the input 62 is changed from “0” to “1”. This signal is output as the output 63 of the output buffer after passing through the slave mode latches in all flip-flops on the scan chain. The difference between the input 62 of the input buffer and the output 63 of the output buffer is measured as the sum of the delay times of the latches in all flip-flops on the scan chain.

As described above, by measuring the total delay time of all the latches constituting the flip-flops 55 to 57 on the scan chain, a simple test pattern can be used without adding a test circuit. Thus, the delay time inside the semiconductor integrated circuit can be evaluated.

[0032]

According to the above embodiment, by measuring the sum of the delay times of all the flip-flops on the scan chain, a simple test can be performed without adding a small-scale test circuit or a test circuit. The delay time inside the semiconductor integrated circuit can be measured using the pattern. In addition, when the performance of the transistor is poor and the performance is low, the delay time measurement using the conventional critical path has a gate stage number of about ten and several stages at most, so the effect is also ten and several nsec. Since the effect of this affects all flip-flops on the scan chain, it takes several hundred nsec or more, so that a low-cost and low-accuracy measuring device can measure and inspect the delay time.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit in a first embodiment of a delay measuring method of the present invention.

FIG. 2 is a diagram showing a circuit in an embodiment of a conventional delay measuring method.

FIG. 3 is a timing chart of the circuit of FIG. 2;

FIG. 4 is a timing chart of the circuit of FIG. 1;

FIG. 5 is a diagram showing a circuit according to a second embodiment of the delay measuring method of the present invention.

FIG. 6 is a timing chart of the circuit of FIG. 5;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Input buffer 2, 3 Positive latch 4 Selector 5 Inverter for clock inversion 6 Input terminal of test mode signal 7 Input terminal of clock signal 8, 9, 10 Flip-flop composed of latch and selector 11 Output buffer 20 Input Buffer 21, 23 Flip-flop 22 Critical path 24 Selector 25 Output buffer 26 Input signal to clock input terminal 27 Input signal to test input terminal of selector 28 Input signal to test mode input terminal 29 Input signal to flip-flop D input terminal Input signal 30 Input signal to clock input terminal of flip-flop 31 Output signal from output buffer 25 40 Input signal corresponding to test mode 6 41 Input signal to input buffer 1 42 Input signal to clock input 7 43 Output buffer Output signal from 11 50 Input buffer 51, 52 Latch of positive polarity 53 Input terminal of clock signal 54 Input terminal of inverted clock signal 55, 56, 57 Flip-flop composed of latch 58 Output buffer 60 Input signal to clock input 53 61 Input signal to inverted clock input 54 62 Input signal to input buffer 50 63 Output signal from output buffer 58

Claims (2)

[Claims] 1. A delay time measuring method which includes a test mode in which both of two latches constituting a flip-flop are in a slave mode, and measures a delay time from input to output of a scan chain in the test mode. 2. A flip-flop having a clock input and an inverted clock input, in which signals having the same polarity are input to the clock input and the inverted clock input, and both of the two latches constituting the flip-flop are set to a slave mode. A delay time measurement method that measures the delay time from input to output of a scan chain.