CN112557883B - Pulse signal parameter testing system - Google Patents
Pulse signal parameter testing system Download PDFInfo
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- CN112557883B CN112557883B CN202110213902.3A CN202110213902A CN112557883B CN 112557883 B CN112557883 B CN 112557883B CN 202110213902 A CN202110213902 A CN 202110213902A CN 112557883 B CN112557883 B CN 112557883B
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- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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- G01R31/2882—Testing timing characteristics
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Abstract
The embodiment of the invention provides a pulse signal parameter testing system, which comprises a delay module, a switch module, a parasitic capacitance improving module and a time measuring unit, wherein the delay module is used for receiving a pulse signal; the signal input end of the pulse signal parameter testing system is respectively connected with the first input end of the parasitic capacitance improving module and the input end of the delay module; the output end of the delay module is respectively connected with the input end of the element to be tested and the first input end of the switch module, the output end of the element to be tested is connected with the second input end of the switch module, and the output end of the switch module is connected with the second input end of the parasitic capacitance improving module; the switch module is used for gating the first input end of the switch module and the output end of the switch module in a time-sharing mode, or gating the second input end of the switch module and the output end of the switch module. The embodiment of the invention provides a pulse signal parameter testing system, which improves the testing precision of a testing machine on the transmission delay time and the pulse signal edge time of a to-be-tested element.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a pulse signal parameter testing system.
Background
The mass production test of the chip is to guarantee that the manufactured chip can meet the use requirement of the market, and ensure the quality of the chip, thereby providing the product which meets the standard and has qualified quality for customers, and the mass production test of the chip is the process of picking out the defects and separating good products and defective products.
The chip test includes a time item test, the time item test includes a test of input and output transmission delay of the chip to be tested and a test of edge time of an output signal of the chip to be tested, and the time item test of the transmission delay of the chip to be tested being about 20ns and the edge time of the output pulse signal being less than 10ns is difficult in the mass production test. The main problems include:
1. the time testing precision of the time measuring unit in the traditional mass production testing machine is +/-10 ns + 0.1% of reading, and obviously, the precision of the time measuring unit for directly testing the time item of the chip cannot be guaranteed.
2. The average value of the test results of the same batch of chips on different test machines has errors.
3. The chip signal to be tested is connected into the testing machine through the connecting cable, parasitic parameters, particularly parasitic capacitance, exist in the connecting cable and the testing machine, and the characteristics of the original signal are changed.
Disclosure of Invention
The embodiment of the invention provides a pulse signal parameter testing system, which improves the testing precision of a testing machine on the transmission delay time and the pulse signal edge time of a to-be-tested element.
The embodiment of the invention provides a pulse signal parameter testing system, which comprises a delay module, a switch module, a parasitic capacitance improving module and a time measuring unit, wherein the delay module is used for receiving a pulse signal;
the signal input end of the pulse signal parameter testing system is respectively connected with the first input end of the parasitic capacitance improving module and the input end of the delay module;
the output end of the delay module is respectively connected with the input end of an element to be tested and the first input end of the switch module, the output end of the element to be tested is connected with the second input end of the switch module, and the output end of the switch module is connected with the second input end of the parasitic capacitance improving module;
a first output end of the parasitic capacitance improving module is connected with a first input end of the time measuring unit, and a second output end of the parasitic capacitance improving module is connected with a second input end of the time measuring unit;
the delay module is used for delaying the pulse signal input by the input end of the delay module; the switch module is used for gating a first input end of the switch module and an output end of the switch module in a time-sharing mode, or gating a second input end of the switch module and an output end of the switch module, and the parasitic capacitance improvement module is used for improving parasitic capacitance in the pulse signal parameter test system; the time measuring unit is used for measuring the time difference of the pulse signals input by the first input end and the second input end of the time measuring unit.
Optionally, the delay module includes a first resistor and a first capacitor;
the first end of the first resistor is a signal input end of the pulse signal parameter testing system, and the second end of the first resistor is connected with the first end of the first capacitor;
the first end of the first capacitor is connected with the input end of the element to be tested, and the second end of the first capacitor is grounded.
Optionally, the switch module comprises a single-pole double-throw switch;
the first end of the single-pole double-throw switch is connected with the input end of the element to be tested, the second end of the single-pole double-throw switch is connected with the output end of the element to be tested, and the control end of the single-pole double-throw switch is connected with the second input end of the parasitic capacitance improving module.
Optionally, the pulse signal parameter testing system provided in the embodiment of the present invention further includes a first inverter, a second inverter, and a third inverter;
the input end of the first phase inverter is the signal input end of the pulse signal parameter testing system, and the output end of the first phase inverter is respectively connected with the input end of the delay module and the input end of the second phase inverter;
the output end of the second inverter is connected with the first input end of the parasitic capacitance improving module;
the input end of the third phase inverter is connected with the output end of the delay module, and the output end of the third phase inverter is respectively connected with the input end of the element to be tested and the first input end of the switch module.
Optionally, the pulse signal parameter testing system provided in the embodiment of the present invention further includes a first comparing module and a second comparing module;
a first input end of the first comparison module is connected with a first power supply, a second input end of the first comparison module is connected with a signal input end of the pulse signal parameter testing system, and an output end of the first comparison module is connected with a first input end of the parasitic capacitance improvement module;
the first input end of the second comparison module is connected with a second power supply, the second input end of the second comparison module is connected with the output end of the switch module, and the output end of the first comparison module is connected with the second input end of the parasitic capacitance improvement module.
Optionally, the pulse signal parameter testing system provided in the embodiment of the present invention further includes a first driving module and a second driving module;
the input end of the first driving module is connected with the output end of the first comparing module, and the output end of the first driving module is connected with the first input end of the parasitic capacitance improving module;
the input end of the second driving module is connected with the output end of the second comparing module, and the output end of the second driving module is connected with the second input end of the parasitic capacitance improving module.
Optionally, the first comparing module is the same as the second comparing module, and the first driving module is the same as the second driving module.
Optionally, the parasitic capacitance improving module includes a first differentiating circuit and a second differentiating circuit;
the input end of the first differential circuit is connected with the output end of the first driving module, and the output end of the first differential circuit is connected with the first input end of the time measuring unit;
the input end of the second differential circuit is connected with the output end of the second driving module, and the output end of the second differential circuit is connected with the second input end of the time measuring unit.
Optionally, the first differentiating circuit includes a second resistor and a second capacitor, and the second differentiating circuit includes a third resistor and a third capacitor;
the first end of the second capacitor is connected with the output end of the first driving module, and the second end of the second capacitor is connected with the first end of the second resistor;
the first end of the second resistor is connected with the first input end of the time measuring unit, and the second end of the second resistor is grounded;
the first end of the third capacitor is connected with the output end of the second driving module, and the second end of the third capacitor is connected with the first end of the third resistor;
and the first end of the third resistor is connected with the second input end of the time measuring unit, and the second end of the third resistor is grounded.
Optionally, the second resistor is the same as the third resistor, and the second capacitor is the same as the third capacitor.
The delay module in the pulse signal parameter testing system provided by the embodiment of the invention delays the output of the pulse signal, ensures that the output end of the delay module is connected with the second input end of the time measuring unit by controlling the conduction of the first input end and the output end of the switch module, ensures that the output end of the element to be tested is connected with the second input end of the parasitic capacitance improving module by controlling the conduction of the second input end of the switch module and the output end of the switch module, and calculates the time difference of the pulse signal input by the second input end and the first input end of the time measuring unit by the time measuring unit, the delay time of the delay module is subtracted to calculate the transmission delay time of the to-be-tested element to the input pulse signal, the conduction between the second input end of the control switch module and the output end of the switch module is controlled to ensure that the output end of the to-be-tested element is connected with the second input end of the time measuring unit, in the rising process of the pulse signal, the time difference of the pulse signal input by the second input end and the first input end of the time measuring unit is calculated by the time measuring unit, and then the delay time of the delay module is subtracted and the transmission delay time of the to-be-tested element is subtracted to calculate the edge time of the pulse signal output by the output end of the to-be-tested element.
Drawings
Fig. 1 is a schematic diagram of a relationship structure between an input pulse signal and an output pulse signal provided by a conventional mass production tester;
FIG. 2 is a schematic diagram of a conventional pulse signal parameter testing system;
FIG. 3 is a schematic diagram of another conventional pulse signal parameter testing system;
fig. 4 is a schematic structural diagram of a pulse signal parameter testing system according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a relationship structure between an input pulse signal and an output pulse signal according to an embodiment of the present invention;
FIG. 6 is a schematic structural diagram of another pulse signal parameter testing system according to an embodiment of the present invention;
FIG. 7 is a schematic structural diagram of another pulse signal parameter testing system according to an embodiment of the present invention;
FIG. 8 is a schematic structural diagram of another pulse signal parameter testing system according to an embodiment of the present invention;
fig. 9 is a schematic diagram of a relationship structure between an input pulse signal and an output pulse signal according to another embodiment of the present invention.
Detailed Description
The embodiments of the present invention will be described in further detail with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of and not restrictive on the broad invention. It should be further noted that, for convenience of description, only some structures, not all structures, relating to the embodiments of the present invention are shown in the drawings.
The existing test method of the mass production test machine for the chip to be tested is to connect the input end and the output end of the chip to be tested with the output end and the input end of the mass production test machine respectively, the output end of the mass production test machine inputs a pulse signal to the input end of the chip to be tested, the pulse signal output by the output end of the chip to be tested is input to the input end of the mass production test machine, and a time measuring unit in the mass production test machine calculates the transmission delay time of the chip to be tested and the edge time of the pulse signal output by the. Fig. 1 is a schematic diagram of a relationship structure between an input pulse signal and an output pulse signal provided by a conventional mass production testing machine, referring to fig. 1, IN1 represents a pulse signal input to an input terminal of a chip to be tested, OUT1 represents a pulse signal output from an output terminal of the chip to be tested, 50% to 10% of the input pulse signal is denoted as a transmission delay time of the chip to be tested to the pulse signal, denoted as ton1, and 10% to 90% of the pulse signal output from the chip to be tested is denoted as a rising edge time of the pulse signal, denoted as tr1, where the conventional mass production testing machine directly measures the magnitudes of ton1 and tr1, and a typical mass production testing machine has a mass production precision: a ± 10ns + 0.1% reading means that the mass production tester has a higher resolution, but there is a fixed deviation of plus or minus 10 ns. The size of ton1 to be measured is generally about 20ns, and the size of tr1 is generally about 10ns, so that the direct measurement accuracy is not high. The same method is used for measuring the edge time tf1 and the transmission delay time toff1 of the falling edge of the pulse signal.
In order to reduce the influence of capacitance in the time measurement unit and parasitic capacitance in the cable in the prior art, the following methods are commonly used:
1. the test cable is shortened as much as possible, the parasitic capacitance of the test cable is relieved, waveform distortion is endured, and the test requirement is relaxed.
The method can only improve the influence of parasitic capacitance in the transmission cable on the tested signal, and the capacitance existing in the time measuring unit still influences the test result.
2. Fig. 2 is a schematic structural diagram of a pulse signal parameter testing system in the prior art, referring to fig. 2, in order to improve the influence of parasitic parameters on signals of more than 10ns in the prior art, a BUF634 buffer is added at the output end of a chip to be tested, the influence of parasitic parameters on more than 10ns can only be improved by adding the BUF634 buffer, and no buffer with the magnitude of 10ns exists at present, so that the problem of low precision on the time test result of less than 10ns also exists.
3. Fig. 3 is a schematic structural diagram of another pulse signal parameter testing system in the prior art, and referring to fig. 3, in the prior art, an analog signal is converted into a digital signal by a comparator for testing, so that the influence of parasitic capacitance in a long cable can be effectively improved. However, for signals of the order of 10ns, the nanosecond delay comparator has no capability of driving 50 Ω impedance, so that the test result cannot be accurate for the time test of 10 ns.
In view of the above problems, the pulse signal parameter testing system provided by the embodiment of the invention not only solves the problem of inaccurate test results of the testing machine, but also solves the influence of parasitic capacitance in the traditional time measuring unit and the transmission cable on the test results.
Fig. 4 is a schematic structural diagram of a pulse signal parameter testing system according to an embodiment of the present invention, and referring to fig. 4, the pulse signal parameter testing system according to the embodiment of the present invention includes a delay module 110, a switch module 120, a parasitic capacitance improving module 150, and a time measuring unit 130; the signal input end of the pulse signal parameter testing system is respectively connected with the first input end of the parasitic capacitance improving module 150 and the input end of the delay module 110; the output end of the delay module 110 is connected to the input end of the device under test 140 and the first input end of the switch module 120, respectively, the output end of the device under test 140 is connected to the second input end of the switch module 120, and the output end of the switch module 120 is connected to the second input end of the parasitic capacitance improving module 150; a first output end of the parasitic capacitance improving module 150 is connected with a first input end of the time measuring unit 130, and a second output end of the parasitic capacitance improving module 150 is connected with a second input end of the time measuring unit 130; the delay module 110 is used for delaying the pulse signal input by the input end of the delay module 110; the switch module 120 is configured to gate a first input terminal of the switch module 120 and an output terminal of the switch module 120 in a time-sharing manner, or gate a second input terminal of the switch module 120 and an output terminal of the switch module 120, and the parasitic capacitance improving module 150 is configured to improve a parasitic capacitance in the pulse signal parameter testing system; the time measuring unit 130 is used for measuring a time difference between the pulse signals input from the first input terminal and the second input terminal of the time measuring unit 130.
Specifically, the pulse signal input by the first input terminal of the parasitic capacitance improvement module 150 is processed by the parasitic capacitance improvement module 150 and then output from the first output terminal of the parasitic capacitance improvement module 150, and the pulse signal input by the second input terminal of the parasitic capacitance improvement module 150 is processed by the parasitic capacitance improvement module 150 and then output from the second output terminal of the parasitic capacitance improvement module 150, because the cable and time measurement unit 130 in the pulse signal parameter test system has a parasitic capacitance and affects the measurement result, the parasitic capacitance improvement module 150 is added in the embodiment of the present invention to improve the parasitic capacitance of the cable and time measurement unit 130. The time measuring unit 130 has high time measuring precision for more than 20ns, the delay time range of the delay module 110 is 20 ns-100 ns, and the delay module 110 can improve the measuring precision of the time measuring unit 130. For example, fig. 5 is a schematic diagram of a relationship structure between an input pulse signal and an output pulse signal according to an embodiment of the present invention, referring to fig. 4 and fig. 5, a testing machine outputs a pulse signal to a signal input terminal of a pulse signal parameter testing system, because of the existence of a delay module 110, a first input terminal of a parasitic capacitance improvement module 150 inputs the pulse signal first, the pulse signal is processed by the parasitic capacitance improvement module 150 and then input to a first input terminal of a time measurement unit 130 through a first output terminal of the parasitic capacitance improvement module 150, the first input terminal of the time measurement unit 130 inputs the pulse signal first, the pulse signal is denoted as IN0, when 50% of a rising edge of the pulse signal is input to the first input terminal of the time measurement unit 130, the time measurement unit 130 starts timing, when the delay time of the delay module 110 needs to be calculated, the first input terminal and the output terminal of the switch module 120 are connected, then the pulse signal output from the output terminal of the delay module 110 is directly input to the second input terminal of the parasitic capacitance improvement module 150, the pulse signal is input to the second input terminal of the time measurement unit 130 through the second output terminal of the parasitic capacitance improvement module 150 after being processed by the parasitic capacitance improvement module 150, the pulse signal is marked as IN, when the second input terminal of the time measurement unit 130 receives 50% of the rising edge of the pulse signal, the time measurement unit 130 calculates the time difference between the pulse signals input from the first input terminal and the second input terminal of the time measurement unit 130, the time difference is marked as t0, when the transmission delay time of the to-be-measured element 140 to the input pulse signal needs to be calculated, the second input terminal and the output terminal of the switch module 120 are connected, then the pulse signal output from the output terminal of the to-be-measured element 140 is directly input to the second input terminal of the parasitic capacitance improvement module, the pulse signal processed by the parasitic capacitance improving module 150 is input to the second input terminal of the time measuring unit 130 through the second output terminal of the parasitic capacitance improving module 150, the pulse signal is recorded as OUT, when the second input terminal of the time measuring unit 130 receives 10% of the rising edge of the pulse signal again, the time measuring unit 130 calculates the time difference between the pulse signal input by the first input terminal and the pulse signal input by the second input terminal of the time measuring unit 130 again, and the time difference is recorded as t1, so that the transmission delay time ton = t1-t0 of the device under test 140 is known. When the edge time of the pulse signal at the output terminal of the device under test 140 needs to be calculated, the second input terminal and the output terminal of the switch module 120 are still connected, when the second input terminal of the time measuring unit 130 receives 90% of the rising edge of the pulse signal OUT again, the time measuring unit 130 calculates the time difference between the pulse signals input by the first input terminal and the second input terminal of the time measuring unit 130 again, and the time difference is t2, so that the edge time tr = t2-t1 of the pulse signal output by the output terminal of the device under test 140 can be known. Because the delay time range of the delay module 110 is over 20ns, t0, t1, and t2 are all greater than 20ns, the transmission delay time of the device to be measured 140 is generally less than 20ns, the edge time of the pulse signal output by the device to be measured is generally about 10ns, and when the conventional time measurement unit measures time within 10ns, the measurement result is often inaccurate. The delay module 110 provided by the embodiment of the present invention has a function of delaying a pulse signal, and for example, the delay module 110 may be a delay chip or a delay circuit composed of a resistor and a capacitor.
The delay module in the pulse signal parameter testing system provided by the embodiment of the invention delays the output of the pulse signal, ensures that the output end of the delay module is connected with the second input end of the time measuring unit by controlling the conduction of the first input end and the output end of the switch module, ensures that the output end of the element to be tested is connected with the second input end of the parasitic capacitance improving module by controlling the conduction of the second input end of the switch module and the output end of the switch module, and calculates the time difference of the pulse signal input by the second input end and the first input end of the time measuring unit by the time measuring unit, the delay time of the delay module is subtracted to calculate the transmission delay time of the to-be-tested element to the input pulse signal, the conduction between the second input end of the control switch module and the output end of the switch module is controlled to ensure that the output end of the to-be-tested element is connected with the second input end of the time measuring unit, in the rising process of the pulse signal, the time difference of the pulse signal input by the second input end and the first input end of the time measuring unit is calculated by the time measuring unit, and then the delay time of the delay module is subtracted and the transmission delay time of the to-be-tested element is subtracted to calculate the edge time of the pulse signal output by the output end of the to-be-tested element.
Optionally, fig. 6 is a schematic structural diagram of another pulse signal parameter testing system according to an embodiment of the present invention, and referring to fig. 6, the delay module 110 includes a first resistor R1 and a first capacitor C1; the first end of the first resistor R1 is a signal input end of the pulse signal parameter testing system, and the second end of the first resistor R1 is connected with the first end of the first capacitor C1; the first end of the first capacitor C1 is connected to the input terminal of the dut 140, and the second end of the first capacitor C1 is grounded.
Specifically, the first resistor R1 and the first capacitor C1 form the delay module 110, and since the first capacitor C1 has the functions of storing and discharging, the pulse signal input at the input terminal of the delay module 110 can be delayed. In the present embodiment, the delay time of the delay module 110 can be controlled by changing the sizes of the first resistor R1 and the first capacitor C1.
Optionally, with continued reference to fig. 6, the switch module 120 includes a single pole, double throw switch; the first end of the single-pole double-throw switch is connected with the input end of the element to be tested 140, the second end of the single-pole double-throw switch is connected with the output end of the element to be tested 140, and the control end of the single-pole double-throw switch is connected with the second input end of the parasitic capacitance improving module 150.
Specifically, when the first terminal of the single-pole double-throw switch and the control terminal of the single-pole double-throw switch are turned on, the time measuring unit 130 may calculate the delay time of the delay module 110 according to a time difference between pulse signals input by the first input terminal and the second input terminal of the time measuring unit 130. When the second terminal of the single-pole double-throw switch is connected to the control terminal of the single-pole double-throw switch, the time measurement unit 130 can calculate the transmission delay time of the device under test 140 and the edge time of the pulse signal output by the output terminal of the device under test according to the time difference input by the second input terminal and the first input terminal of the time measurement unit 130.
Optionally, fig. 7 is a schematic structural diagram of another pulse signal parameter testing system according to an embodiment of the present invention, and referring to fig. 7, the pulse signal parameter testing system according to the embodiment of the present invention further includes a first inverter N1, a second inverter N2, and a third inverter N3; the input end of the first inverter N1 is the signal input end of the pulse signal parameter testing system, and the output end of the first inverter N1 is respectively connected with the input end of the delay module 110 and the input end of the second inverter N2; the output end of the second inverter N2 is connected to the first input end of the parasitic capacitance improving module 150; the input end of the third inverter N3 is connected to the output end of the delay module 110, and the output end of the third inverter N3 is connected to the input end of the device under test 140 and the first input end of the switch module 120, respectively.
Specifically, the first inverter N1 inverts the pulse signal input from the signal input terminal of the pulse signal parameter testing system, and then the pulse signal is inverted again by the second inverter N2, and the third inverter N3 inverts the pulse signal output from the output terminal of the first inverter N1 to be the same as the pulse signal output from the output terminal of the second inverter N2. The pulse signal input by the signal input end of the pulse signal parameter testing system can increase the transmission rate of the pulse signal by continuously passing through the first inverter N1 and the second inverter N2, and similarly, the pulse signal input by the signal input end of the pulse signal parameter testing system can also increase the transmission rate of the pulse signal by passing through the first inverter N1 and the third inverter N3.
Optionally, fig. 8 is a schematic structural diagram of another pulse signal parameter testing system according to an embodiment of the present invention, and referring to fig. 8, the pulse signal parameter testing system according to the embodiment of the present invention further includes a first comparing module 131 and a second comparing module 132; a first input end of the first comparing module 131 is connected with the first power supply, a second input end of the first comparing module 131 is connected with a signal input end of the pulse signal parameter testing system, and an output end of the first comparing module 131 is connected with a first input end of the parasitic capacitance improving module 150; a first input terminal of the second comparing module 132 is connected to the second power supply, a second input terminal of the second comparing module 132 is connected to the output terminal of the switch module 120, and an output terminal of the first comparing module 131 is connected to a second input terminal of the parasitic capacitance improving module 150.
For example, fig. 9 is a schematic diagram of a relationship structure between an input pulse signal and an output pulse signal according to another embodiment of the present invention, referring to fig. 8 and fig. 9, a testing machine outputs a pulse signal to a signal input terminal of a pulse signal parameter testing system, controls a magnitude of a first power supply to be 50% of a rising edge of the pulse signal input by the signal input terminal of the pulse signal parameter testing system, when a pulse signal input by a second input terminal of a first comparing module 131 is greater than a magnitude of the first power supply input by the first input terminal of the first comparing module, an output terminal of the first comparing module 131 outputs a signal to a first input terminal of a parasitic capacitance improving module 150, the signal is processed by the parasitic capacitance improving module 150 and then output from a first output terminal of the parasitic capacitance improving module 150 to a first input terminal of a time measuring unit 130, the time measuring unit 130 detects that a signal is input by the first input terminal of the time measuring unit 130, the timing starts from zero, and the pulse signal inputted from the second input terminal of the first comparing module 131 is denoted as IN 2. Then, the magnitude of the second power supply is controlled to be 50% of the rising edge of the pulse signal input by the signal input terminal of the pulse signal parameter testing system, the first terminal of the single-pole double-throw switch is controlled to be connected with the control terminal, when the pulse signal input by the second input terminal of the second comparing module 132 is greater than the magnitude of the second power supply input by the first input terminal of the second comparing module 132, the pulse signal input by the second input terminal of the second comparing module 132 at this time is recorded as IN3, the output terminal of the second comparing module 132 outputs a signal to the second input terminal of the parasitic capacitance improving module 150, the signal is output from the second output terminal of the parasitic capacitance improving module 150 to the second input terminal of the time measuring unit 130 after being processed by the parasitic capacitance improving module 150, after the time measuring unit 130 detects that the signal is input by the second input terminal of the time measuring unit 130, the time measuring unit 130 calculates the time difference between the signal input by the second input terminal and the first input terminal of, denoted t 4. Then the second end of the single-pole double-throw switch is controlled to be connected with the control end, the size of the second power supply is controlled to be 10% of the rising edge of the pulse signal input by the signal input end of the pulse signal parameter testing system, when the pulse signal inputted from the second input terminal of the second comparing module 132 is greater than the second power inputted from the first input terminal, at this time, the pulse signal input by the second input terminal of the second comparing module 132 is recorded as OUT3, the output terminal of the second comparing module 132 inputs a signal to the second input terminal of the parasitic capacitance improving module 150, and the signal is processed by the parasitic capacitance improving module 150 and then output from the second output terminal of the parasitic capacitance improving module 150 to the second input terminal of the time measuring unit 130, at this time, the time measuring unit 130 calculates the time difference between the signal input from the first input terminal of the time measuring unit 130 and the signal input from the second input terminal at this time, which is denoted as t 5. Then, the magnitude of the second power supply is controlled to be 90% of the rising edge of the pulse signal input by the signal input end of the pulse signal parameter testing system again, and the second end of the single-pole double-throw switch is controlled to be connected to the control end at the same time, similarly, when the pulse signal input by the second input end of the second comparing module 132 is greater than the magnitude of the second power supply input by the first input end of the second comparing module 132, the output end of the second comparing module 132 inputs a signal to the second input end of the parasitic capacitance improving module 150, and the signal is output from the second output end of the parasitic capacitance improving module 150 to the second input end of the time measuring unit 130 after being processed by the parasitic capacitance improving module 150, at this time, the time measuring unit 130 calculates the time difference between the signals input by the first input end and the second input end at this time again, and records the time difference as t 6. Then the delay time of the delay module 110 is t4, the transmission delay time of the chip 140 to be tested to the pulse signal is ton2= t5-t4, and the edge time when the pulse signal rises is tr2= t6-t 5. Similarly, the delay time and the edge time of the dut 140 for the falling edge of the pulse signal are calculated by the same method, and are not described herein again.
Optionally, with continuing reference to fig. 8, the pulse signal parameter testing system provided in the embodiment of the present invention further includes a first driving module 134 and a second driving module 135; the input end of the first driving module 134 is connected to the output end of the first comparing module 131, and the output end of the first driving module 134 is connected to the first input end of the parasitic capacitance improving module 150; an input terminal of the second driving module 135 is connected to an output terminal of the second comparing module 132, and an output terminal of the second driving module 135 is connected to a second input terminal of the parasitic capacitance improving module 150.
Specifically, the first driving module 134 and the second driving module 135 function to increase the driving capability of the signal.
Optionally, the first comparing module 131 and the second comparing module 132 are the same, and the first driving module 134 and the second driving module 135 are the same.
Specifically, the first comparing module 131 is a first comparator, the second comparing module 132 is a second comparator, the first driving module 134 is a first driver, and the second driving module 135 is a second driver. Because the pulse signal input by the second input end of the first comparator is the same as the pulse signal input by the second input end of the second comparator, the first comparator and the second comparator are the same, so that the consistency of the first comparator and the second comparator on the transmission delay of the pulse signal can be ensured.
Optionally, with continued reference to fig. 8, the parasitic capacitance improvement module 150 includes a first differentiating circuit 136 and a second differentiating circuit 137; an input end of the first differentiating circuit 136 is connected with an output end of the first driving module 134, and an output end of the first differentiating circuit 136 is connected with a first input end of the time measuring unit 130; an input of the second differentiating circuit 137 is connected to an output of the second driving module 135, and an output of the second differentiating circuit 137 is connected to a second input of the time measuring unit 130.
Specifically, the first differentiating circuit 136 functions to emphasize the change in the input signal at the input terminal of the first differentiating circuit 136 and suppress the constant in the input signal, thereby improving the influence of the parasitic capacitance in the time measuring unit 130 on the measurement result, and the second differentiating circuit 137 also functions.
Optionally, with continued reference to fig. 8, the first differentiating circuit 136 includes a second resistor R2 and a second capacitor C2, and the second differentiating circuit 137 includes a third resistor R3 and a third capacitor C3; a first end of the second capacitor C2 is connected to the output end of the first driving module 134, and a second end of the second capacitor C2 is connected to a first end of the second resistor R2; a first end of the second resistor R2 is connected to the first input end of the time measuring unit 130, and a second end of the second resistor R2 is grounded; a first end of the third capacitor C3 is connected to the output end of the second driving module 135, and a second end of the third capacitor C3 is connected to a first end of the third resistor R3; the first terminal of the third resistor R3 is connected to the second input terminal of the time measuring unit 130, and the second terminal of the third resistor R3 is grounded.
Specifically, the parasitic capacitance in the time measuring unit 130 and the cable can be improved by adjusting the sizes of the second capacitor C2 and the second resistor R2 and the third capacitor C3 and the third resistor R3.
Optionally, the second resistor R2 is the same as the third resistor R3, and the second capacitor C2 is the same as the third capacitor C3.
Specifically, the second resistor R2 is the same as the third resistor R3, the second capacitor C2 and the third capacitor C3 have the same function and the same function principle as the first comparator and the second comparator, and a worker can use a multimeter to measure the sizes of the second resistor R2 and the third resistor R3 to ensure that the second resistor R2 is the same as the third resistor R3, and can also use a multimeter to measure the sizes of the second capacitor C2 and the third capacitor C3 to ensure that the second capacitor C2 is the same as the third capacitor C3.
The pulse signal parameter testing system provided by the embodiment of the invention prolongs the time measured by the time measuring unit to more than 20ns through the delay module, thereby improving the measuring precision of the time measuring unit and further improving the measuring precision of the testing machine, and the problem of different testing results can not occur even if different testing machines are used for testing the transmission delay time of the element to be tested and the edge time of the pulse signal. The first differential circuit and the second differential circuit in the parasitic capacitance improvement module solve the influence of the parasitic capacitance in the cable and time measurement unit on the test result. The pulse signal parameter testing system is added with the first inverter, the second inverter, the third inverter, the first capacitor, the second capacitor, the third capacitor, the first resistor, the second resistor, the third resistor and the single-pole double-throw switch, and the components are low in cost and are easy to realize corresponding functions after being connected.
It should be noted that the foregoing is only a preferred embodiment of the present invention and the technical principles applied. Those skilled in the art will appreciate that the embodiments of the present invention are not limited to the specific embodiments described herein, and that various obvious changes, adaptations, and substitutions are possible, without departing from the scope of the embodiments of the present invention. Therefore, although the embodiments of the present invention have been described in more detail through the above embodiments, the embodiments of the present invention are not limited to the above embodiments, and many other equivalent embodiments may be included without departing from the concept of the embodiments of the present invention, and the scope of the embodiments of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A pulse signal parameter test system is characterized by comprising a delay module, a switch module, a parasitic capacitance improvement module and a time measurement unit;
the signal input end of the pulse signal parameter testing system is respectively connected with the first input end of the parasitic capacitance improving module and the input end of the delay module;
the output end of the delay module is respectively connected with the input end of an element to be tested and the first input end of the switch module, the output end of the element to be tested is connected with the second input end of the switch module, and the output end of the switch module is connected with the second input end of the parasitic capacitance improving module;
a first output end of the parasitic capacitance improving module is connected with a first input end of the time measuring unit, and a second output end of the parasitic capacitance improving module is connected with a second input end of the time measuring unit;
the delay module is used for delaying the pulse signal input by the input end of the delay module; the switch module is used for gating a first input end of the switch module and an output end of the switch module in a time-sharing mode, or gating a second input end of the switch module and an output end of the switch module, and the parasitic capacitance improvement module is used for improving parasitic capacitance in the pulse signal parameter test system; the time measuring unit is used for measuring the time difference of the pulse signals input by the first input end and the second input end of the time measuring unit.
2. The pulsed signal parametric test system of claim 1, wherein the delay module comprises a first resistor and a first capacitor;
the first end of the first resistor is a signal input end of the pulse signal parameter testing system, and the second end of the first resistor is connected with the first end of the first capacitor;
the first end of the first capacitor is connected with the input end of the element to be tested, and the second end of the first capacitor is grounded.
3. The pulsed signal parametric test system of claim 1, wherein the switch module comprises a single pole double throw switch;
the first end of the single-pole double-throw switch is connected with the input end of the element to be tested, the second end of the single-pole double-throw switch is connected with the output end of the element to be tested, and the control end of the single-pole double-throw switch is connected with the second input end of the parasitic capacitance improving module.
4. The pulse signal parametric test system of claim 1, further comprising a first inverter, a second inverter, and a third inverter;
the input end of the first phase inverter is the signal input end of the pulse signal parameter testing system, and the output end of the first phase inverter is respectively connected with the input end of the delay module and the input end of the second phase inverter;
the output end of the second inverter is connected with the first input end of the parasitic capacitance improving module;
the input end of the third phase inverter is connected with the output end of the delay module, and the output end of the third phase inverter is respectively connected with the input end of the element to be tested and the first input end of the switch module.
5. The pulse signal parameter testing system of claim 1, further comprising a first comparison module and a second comparison module;
a first input end of the first comparison module is connected with a first power supply, a second input end of the first comparison module is connected with a signal input end of the pulse signal parameter testing system, and an output end of the first comparison module is connected with a first input end of the parasitic capacitance improvement module;
the first input end of the second comparison module is connected with a second power supply, the second input end of the second comparison module is connected with the output end of the switch module, and the output end of the first comparison module is connected with the second input end of the parasitic capacitance improvement module.
6. The pulse signal parameter testing system of claim 5, further comprising a first driving module and a second driving module;
the input end of the first driving module is connected with the output end of the first comparing module, and the output end of the first driving module is connected with the first input end of the parasitic capacitance improving module;
the input end of the second driving module is connected with the output end of the second comparing module, and the output end of the second driving module is connected with the second input end of the parasitic capacitance improving module.
7. The pulse signal parameter testing system of claim 6, wherein the first comparing module and the second comparing module are the same, and the first driving module and the second driving module are the same.
8. The pulse signal parameter testing system according to claim 6, wherein the parasitic capacitance improvement module includes a first differential circuit and a second differential circuit;
the input end of the first differential circuit is connected with the output end of the first driving module, and the output end of the first differential circuit is connected with the first input end of the time measuring unit;
the input end of the second differential circuit is connected with the output end of the second driving module, and the output end of the second differential circuit is connected with the second input end of the time measuring unit.
9. The pulse signal parameter testing system of claim 8, wherein the first differentiating circuit comprises a second resistor and a second capacitor, and the second differentiating circuit comprises a third resistor and a third capacitor;
the first end of the second capacitor is connected with the output end of the first driving module, and the second end of the second capacitor is connected with the first end of the second resistor;
the first end of the second resistor is connected with the first input end of the time measuring unit, and the second end of the second resistor is grounded;
the first end of the third capacitor is connected with the output end of the second driving module, and the second end of the third capacitor is connected with the first end of the third resistor;
and the first end of the third resistor is connected with the second input end of the time measuring unit, and the second end of the third resistor is grounded.
10. The pulsed signal parametric test system of claim 9, wherein the second resistance is the same as the third resistance and the second capacitance is the same as the third capacitance.
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