JP2019060744A - Delay time measuring device, semiconductor device, and delay time measuring method - Google Patents

Abstract

To provide a delay time measuring device, a semiconductor device and a delay time measuring method with which it is possible to measure the delay time of a circuit element that is a measurement object with high accuracy.SOLUTION: The delay time measuring device comprises: a synthesizing unit for generating a composite signal synthesized from a signal received at the input terminal of a circuit element and a signal outputted from the circuit element; a delay measurement auxiliary circuit 10 including a counter for counting the pulses appearing in the composite signal and obtaining a count value; and a delay measurement processing unit 30 for supplying a pulse signal including a string of pulses whose pulse width increases by a prescribed increment value at a time with the passage of time to the input terminal of the circuit element, determining for each pulse whether or not the count value of the counter is 1 at a point of time after the lapse of a prescribed time from the leading edge of the pulse, and obtaining the pulse width when its count value is determined to be 1 as a measured delay time of the circuit element.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a delay time measuring device for measuring the delay time of a circuit element, a semiconductor device, and a method of measuring the delay time.

  In a test at the time of product shipment of a semiconductor device such as a semiconductor IC (Integrated Circuit) chip, it is confirmed whether a circuit formed in the semiconductor device operates properly.

  Incidentally, a delay element may be included in a circuit formed in a semiconductor device, and in recent years, it is desired to measure the delay time of such a delay element in a test at the time of product shipment.

  For example, the tester supplies a test signal to the delay element through the input terminal of the semiconductor device, and the time from when the test signal is supplied to the signal output from the delay element appears on the output terminal of the semiconductor device By measuring, the delay time of this delay element is determined.

  Further, a technique has been proposed in which a delay measurement circuit is provided in a semiconductor device to measure the delay time of the circuit formed in the semiconductor device (see, for example, Patent Document 1).

  The delay measurement circuit includes a chopper circuit that generates a pulse having a pulse width equal to the delay time of the circuit to be measured for the delay time according to a control signal having a predetermined pulse width. The delay measurement circuit sequentially generates pulses in which the pulse width of the pulse output from the chopper circuit is narrowed stepwise by a predetermined width, and the number of generated pulses is counted by a counter. The minimum pulse width that can be counted by the counter is the result of multiplying the pulse count value at the time when the pulse can not be counted by the counter because the pulse width is narrowed by a predetermined width. That is, the sum of the limit pulse widths is taken as the delay time of the circuit to be measured.

WO 2013/076799 Publication

  However, as described above, when measuring the delay time from when the test signal is supplied to the input terminal of the semiconductor device to when the signal passed through the delay element appears at the output terminal of the semiconductor device, the delay time The delay time in the path from the output terminal to the delay element is included. Therefore, the delay time of only the circuit to be measured can not be measured accurately.

  On the other hand, in the method disclosed in Patent Document 1, when the pulse width of the pulse output from the chopper circuit is narrowed stepwise by a predetermined width, the predetermined width is set using element delay of the inverter or the NAND element. doing. The element delay of such an inverter or NAND element fluctuates due to manufacturing variations or environmental temperature.

  Further, in the method disclosed in Patent Document 1, the number of pulses output from the chopper circuit is counted by a counter, and the pulse width of the pulse becomes the limit pulse when the counting operation of the pulse becomes impossible by the counter. It is judged that it became smaller than the width. At this time, the limit pulse width of the pulse that can be counted by the counter fluctuates due to manufacturing variations or environmental temperature.

  From the above, even with the method disclosed in Patent Document 1, there is a problem that the delay time of the circuit element to be measured can not be measured accurately.

  Therefore, an object of the present invention is to provide a delay time measuring device, a semiconductor device, and a method of measuring a delay time that can measure the delay time of a circuit element to be measured with high accuracy.

  The delay time measuring device according to the present invention is a delay time measuring device for measuring the delay time of a circuit element, and is a combination of the signal received at the input end of the circuit element and the signal output from the circuit element. And a delay measurement auxiliary circuit including a synthesis unit for generating a signal and a counter for counting pulses appearing in the synthesized signal to obtain a count value, and a train of pulses whose pulse width increases by a predetermined increment as time passes. A pulse signal is supplied to the input end of the circuit element, and it is determined whether or not the count value of the counter is 1 when a predetermined period has elapsed from the time of the leading edge of the pulse for each pulse. And a delay measurement processing unit that obtains the pulse width when it is determined that the count value is 1 as a measurement delay time of the circuit element.

  The delay time measuring device according to the present invention is a delay time measuring device for measuring the delay time of the first to r (r is an integer of 2 or more) circuit elements connected in series. A synthesis unit that generates a synthesis signal that synthesizes the signal received at the input end of the first circuit element and the signal output from each of the first to rth circuit elements, and a pulse appearing in the synthesis signal Supplying a pulse signal to the input end of the circuit element including a delay measurement auxiliary circuit including a counter that counts a number to obtain a count value, and a train of pulses whose pulse width increases by a predetermined increment as time passes; It is determined whether or not the count value of the counter is (r-1) when a predetermined period has elapsed from the time of the leading edge of the pulse for each pulse, and the count value is (r-1) The delay of the pulse width when it is determined that there is a minimum delay It is determined whether or not the count value of the counter at the time when the predetermined period has elapsed from the time point of the leading edge of the pulse for each pulse is a first measurement delay time representing the time interval. And a delay measurement processing unit that obtains the pulse width when it is determined that the count value is 1 as a second measurement delay time that represents the maximum delay time.

  A semiconductor device according to the present invention has a circuit element for delaying and outputting a signal received at an input end, and a delay measurement auxiliary circuit, wherein the delay measurement auxiliary circuit is a signal at an input end of the circuit element A synthesis unit that generates a synthesis signal that synthesizes the signal output from the circuit element, and a counter that counts the number of pulses appearing in the synthesis signal and outputs a count value signal representing the number of pulses Including.

  A semiconductor device according to the present invention includes first to r (r is an integer of 2 or more) circuit elements connected in series and a delay measurement auxiliary circuit, and the delay measurement auxiliary circuit A synthesis unit for generating a synthesized signal obtained by synthesizing the signal at the input end of the first circuit element and the signal output from each of the first to rth circuit elements, and a pulse appearing in the synthesized signal And a counter that counts a number and outputs a count signal representing the number of said pulses.

  A method of measuring a delay time according to the present invention is a method of measuring a delay time for measuring a delay time of a circuit element, and combining a signal received at an input end of the circuit element and a signal output from the circuit element A pulse signal including a train of pulses whose pulse width is increased by a predetermined increment value as time passes, is supplied to the input end of the circuit element, and for each pulse, the leading edge of the pulse is generated. It is determined whether or not the number of pulses appearing in the composite signal is 1 before a predetermined period of time elapses from the time point, and the pulse width when it is determined that the number of pulses is 1 is the circuit Obtained as the measurement delay time of the element.

  In the present invention, a composite signal is generated by combining the signal received at the input end of the circuit element whose delay time is to be measured and the signal output from the circuit element, and the pulse width increases by a predetermined amount over time. A pulse signal comprising a train of pulses which increases by one is supplied to the input of this circuit element. Here, for each pulse, the number of pulses appearing in the composite signal described above is counted from the time of the leading edge of the pulse to the lapse of a predetermined period. Then, the pulse width when the number of pulses reaches 1 is obtained as the measurement delay time of the circuit element.

  Therefore, according to the present invention, the delay that occurs between the external terminal of the semiconductor device in which the circuit element whose delay time is to be measured is formed and the input end (output end) of the circuit element is not included. Therefore, it becomes possible to perform delay time measurement with high accuracy.

  Also, in the present invention, a pulse narrower than the limit pulse width that does not allow counting operation with the counter is not handled. Therefore, when the pulse width of the pulse having the pulse width corresponding to the delay time of the circuit to be measured is successively reduced, the number of pulses is counted by the counter, and the counting operation becomes impossible. The delay time can be measured with high accuracy as compared with a device that measures the delay time based on the count value of.

FIG. 1 is a block diagram showing a configuration of a test system 100 including a delay time measurement device according to the present invention. FIG. 6 is a circuit diagram showing an example of a delay measurement auxiliary circuit 10 formed in a semiconductor IC chip 200 and a circuit element TG to be measured. 10 is a flowchart illustrating a procedure of delay measurement processing performed by the delay measurement processing unit 30 included in the tester 300. It is a time chart showing operation | movement of the delay measurement auxiliary | assistant circuit 10 by the delay measurement process shown in FIG. FIG. 6 is a circuit diagram showing a configuration of a delay measurement auxiliary circuit 10 employed when measuring delay times of circuit elements TG1 and TG2 connected in series. When measuring the delay time of the circuit element TG1 and TG2 which are connected in series, it is a flowchart showing an example of the delay measurement process which the tester 300 performs. FIG. 7 is a time chart showing the operation of the delay measurement auxiliary circuit 10 by the delay measurement process shown in FIG. 6. FIG. 7 is a time chart showing the operation of the delay measurement auxiliary circuit 10 by the delay measurement process shown in FIG. 6. It is a circuit diagram showing the composition of delay measurement auxiliary circuit 10 adopted when measuring the delay time of r (r is an integer greater than or equal to 2) pieces of circuit elements TG1 to TGr connected in series. FIG. 10 is a circuit diagram showing a modification of the delay measurement auxiliary circuit 10 shown in FIG. 9;

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing the configuration of a test system 100 including a delay time measurement device according to the present invention. The test system 100 includes a semiconductor IC (Integrated Circuit) chip 200 and a tester 300 that performs a test at the time of product shipment of the semiconductor IC chip 200.

  In the semiconductor IC chip 200, as shown in FIG. 2, a circuit element TG whose delay time is to be measured, and a delay measurement auxiliary circuit 10 included in the delay time measurement device according to the present invention are formed.

  The circuit element TG is, for example, a delay element that delays and outputs a pulse signal supplied to its own input while maintaining its waveform.

  The delay measurement auxiliary circuit 10 includes a two-input OR gate 12 and a counter 13.

  The first input end of the OR gate 12 is connected to the input end of the circuit element TG whose delay time is to be measured via the node n1, and the second input end of the OR gate 12 is the circuit element TG via the node n2. Connected to the output end of.

  The OR gate 12 calculates the logical sum of the binary input signal input to the circuit element TG and the binary output signal output from the circuit element TG. The OR gate 12 generates a composite signal Ct by combining the binary input signal input to the circuit element TG and the binary output signal output from the circuit element TG according to the logical sum, and generates a composite signal Ct. Supply to the clock terminal of

  The counter 13 counts the number of positive polarity pulses of logic level 1 appearing in the composite signal Ct as follows.

  That is, the counter 13 counts the number of pulses from the initial value “0”, and repeats the counting operation of returning the count value to the initial value “0” at the next pulse when the counted value reaches “2”. The counter 13 supplies a count value signal CD representing the count value to the tester 300 via the external terminal Ps of the semiconductor IC chip 200. Incidentally, even if the count value signal CD is once held in a register (not shown) or the like formed in the semiconductor IC chip 200, it may be supplied to the tester 300 through the external terminal Pd of the semiconductor IC chip 200. good.

  In the example shown in FIG. 2, the counter 13 is not provided on the tester 300 side such as the delay measurement processing unit 30, but is provided in the delay measurement auxiliary circuit 10. This is because, when the output signal from the OR gate 12 is directly output, the possibility that an error occurs in the inspection becomes large when the waveform is broken. Therefore, by providing the counter 13 in the delay measurement auxiliary circuit 10, such count can be reduced because the count data is generated and output in the circuit.

  The reset terminal R of the counter 13 is connected to an external terminal Pdr for reset that is used by an internal circuit (not shown) of the semiconductor IC chip 200 through the node n3. The external terminal Pdr is connected to the tester 300. When, for example, the reset signal RST of logic level 0 is supplied from the tester 300 via the external terminal Pdr, the counter 13 resets the count value described above, that is, sets the initial value to “0”.

  The tester 300 supplies various test signals to the semiconductor IC chip 200 to operate the internal circuit, and compares the operation result with an expected value to confirm whether the semiconductor IC chip 200 is non-defective or not. Do so-called functional tests.

  Furthermore, the tester 300 operates the delay measurement auxiliary circuit 10 and the circuit element TG formed in the semiconductor IC chip 200 in the procedure according to the delay measurement flow shown in FIG. It includes a delay measurement processing unit 30 to measure.

  In FIG. 3, first, the delay measurement processing unit 30 sets a predetermined pulse width W0 as an initial pulse width W (step S11). The pulse width W0 is smaller than the delay time on the specifications of the circuit element TG.

  Next, the delay measurement processing unit 30 supplies the reset signal RST to the reset terminal R of the counter 13 of the delay measurement auxiliary circuit 10 via the external terminal Pdr of the semiconductor IC chip 200 (step S12). Thereby, the count value of the said counter 13 is reset to "0".

  Next, the delay measurement processing unit 30 supplies a delay measurement pulse signal including the pulse DP having the pulse width W to the input end of the circuit element TG via the external terminal Pd of the semiconductor IC chip 200 (step S13).

  The delay measurement processing unit 30 waits for a predetermined measurement standby period Sb from the time point of the leading edge of the pulse DP (step S14), and then the count value represented by the count value signal CD output from the counter 13 It is determined whether it is "1" (step S15). The measurement standby period Sb has, for example, a period length obtained by adding a predetermined margin period to the delay time of the circuit element TG specified on the specification. That is, the measurement standby period Sb is longer than the delay time on the specification of the circuit element TG. Furthermore, the measurement standby period Sb is shorter than the period of the pulse DP by the delay measurement pulse signal.

  If it is determined in step S15 that the count value represented by the count value signal CD is not “1”, the delay measurement processing unit 30 newly adds the pulse width W to the predetermined increase value g. The pulse width W is set (step S16). The increase value g has, for example, a magnitude corresponding to an allowable error value of the delay time of the circuit element TG permitted on the specification of the semiconductor IC chip 200.

  After execution of step S16, the delay measurement processing unit 30 returns to execution of step S12, and performs the operations of steps S12 to S15 described above again.

  Here, when it is determined in step S15 that the count value represented by the count value signal CD is “1”, the delay measurement processing unit 30 determines the current pulse width W as the measurement delay time of the circuit element TG. Then, a measurement delay time signal DT representing this measurement delay time is generated (step S17).

  Thus, the delay measurement processing unit 30 repeatedly executes the series of measurement processing in steps S12 to S16 until it is determined in step S15 that the count value represented by the count value signal CD is “1”. . Thereby, the delay measurement processing unit 30 supplies a delay measurement pulse signal including a series of the pulse DP whose pulse width of the pulse DP increases by an increase value g as time passes, to the input end of the circuit element TG. The pulse width W0 of the first pulse DP in the train of pulses DP is smaller than the delay time on the specifications of the circuit element TG.

  During this time, the delay measurement processing unit 30 takes, for each pulse DP, the number of pulses (CD) counted by the counter 13 from the leading edge of this pulse DP until the measurement standby period Sb elapses. The pulse width W when “1” becomes “1” is taken as the measurement delay time of the circuit element TG.

The operation of the delay measurement auxiliary circuit 10 when the delay measurement processing shown in FIG. 3 is performed on the delay measurement auxiliary circuit 10 and the circuit element TG will be described in detail below along the time chart shown in FIG. Do.
[Measurement processing ds1]
The delay measurement processing unit 30 first supplies the reset signal RST of logic level 0 to the reset terminal R of the counter 13 of the delay measurement auxiliary circuit 10 in the first round of measurement processing ds1 in steps S12 to S16. The count value of the counter 13 is reset to "0" (S12). Next, as shown in FIG. 4, the delay measurement processing unit 30 supplies a pulse DP having a pulse width W0 to the input end of the circuit element TG (S13). Thereby, a pulse signal including the pulse DP is supplied to the OR gate 12 of the delay measurement auxiliary circuit 10 via the node n1. Then, the OR gate 12 supplies the synthesized signal Ct including the pulse DP having the pulse width W 0 to the clock terminal of the counter 13. Thereby, as shown in FIG. 4, the counter 13 counts up the count value represented by the count value signal CD from "0" to "1" at the timing of the rising edge portion of the pulse DP in the composite signal Ct. Do.

  Here, the circuit element TG outputs a pulse DPd obtained by delaying the pulse DP having the pulse width W0 described above by the delay time DLY. The pulse DPd is supplied to the OR gate 12 via the node n2. At this time, the pulse width W0 of the pulse DP is smaller than the delay time DLY of the circuit element TG. Therefore, the OR gate 12 supplies the synthesized signal Ct in which the pulse corresponding to the second pulse DPd appears following the pulse corresponding to the first pulse DP as described above to the clock terminal of the counter 13. Thereby, as shown in FIG. 4, the counter 13 counts the count value represented by the count value signal CD from “1” to “2” at the timing of the rising edge portion of the pulse corresponding to the pulse DPd in the composite signal Ct. Count up to

After waiting for the measurement standby period Sb (S14) from the time of the rising edge of the pulse DP having the pulse width W0, the delay measurement processing unit 30 takes in the count value signal CD output from the counter 13, and the count value It is determined whether it is "1" (S15). At this time, as shown in FIG. 4, in the measurement process ds1, the count value represented by the count value signal CD is “2”. Therefore, the delay measurement processing unit 30 sets a new pulse width (W0 + g) obtained by adding the increase value g to the current pulse width W0 (S16), and subsequently executes the second round of measurement processing ds2 .
[Measurement processing ds2]
In the measurement process ds2, as shown in FIG. 4, the delay measurement processing unit 30 first supplies the reset signal RST at the logic level 0 to the reset terminal R of the counter 13 to set the count value of the counter 13 to “0. Reset to "" (S12). Next, as shown in FIG. 4, the delay measurement processing unit 30 supplies a pulse DP having a pulse width (W0 + g) to the input end of the circuit element TG (S13). Thus, a signal including the pulse DP is supplied to the OR gate 12 via the node n1. Then, the OR gate 12 supplies the synthesized signal Ct including the pulse corresponding to the pulse DP having the pulse width (W0 + g) to the clock terminal of the counter 13. Thereby, as shown in FIG. 4, the counter 13 counts the count value represented by the count value signal CD from “0” to “1” at the timing of the rising edge portion of the pulse corresponding to the pulse DP in the composite signal Ct. Count up to

  Here, the circuit element TG outputs a pulse DPd obtained by delaying the pulse DP having the above-described pulse width (W0 + g) by the delay time DLY. The pulse DPd is supplied to the OR gate 12 via the node n2. At this time, the pulse width (W0 + g) of the pulse DP is smaller than the delay time DLY of the circuit element TG as shown in FIG. Therefore, the OR gate 12 supplies the synthesized signal Ct in which the pulse corresponding to the second pulse DPd appears following the pulse corresponding to the first pulse DP to the clock terminal of the counter 13. Thereby, as shown in FIG. 4, the counter 13 counts the count value represented by the count value signal CD from “1” to “2” at the timing of the rising edge portion of the pulse corresponding to the pulse DPd in the composite signal Ct. Count up to

The delay measurement processing unit 30 counts the count value indicated by the count value signal CD output from the counter 13 after the elapse of the measurement standby period Sb from the time of the rising edge of the pulse DP having the pulse width (W0 + g) (S14) It is determined whether or not is "1" (S15). At this time, as shown in FIG. 4, in the measurement process ds2, the count value indicated by the count value signal CD is "2". Therefore, the delay measurement processing unit 30 sets a new pulse width (W0 + 2g) as the current pulse width (W0 + g) added with the increase value g (S16), and continues the third round of measurement processing ds3. Run.
[Measurement processing ds3]
Also in the measurement process ds3, the delay measurement processing unit 30 temporarily resets the count value of the counter 13 to "0" by the reset signal RST of the logic level 0 as in the measurement process ds2 (S12). Then, after the pulse DP having the pulse width (W0 + 2g) is supplied to the input end of the circuit element TG (S13) and after waiting for the measurement standby period Sb (S14), the delay measurement processing unit 30 counts the count value of the counter 13 It is determined whether it is "1" (S15). In the measurement process ds3, as shown in FIG. 4, the pulse width (W0 + 2g) of the pulse DP is smaller than the delay time DLY of the circuit element TG. Therefore, also in the measurement process ds3, as in the measurement process ds2, the composite signal Ct in which a pulse corresponding to the second pulse DPd appears following the pulse corresponding to the first pulse DP is provided to the clock terminal of the counter 13. Supplied.

Therefore, even in the measurement process ds3, the count value of the counter 13 is “2”, and the delay measurement processing unit 30 sets a new pulse width (W0 + 3 g) as the current pulse width (W0 + 2 g) plus the increase value g. The setting is made (S16), and the measurement process ds4 of the fourth cycle is subsequently executed.
[Measurement processing ds4]
Also in the measurement process ds4, the delay measurement processing unit 30 first resets the count value of the counter 13 to “0” by the reset signal RST of the logic level 0 as in the measurement process ds3 (S12). Then, after the pulse DP having the pulse width (W0 + 3g) is supplied to the input end of the circuit element TG (S13), and after waiting for the measurement standby period Sb (S14), the delay measurement processing unit 30 counts the count value of the counter 13 It is determined whether it is "1" (S15).

  In the measurement process ds4, as shown in FIG. 4, the pulse width (W0 + 3g) of the pulse DP is equal to the delay time DLY of the circuit element TG. Therefore, in the measurement process ds4, as shown in FIG. 4, the composite signal Ct representing the logical sum of the signal of the node n1 including the pulse DP and the signal of the node n2 including the pulse DPd has a logic level 1 alone. Only one pulse will appear. Thereby, in the measurement process ds4, the count value of the counter 13 becomes “1”, so the delay measurement processing unit 30 measures the measurement delay time signal DT representing the current pulse width (W0 + 3g) as the delay time DLY of the circuit element TG. Are generated (S17). That is, the delay time DLY of the circuit element TG is measured to be (W0 + 3 g).

  As described above, in the above-described embodiment, the delay measurement auxiliary circuit 10 is provided in the semiconductor IC chip 200 in order to measure the delay time of the circuit element TG formed in the semiconductor IC chip 200.

  The delay measurement auxiliary circuit 10 includes an OR gate 12 as a synthesis unit that generates a synthesized signal Ct obtained by synthesizing a signal received at an input end of a circuit element to be subjected to delay measurement and a signal output from the circuit element. A counter 13 is included which counts the number of pulses appearing in the composite signal to obtain a count value.

  Furthermore, in the present invention, first, the delay measurement processing unit 30 included in the tester 300 is a circuit element to be subjected to delay measurement for a pulse signal including a train of pulses DP whose pulse width increases by an increase value g as time passes. Supply to the input end of TG.

  Here, when the pulse width of the pulse DP is smaller than the delay time of the circuit element TG, the synthesized signal Ct is delayed by the circuit element TG and output following the first pulse corresponding to the pulse DP. A second pulse corresponding to the output pulse DPd appears. Therefore, at this time, the number of pulses appearing in the synthesized signal Ct is “2”.

  On the other hand, when the pulse width of the pulse DP is equal to or longer than the delay time of the circuit element TG, the pulse corresponding to the pulse DP and the pulse DPd delayed and output by the circuit element TG are supported in the composite signal Ct. And overlapping pulses overlap each other. Therefore, at this time, the number of pulses appearing in the synthesized signal Ct is “1”.

  That is, when the pulse signal as described above is supplied to the circuit element TG, for each pulse DP, the number of pulses appearing in the combined signal during a predetermined period (Sb) from the time of the leading edge of the pulse is The pulse width (W) at the time of becoming "1" becomes equal to the delay time of the circuit element TG.

  Therefore, the delay measurement processing unit 30 first supplies the circuit element TG with a pulse signal including a series of pulses DP in which the pulse width W increases by an increase value g as time passes (S13). Here, for each pulse DP, the delay measurement processing unit 30 determines whether the count value of the counter 13 is “1” at the time when a predetermined period (Sb) has elapsed (S14) from the leading edge of the pulse. It judges (S15). At this time, the delay measurement processing unit 30 sets the pulse width W when it is determined that the count value of the counter 13 is “1” as the measurement delay time of the circuit element TG (S17).

  Therefore, according to the delay time measurement using the delay measurement auxiliary circuit 10, in the measured delay time information, there is a delay caused between the external terminal of the semiconductor IC chip 200 and the input end and the output end of the circuit element TG. Since it is not included, it is possible to measure the delay time with high accuracy.

  Further, in the delay measurement auxiliary circuit 10, a pulse signal including a pulse narrower than the minimum pulse width that can be counted by the counter 13 is not input to the clock terminal of the counter 13. Since the limit pulse width fluctuates due to manufacturing variations or environmental temperature etc., when a pulse signal having a pulse width near the limit pulse width is supplied to the clock terminal of the counter, this counter It becomes unclear whether or not to perform the counting operation.

  Therefore, while sequentially generating pulses in which the pulse width of a pulse having a pulse width corresponding to the delay time of the circuit to be measured is narrowed stepwise, the number of the pulses is counted by a counter, and the counting operation can not be performed by the counter. It becomes possible to measure the delay time with high accuracy as compared with the device which determines the delay time based on the pulse count value at the time point.

  In the above-described embodiment, the measurement operation of the delay time by the tester 300 and the delay measurement auxiliary circuit 10 has been described by taking the case of measuring the delay time of a single circuit element TG as an example. The number of circuit elements to be connected is not limited to one.

  FIG. 5 is a circuit diagram showing a configuration of a delay measurement auxiliary circuit 10 provided when measuring the delay time of two circuit elements TG1 and TG2 connected in series.

  The delay measurement auxiliary circuit 10 shown in FIG. 5 includes a 3-input OR gate 22 and a counter 23.

  The first input end of the OR gate 22 is connected to the input end of the circuit element TG1 via the node n0. The second input end of the OR gate 22 is connected to the output end of the circuit element TG1 and the input end of the circuit element TG2 via the node n1, and the third input end of the OR gate 22 is connected to the circuit via the node n2. It is connected to the output end of the element TG2.

  The OR gate 22 has a binary signal (logic level 0 or 1) input through the node n0, a binary signal input through the node n1, and a binary signal input through the node n2. Calculate the logical sum with the signal. The OR gate 22 generates a combined signal Ct by combining the binary input signal input to the circuit element TG1 and the binary output signal output from each of the circuit elements TG1 and TG2 according to the logical sum. Is supplied to the clock terminal of the counter 23.

  The counter 23 counts the number of positive polarity pulses of logic level 1 appearing in the composite signal Ct as follows.

  That is, the counter 23 counts the number of pulses from the initial value “0”, and repeats the counting operation of returning the count value to the initial value “0” at the next pulse when the count value reaches “3”. The counter 23 supplies a count value signal CD representing the count value to the tester 300 via the external terminal Ps of the semiconductor IC chip 200. Incidentally, even if the count value signal CD is once held in a register (not shown) or the like formed in the semiconductor IC chip 200, it may be supplied to the tester 300 through the external terminal Pd of the semiconductor IC chip 200. good.

  The reset terminal R of the counter 23 is connected to a reset external terminal Pdr used by an internal circuit (not shown) of the semiconductor IC chip 200 via the node n3. The external terminal Pdr is connected to the tester 300. When, for example, a reset signal RST of logic level 0 is supplied from the tester 300 via the external terminal Pdr, the counter 23 resets the count value described above, that is, sets the initial value to “0”.

  FIG. 6 shows a semiconductor IC chip including the delay measurement auxiliary circuit 10 shown in FIG. 5 and the circuit elements TG1 and TG2 shown in FIG. 5 in order to measure the delay times of the circuit elements TG1 and TG2. It is a flowchart showing the delay measurement process given to 200. FIG.

  In FIG. 6, first, the delay measurement processing unit 30 sets a predetermined pulse width W0 as an initial pulse width W (step S11).

  Next, the delay measurement processing unit 30 supplies the reset signal RST to the reset terminal R of the counter 23 of the delay measurement auxiliary circuit 10 via the external terminal Pdr of the semiconductor IC chip 200 (step S12). Thereby, the count value of the said counter 23 is reset to "0".

  Next, the delay measurement processing unit 30 supplies a delay measurement pulse signal including the pulse DP having the pulse width W to the input end of the circuit element TG1 via the external terminal Pd of the semiconductor IC chip 200 (step S13).

  The delay measurement processing unit 30 waits for a predetermined measurement standby period Sc from the time of the leading edge of the pulse DP (step S14), and then the count value represented by the count value signal CD output from the counter 23 It is determined whether it is "2" (step S15a). The measurement standby period Sc has, for example, a period length obtained by adding a predetermined margin period to the time obtained by adding the delay time of the circuit element TG1 and the delay time of the circuit element TG2 specified in the specification. That is, the measurement standby period Sc is longer than the sum of the delay time on the specification of the circuit element TG1 and the delay time on the specification of the circuit element TG2. Furthermore, the measurement waiting period Sc is shorter than the period of the pulse DP by the delay measurement pulse signal.

  If it is determined in step S15a that the count value represented by the count value signal CD is not “2”, the delay measurement processing unit 30 newly adds a pulse width W to which the predetermined increase value g is added. The pulse width W is set (step S16).

  After execution of step S16, the delay measurement processing unit 30 returns to execution of step S12, and performs the operations of steps S12 to S14 and S15a described above again.

  Here, when it is determined in step S15a that the count value represented by the count value signal CD is “2”, the delay measurement processing unit 30 determines that the current pulse width W is equal to that of the circuit elements TG1 and TG2. The measurement delay time DT1, which represents the smaller measurement delay time, is generated (step S17a).

  After execution of step S17a, the delay measurement processing unit 30 sets a new pulse width W that is obtained by adding the increase value g to the pulse width W (step S21).

  Next, the delay measurement processing unit 30 supplies the reset signal RST to the reset terminal R of the counter 23 of the delay measurement auxiliary circuit 10 via the external terminal Pdr of the semiconductor IC chip 200 (step S22). Thereby, the count value of the said counter 23 is reset to "0".

  Next, the delay measurement processing unit 30 supplies a delay measurement pulse signal including the pulse DP having the pulse width W to the input end of the circuit element TG1 via the external terminal Pd of the semiconductor IC chip 200 (step S23).

  The delay measurement processing unit 30 waits for a predetermined measurement standby period Sc from the time of the leading edge of the pulse DP (step S24), and then the count value represented by the count value signal CD output from the counter 23 It is determined whether it is "1" (step S25).

  When it is determined in step S25 that the count value represented by the count value signal CD is not "1", the delay measurement processing unit 30 returns to the execution of the above-described step S21, and the above-described steps S21 to S25. Execute the operation again.

  On the other hand, when it is determined in step S25 that the count value represented by the count value signal CD is "1", the delay measurement processing unit 30 determines that the current pulse width W is equal to that of the circuit elements TG1 and TG2. The measurement delay time signal DT2 is generated, which represents the larger measurement delay time as the measurement delay time (step S26).

  Thus, the delay measurement processing unit 30 first repeats the series of measurement processing in steps S12 to S16 until it is determined that the count value represented by the count value signal CD is "2" in step S15a. Run.

  Thereby, the delay measurement processing unit 30 supplies a delay measurement pulse signal including a train of pulses DP whose pulse width of the pulse DP increases by an increase value g as time passes, to the input end of the circuit element TG1. The pulse width W0 of the first pulse DP in the train of pulses DP is smaller than the delay time on the specifications of the circuit elements TG1 and TG2.

  During this time, the delay measurement processing unit 30 determines, for each pulse DP, whether or not the count value (CD) of the counter 23 at the time when the measurement standby period Sc has elapsed from the leading edge of this pulse DP is "2". judge. Here, the delay measurement processing unit 30 represents the pulse width W when the count value of the counter 23 is determined to be “2” as the delay time among the circuit elements TG1 and TG2 which has the smaller delay time. Measurement time (DT1).

  Then, subsequently, the delay measurement processing unit 30 repeatedly executes the series of measurement processing in steps S21 to S25 until it is determined in step S25 that the count value represented by the count value signal CD is "1". .

  Thereby, the delay measurement processing unit 30 supplies the delay measurement pulse signal including the train of the pulse DP whose pulse width of the pulse DP increases by an increase value g as time elapses to the input end of the circuit element TG1.

  During this time, the delay measurement processing unit 30 determines, for each pulse DP, whether or not the count value (CD) of the counter 23 at the time when the measurement standby period Sc has elapsed from the leading edge of this pulse DP is "1". judge. Here, the delay measurement processing unit 30 represents the pulse width W when the count value of the counter 23 is determined to be “1” as the delay time of the circuit element TG1 or TG2 having the larger delay time. Measurement time (DT2).

  That is, by applying the delay measurement process shown in FIG. 6 to delay measurement auxiliary circuit 10 shown in FIG. 5 and circuit elements TG1 and TG2, the delay time (DT1) of the circuit element TG1 or TG2 having the smaller delay time (DT1) And the larger delay time (DT2) is measured.

An example of the operation of measuring the delay time of each of the circuit elements TG1 and TG2 by the delay measurement process shown in FIG. 6 will be described below along the time charts shown in FIGS. 7 and 8.
[Measurement processing ds1]
The delay measurement processing unit 30 first supplies the reset signal RST of logic level 0 to the reset terminal R of the counter 23 of the delay measurement auxiliary circuit 10 in the measurement process ds1 of the first cycle in steps S12 to S16. The count value of the counter 23 is reset to "0" (S12). Next, as shown in FIG. 7, the delay measurement processing unit 30 supplies a pulse DP having a pulse width W0 to the input end of the circuit element TG1 (S13). Thus, a signal including the pulse DP is supplied to the OR gate 22 of the delay measurement auxiliary circuit 10 via the node n0. Then, the OR gate 22 supplies a synthesized signal Ct including a pulse corresponding to the pulse DP having the pulse width W0 to the clock terminal of the counter 23. Thereby, as shown in FIG. 7, the counter 23 counts the count value represented by the count value signal CD from “0” to “1” at the timing of the rising edge portion of the pulse corresponding to the pulse DP in the composite signal Ct. Count up to

  Here, when the circuit element TG1 receives the pulse DP having the above pulse width W0, it outputs a pulse DPd1 delayed by a delay time DLY1 as shown in FIG. The pulse DPd1 is supplied to the OR gate 22 via the node n1. At this time, the pulse width W0 of the pulse DP is smaller than the delay time DLY1 of the circuit element TG1. Therefore, the OR gate 22 supplies the synthesized signal Ct in which the pulse corresponding to the second pulse DPd1 appears to the clock terminal of the counter 23 following the pulse corresponding to the first pulse DP as described above. Thereby, as shown in FIG. 7, the counter 23 counts the count value represented by the count value signal CD from “1” to “2” at the timing of the rising edge portion of the pulse corresponding to the pulse DPd1 in the composite signal Ct. Count up to

  When the circuit element TG2 receives the pulse DPd1 having the pulse width W0, it outputs a pulse DPd2 delayed by a delay time DLY2 as shown in FIG. The pulse DPd2 is supplied to the OR gate 22 via the node n2. At this time, the pulse width W0 of the pulse DPd1 is smaller than the delay time DLY2 of the circuit element TG2. Therefore, the OR gate 22 supplies the synthesized signal Ct in which the pulse corresponding to the third pulse DPd2 appears to the clock terminal of the counter 23 following the pulse corresponding to the second pulse DPd1 as described above. Thereby, as shown in FIG. 7, the counter 23 counts the count value represented by the count value signal CD from “2” to “3” at the timing of the rising edge portion of the pulse corresponding to the pulse DPd2 in the composite signal Ct. Count up to

The delay measurement processing unit 30 waits for the measurement standby period Sc from the time of the rising edge portion of the pulse DP (S14), and then takes in the count value signal CD output from the counter 23, and the count value is "2". It is determined whether there is any (S15a). At this time, as shown in FIG. 7, in the first round of measurement processing ds1, the count value represented by the count value signal CD is “3”. Therefore, the delay measurement processing unit 30 sets a new pulse width (W0 + g) obtained by adding the increase value g to the current pulse width W0 (S16), and subsequently executes the second round of measurement processing ds2 .
[Measurement processing ds2]
In the measurement process ds2, as shown in FIG. 7, the delay measurement processing unit 30 first supplies the reset signal RST of the logic level 0 to the reset terminal R of the counter 23, whereby the count value of the counter 23 is “0”. Reset to "" (S12). Next, as shown in FIG. 7, the delay measurement processing unit 30 supplies a pulse DP having a pulse width (W0 + g) to the input end of the circuit element TG1 (S13). Thus, a signal including the pulse DP is supplied to the OR gate 22 via the node n0. Then, the OR gate 22 supplies the synthesized signal Ct including the pulse DP having this pulse width (W0 + g) to the clock terminal of the counter 23. Thereby, as shown in FIG. 7, the counter 23 counts the count value represented by the count value signal CD from “0” to “1” at the timing of the rising edge portion of the pulse corresponding to the pulse DP in the composite signal Ct. Count up to

  Here, the circuit element TG1 outputs a pulse DPd1 obtained by delaying the pulse DP having the above pulse width (W0 + g) by the delay time DLY1. The pulse DPd1 is supplied to the OR gate 22 via the node n1. At this time, the pulse width (W0 + g) of the pulse DP is smaller than the delay time DLY1 of the circuit element TG1 as shown in FIG. Therefore, the OR gate 22 supplies the synthesized signal Ct in which the pulse corresponding to the second pulse DPd1 appears following the pulse corresponding to the first pulse DP to the clock terminal of the counter 23. Thereby, as shown in FIG. 7, the counter 23 counts the count value represented by the count value signal CD from “1” to “2” at the timing of the rising edge portion of the pulse corresponding to the pulse DPd1 in the composite signal Ct. Count up to

  When circuit element TG2 receives pulse DPd1 having a pulse width (W0 + g), it outputs pulse DPd2 delayed by delay time DLY2 as shown in FIG. The pulse DPd2 is supplied to the OR gate 22 via the node n2. At this time, the pulse width (W0 + g) of the pulse DPd1 is smaller than the delay time DLY2 of the circuit element TG2. Therefore, the OR gate 22 supplies the synthesized signal Ct in which the pulse corresponding to the third pulse DPd2 appears to the clock terminal of the counter 23 following the pulse corresponding to the second pulse DPd1 as described above. Thereby, as shown in FIG. 7, the counter 23 counts the count value represented by the count value signal CD from “2” to “3” at the timing of the rising edge portion of the pulse corresponding to the pulse DPd2 in the composite signal Ct. Count up to

The delay measurement processing unit 30 waits from the time of the rising edge of the pulse DP having the pulse width (W0 + g) for the measurement standby period Sc (S14), and then displays the value indicated by the count value signal CD output from the counter 23. It is determined whether the numerical value is "2" (S15a). At this time, as shown in FIG. 7, in the measurement process ds2, the count value indicated by the count value signal CD is “3”. Therefore, the delay measurement processing unit 30 sets a new pulse width (W0 + 2g) obtained by adding the increase value g to the current pulse width (W0 + g) (S16), and continues the measurement processing ds3 of the third cycle Not shown).
[Measurement processing ds3]
Also in the measurement processing ds3, the delay measurement processing unit 30 resets the count value of the counter 23 to "0" as in the measurement processing ds2 (S12). Then, after the pulse DP having the pulse width (W0 + 2g) is supplied to the input end of the circuit element TG1 (S13), and after waiting for the measurement standby period Sc (S14), the delay measurement processing unit 30 It is determined whether it is "1" (S15). In the measurement process ds3, the pulse width (W0 + 2g) of the pulse DP is smaller than the delay time DLY1 of the circuit element TG1, and the pulse width (W0 + 2g) of the pulse DP is smaller than the delay time DLY2 of the circuit element TG2.

  Therefore, also in the measurement process ds3, as in the measurement process ds2, a synthesized signal Ct in which three pulses respectively corresponding to the pulses DP, DPd1 and DPd2 appear sequentially is supplied to the clock terminal of the counter 23.

Accordingly, even in the measurement process ds3, the count value of the counter 23 is “3”, and the delay measurement processing unit 30 sets a new pulse width (W0 + 3 g) as the current pulse width (W0 + 2 g) plus the increase value g. The setting is made (S16), and the measurement process ds4 of the fourth cycle is subsequently executed.
[Measurement processing ds4]
In the measurement process ds4, as shown in FIG. 8, the delay measurement processing unit 30 resets the count value of the counter 23 to "0" by the reset signal RST of the logic level 0 (S12). Then, after the pulse DP having the pulse width (W0 + 3g) is supplied to the input end of the circuit element TG1 (S13), and after waiting for the measurement standby period Sc (S14), the delay measurement processing unit 30 counts the count value of the counter 23 It is determined whether it is "2" (S15a).

  Here, in the measurement process ds4, as shown in FIG. 8, the pulse width (W0 + 3g) of the pulse DP is smaller than the delay time DLY1 of the circuit element TG1, but the pulse width (W0 + 3g) of the pulse DPd1 is Equal to the delay time DLY2.

  Therefore, in the measurement process ds4, as shown in FIG. 8, in the combined signal Ct representing the logical sum of the signals of the nodes n0, n1 and n2, a pulse corresponding to the pulse DP and a single signal corresponding to the pulses DPd1 and DPd2 One pulse will appear.

As a result, the count value of the counter 23 becomes “2”, and the delay measurement processing unit 30 sets the pulse width (W0 + 3g) at the present time as the measurement delay time of the circuit element TG1 or TG2 having the smaller delay time. , And generates a measurement delay time signal DT1 representing this (S17a). Subsequently, the delay measurement processing unit 30 executes the measurement processing ds5 of the fifth round.
[Measurement processing ds5]
In the measurement process ds5, the delay measurement processing unit 30 sets a new pulse width (W0 + 4g) as the current pulse width (W0 + 3g) plus the increase value g (S21). Next, as shown in FIG. 8, the delay measurement processing unit 30 resets the count value of the counter 23 to “0” by the reset signal RST of the logic level 0 (S22). Then, after the delay measurement processing unit 30 supplies the pulse DP having the pulse width (W0 + 4g) to the input end of the circuit element TG1 as shown in FIG. 8 (S23) and waits for the measurement standby period Sc (S24), It is determined whether the count value of the counter 23 is "1" (S25).

  Here, in the measurement process ds5, as shown in FIG. 8, the pulse width (W0 + 4g) of the pulse DP is equal to the delay time DLY1 of the circuit element TG1, and the pulse width (W0 + 4g) of the pulse DPd1 is the delay time of the circuit element TG2 Greater than DLY2.

  Therefore, in the measurement process ds5, as shown in FIG. 8, only a single pulse in which the pulses DP, DPd1 and DPd2 overlap appears in the synthesized signal Ct representing the logical sum of the signals of the nodes n0, n1 and n2. It will be. Accordingly, since the count value of the counter 23 is “1”, the delay measurement processing unit 30 sets the pulse width (W0 + 4g) at the present time as the measurement delay time of the circuit element TG1 or TG2 having the larger delay time, A measurement delay time signal DT2 representing this is generated (S26).

  As described above, when measuring the delay time of the circuit elements TG1 and TG2 connected in series, the delay measurement auxiliary circuit 10 having the circuit configuration shown in FIG. 5 is employed, and the delay measurement process shown in FIG. Apply.

  Thereby, (W0 + 3g) is measured as the measurement delay time of the smaller delay time among the circuit elements TG1 and TG2, and (W0 + 4g) is measured as the measurement delay time of the larger delay time. Therefore, according to such delay time measurement, it can be determined whether or not the delay time of each circuit element is within the specified range on the specification.

  In the configuration shown in FIG. 5, the delay measurement auxiliary circuit 10 including the 3-input OR gate 22 and the counter 23 measures the delay times of the two circuit elements TG1 and TG2. Therefore, in order to measure the delay time of the two circuit elements TG1 and TG2, a circuit is provided as compared with the case where the delay measurement auxiliary circuit 10 including the 2-input OR gate 12 and the counter 13 shown in FIG. The scale can be reduced.

  The embodiment shown in FIG. 5 shows the configuration of the delay measurement auxiliary circuit 10 provided when measuring the delay time of each of the two circuit elements TG1 and TG2 connected in series. The number of series stages of circuit elements to be measured is not limited to two.

  For example, when measuring the delay time of r (r is an integer of 2 or more) circuit elements TG1 to TGr connected in series, the delay measurement auxiliary circuit 10 as shown in FIG. It should be formed in

  The delay measurement auxiliary circuit 10 shown in FIG. 9 includes an (r + 1) -input OR gate 102 and a counter 103.

  The OR gate 102 receives the signal at the input end of the circuit element TG1 and the signal at the output end of each of the circuit elements TG2 to TGr via the node n0 to the node nr. The OR gate 102 supplies a synthesized signal Ct representing the logical sum of the signal at the input end of the circuit element TG1 and the signal at the output end of each of the circuit elements TG2 to TGr to the clock terminal of the counter 103.

  The counter 103 counts the number of positive polarity pulses of logic level 1 appearing in the synthesized signal Ct as follows.

  That is, the counter 103 counts the number of pulses from the initial value “0”, and repeats the counting operation of returning the count value to the initial value “0” at the next pulse when the counted value reaches “r + 1”. The counter 103 externally outputs the count value signal CD representing the count value through the external terminal Pd of the semiconductor IC chip. When the counter 103 receives the reset signal RST of logic level 0 at the external terminal Pdr of the semiconductor IC chip, the counter 103 resets the above-described count value, that is, sets the initial value to “0”.

  In short, a delay time measuring device for measuring the delay time of first to r (r is an integer of 2 or more) circuit elements connected in series includes the following delay measurement auxiliary circuit and delay measurement processing unit Anything is fine.

  That is, the delay measurement auxiliary circuit (10) combines the signal received at the input terminal of the first circuit element (TG1) and the signal output from each of the first to rth circuit elements (TG1 to TGr). And a counter (103) for obtaining a coefficient value by counting the number of pulses appearing in the synthesized signal.

  First, the delay measurement processing unit (30) supplies a pulse signal including a train of pulses (DP) whose pulse width (W) increases by a predetermined increment value (g) as time passes, to the input end of the circuit element. Here, the delay measurement processing unit determines, for each pulse, whether or not the count value of the counter is (r-1) when a predetermined period (Sc) has elapsed from the time of the leading edge of the pulse. The pulse width (W) when it is determined to be (r-1) is obtained as a first measurement delay time (DT1) representing the minimum delay time. That is, the minimum delay time among the delay times of the first to rth circuit elements (TG1 to TGr) is measured.

  Subsequently, the delay measurement processing unit (30) determines, for each pulse, whether or not the count value of the counter at the time when a predetermined period (Sc) has elapsed from the time of the leading edge of the pulse is "1". The pulse width (W) when it is determined to be “1” is obtained as a second measurement delay time (DT2) representing the maximum delay time. That is, the maximum delay time among the delay times of the first to rth circuit elements (TG1 to TGr) is measured.

  Note that among the circuit elements TG1 to TGr shown in FIG. 9, a configuration may be adopted in which the circuit element TG for which the delay time is to be measured can be specified arbitrarily.

  FIG. 10 is a circuit diagram showing a modification of the configuration shown in FIG. 9 made in view of the above point.

  In the configuration shown in FIG. 10, the delay measurement auxiliary circuit 10 is the same as the configuration shown in FIG. 9 except for the addition of switches SW0 to SWr, that is, the OR gate 102 and the counter 103. The switches SW0 to SWr are made of, for example, MOS (Metal Oxide Semiconductor) type transistors, each of which is independently set to one of the on state and the off state.

  The switch SW0 connects the input end of the circuit element TG1 to the first input end of the OR gate 102 when in the on state. The switch SWk (k is an integer of 1 to r) connects the output end of the circuit element TGk to the k-th input end of the OR gate 102 in the on state.

  Here, for example, in the case where only TG2 among the circuit elements TG1 to TGr is designated as a measurement object of the delay time, only SW1 and SW2 of the switches SW0 to SWr are set to the on state, and the other switches SW0 and Set all SW3 to SWr to the off state.

  In the above embodiment, the delay element for delaying and outputting the input signal is used as a measurement target, but if it is a circuit element for outputting while maintaining the pulse width of the input signal, the purpose is to delay the signal. It is also possible to use a circuit element which is not included or a circuit block composed of a plurality of circuit elements as a measurement target.

  Further, in the above embodiment, since the pulse DP is a positive polarity pulse of logic level 1, OR gate (12 as a synthesis unit for synthesizing the signal input to the circuit element (TG, TG1) and the output signal , 22, 102). However, when the pulse DP is a negative pulse at logic level 0, an AND gate that generates a logical product result of each input as a synthesized signal Ct may be adopted as the synthesizing unit.

10 delay measurement auxiliary circuit 12, 22, 102 or gate 13, 23, 103 counter 30 delay measurement processing unit 100 test system 200 semiconductor IC chip 300 tester

Claims (11)

A delay time measuring device for measuring a delay time of a circuit element, comprising:
A synthesis unit that generates a synthesized signal that synthesizes the signal received at the input end of the circuit element and the signal output from the circuit element, and a counter that counts pulses appearing in the synthesized signal to obtain a count value Delay measurement auxiliary circuit,
A pulse signal including a train of pulses whose pulse width increases by a predetermined increment value as time passes is supplied to the input end of the circuit element, and a point in time when a predetermined period has elapsed from the point of the leading edge of the pulse for each pulse. A delay measurement processing unit that determines whether the count value of the counter at 1 is 1 and obtains the pulse width at the time when the count value is determined to be 1 as a measurement delay time of the circuit element; And a delay time measuring device.   The pulse width of the first pulse of the train of pulses is smaller than the delay time on the specification of the circuit element, and the predetermined period is longer than the delay time on the specification of the circuit element. The delay time measurement device according to 1.   The delay time measurement device according to claim 1 or 2, wherein the increase value has a magnitude corresponding to a tolerance on a specification of the delay time. The combining unit includes a logic gate that generates, as the combined signal, the result of the logical sum or logical product of the signal received at the input end of the circuit element and the signal output from the circuit element,
The counter receives the composite signal at its clock terminal, counts the number of pulses appearing in the composite signal from 0, and repeats the counting operation to return the count value to 0 when the count value reaches 2 The delay time measuring device according to any one of claims 1 to 3, which is a counter. The circuit element and the delay measurement auxiliary circuit are formed on the same semiconductor chip,
The delay time measurement device according to any one of claims 1 to 4, wherein the delay time measurement processing unit is included in a tester that tests the semiconductor chip. A delay time measuring device for measuring the delay time of first to r (r is an integer of 2 or more) circuit elements connected in series.
A combining unit generating a combined signal combining the signal received at the input end of the first circuit element and the signal output from each of the first to rth circuit elements, and appears in the combined signal A delay measurement auxiliary circuit including a counter that counts the number of pulses to obtain a count value;
A pulse signal including a train of pulses whose pulse width increases by a predetermined increment value as time passes is supplied to the input end of the circuit element, and a point in time when a predetermined period has elapsed from the point of the leading edge of the pulse for each pulse. The pulse width at the time when it is determined that the count value of the counter at (i) is (r-1) and the count value is determined to be (r-1) represents the minimum delay time. The measurement delay time is 1, and it is determined whether the count value of the counter at the time when the predetermined period has elapsed from the time point of the leading edge of the pulse for each pulse is 1 and the count value is 1 And a delay measurement processing unit configured to obtain the pulse width when it is determined to be the second measurement delay time that represents the maximum delay time. A circuit element that delays and outputs a signal received at an input end;
And a delay measurement auxiliary circuit;
The delay measurement auxiliary circuit is
A synthesizing unit that generates a synthesized signal by synthesizing the signal at the input end of the circuit element and the signal output from the circuit element;
A counter which counts the number of pulses appearing in the composite signal and outputs a count value signal representing the number of pulses. The combining unit includes a logic gate that generates, as the combined signal, the result of the logical sum or logical product of the signal received at the input end of the circuit element and the signal output from the circuit element,
The counter receives the composite signal at its clock terminal, counts the number of pulses appearing in the composite signal from 0, and repeats the counting operation to return the count value to 0 when the count value reaches 2 The semiconductor device according to claim 7, which is a counter. First to r (r is an integer of 2 or more) circuit elements connected in series;
And a delay measurement auxiliary circuit;
The delay measurement auxiliary circuit is
A combining unit that generates a combined signal combining the signal at the input end of the first circuit element and the signal output from each of the first to rth circuit elements;
A counter which counts the number of pulses appearing in the composite signal and outputs a count value signal representing the number of pulses. The combining unit uses, as the combined signal, the result of the logical sum or logical product of the signal received at the input end of the first circuit element and the signal output from each of the first to rth circuit elements. Including logic gates to generate,
The counter receives the composite signal at its clock terminal, counts the number of pulses appearing in the composite signal from 0, and counts the count value back to 0 when the count value reaches (r + 1). The semiconductor device according to claim 9, which is a counter that repeats. A delay time measuring method of measuring a delay time of a circuit element, comprising:
Generating a composite signal by combining the signal received at the input end of the circuit element and the signal output from the circuit element,
Supplying a pulse signal including a train of pulses whose pulse width increases by a predetermined increment value as time passes, to the input end of the circuit element;
It is determined whether or not the number of pulses appearing in the composite signal is 1 between the time point of the leading edge of the pulse and the lapse of a predetermined period for each pulse, and the number of pulses is 1 A method of measuring a delay time, wherein the pulse width at the time of determination is obtained as a measurement delay time of the circuit element.