JPH0675022A - Semiconductor integrated circuit device and testing method therefor - Google Patents

Abstract

PURPOSE:To measure a true access time accurately with no effect of peripheral circuit by constituting a test circuit for a semiconductor integrated circuit device generating inherent pulses based on the pulse width of a test clock signal having pulse width approximately representative of the access time of a test object. CONSTITUTION:In a semiconductor integrated circuit device incorporating a test circuit 12, the test circuit 12 generates a control timing signal SF based on a data DOUT read out from a memory circuit element M, logic output value of an operation clock signal CK, a logic output value, and an expected output value DR from a memory circuit element M. The test circuit 12 comprises a signal output circuit 12A for outputting a ternary output signal SB based on the data DOUT read out from the memory circuit element M and the operation clock signal CK, and a signal generating circuit 12B for generating the control timing signal SF based on the ternary output signal SB and the expected output value DR from the memory circuit element M.

Description

Detailed Description of the Invention

[Table of Contents] Industrial Application Field of the Prior Art (FIG. 9) Problem to be Solved by the Invention Means for Solving the Problem (FIGS. 1 and 2) Action Example (1) First Example (FIGS. 3 to 7) (2) Description of the second embodiment (FIG. 8)

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a test method thereof, and more specifically, a circuit for testing a semiconductor memory circuit built in a chip such as a gate array or a standard cell, and a circuit therefor. It relates to the test method.

In recent years, as semiconductor devices have been highly integrated and highly densified, RAMs have been mounted on chips such as gate arrays and standard cells.
A large-scale semiconductor integrated circuit (hereinafter referred to as LSI) device having a built-in (writable / readable memory at any time) tends to be developed. Further, with the demand for higher performance and higher performance of LSI devices, the access time of RAM tends to be further increased.

According to this, in order to reduce the load on the LSI tester for testing a large-scale LSI device, a test circuit for assisting the test is provided inside the LSI device. For example, a test clock input terminal is provided at the test clock input terminal. The operation test of the RAM is performed by measuring the time difference between the input of the test clock signal and the output of the test output data to the test output terminal connected to the output side peripheral circuit.

Therefore, the delay time of the test data, the test clock signal and the test output data by the test input wiring and the test clock wiring leading to the input side peripheral circuit and the output side peripheral circuit intervenes in the true access time of the RAM. Become.
As a result, as the semiconductor integrated circuit device becomes higher in function and higher in performance, the access time is getting faster and faster.
These delays cannot be ignored when trying to make a true evaluation.

In particular, the access time of the built-in RAM is 1
In a semiconductor integrated circuit device that cuts [ns], it is difficult to accurately measure the true access time by a method of supplying test data or a test clock signal from the outside and measuring based on the test output data.

In view of this, a test circuit for supplying a test clock signal having a pulse width indicating the access time of the object to be tested and generating a unique pulse based on the pulse width is constructed. What is needed is a circuit and method that can accurately measure the true access time.

[0008]

2. Description of the Related Art FIG. 9 is an explanatory diagram according to a conventional example. FIG. 9 shows an explanatory diagram of a method of testing a RAM built-in gate array according to a conventional example. For example, a RAM-incorporated gate array, which is an example of the device under test 13, includes a plurality of RAMs (memory capable of writing / reading at any time) 1, a gate array 2, an input-side peripheral circuit 3, an output-side peripheral circuit 4, and a plurality of RAMs in FIG. Other various input / output terminals.

The input side peripheral circuit 3 and the output side peripheral circuit 4 are difficult to test all the memory cells of the RAM 1 only by the functional test of the entire chip.
A test assisting function is provided to assist an LSI tester that tests the built-in gate array 13.

For example, in the case of measuring the access time of the RAM 1, in FIG. 9, first, the test mode signal T / A is supplied to the input side peripheral circuit 3 and the output side peripheral circuit 4, and the test mode signal T / A is, for example, "H". The level is set and the RAM 1 is set to the test mode. As a result, the input side peripheral circuit 3 and the output side peripheral circuit 4 are separated from the gate array 2, the test clock signal TCK and the test data TIN are supplied, and the test is performed from the output side peripheral circuit 4 similarly to a general single RAM. Output data TOUT is obtained.

During normal use, the test mode signal T / A = appears on the input side peripheral circuit 3 and the output side peripheral circuit 4.
The "L" level is supplied to put the RAM1 into the normal mode. As a result, the input side peripheral circuit 3 and the output side peripheral circuit 4 are
Is connected to the gate array 2, and when various input data are input, output data processed by the gate array 2 is output. As a result, the RAM 1 can be separated from the peripheral gate array 2 and the access time of the RAM can be measured independently.

[0012]

By the way, the conventional R
According to the method of testing the AM-incorporated gate array 13, FIG.
As shown in (a), a time difference TAA2 between the input of the test clock signal TCK to the test clock input terminal and the output of the test output data TOUT to the test output terminal connected to the output side peripheral circuit 4. Is measured (see FIG. 9B).

That is, in FIG. 9B, time t0
Then, the test clock signal TCK is input to the input side peripheral circuit 3 and the clock signal TCK reaches the input register of the RAM1 at the time t1 after the delay time T1 and the test is performed at the time t2 after the true access time TAA1. The output data TOUT is output, and the test output data TOUT appears in the output side peripheral circuit 4 at time t3 after the delay time T2.

Therefore, the delay times T1 and T2 of the test data DIN, the test clock signal TCK and the test output data TOUT by the test input wiring and the test clock wiring leading to the input side peripheral circuit 3 and the output side peripheral circuit 4 are true of the RAM1. Access time TAA1 of As a result, the delay times T1 and T2 can be reduced when the true evaluation is to be performed on the access time of the RAM 1 which is further increased in speed as the function and performance of the semiconductor integrated circuit device are improved.
Cannot be ignored.

In particular, the access time TAA1 of the built-in RAM
In the semiconductor integrated circuit device whose power consumption is less than 1 [ns], the true access time TAA1 is accurately measured depending on the method of supplying the test data DIN and the test clock signal TCK from the outside and measuring based on the test output data TOUT. Will be difficult to do.

If it is attempted to measure the true access time TAA1 by capturing the rising and falling of the test clock signal TCK between the input latch and the output latch, the sensitivity and operating speed of the output latch are reflected in the measurement accuracy. However, if a high-precision measuring device is dared to be developed, there is a problem that the development period is extended and the size is increased, and the versatility is lacking.

The present invention was created in view of the problems of the conventional example, and supplies a test clock signal having a pulse width indicating the access time of an object to be tested, and is unique based on the pulse width. It is an object of the present invention to provide a semiconductor integrated circuit device that constitutes a test circuit that generates a pulse and that can accurately measure a true access time regardless of the influence of peripheral circuits, and a test method thereof.

[0018]

[Means for Solving the Problems] FIGS. 1 (a) and 1 (b) are
2 is a principle diagram of a semiconductor integrated circuit device according to the present invention, and FIG.
(A), (b) has respectively shown the principle figure of the test method of the semiconductor integrated circuit device which concerns on this invention.

As shown in FIG. 1A, the first semiconductor integrated circuit device of the present invention is a semiconductor integrated circuit in which a test circuit 12 for assisting the test of the internal integrated circuit 11 including the memory circuit element M is incorporated. In the circuit device, the test circuit 12 causes the control timing signal based on the logical output value of the read data DOUT of the memory circuit element M and the operation clock signal CK, and the logical output value and the expected output value DR of the memory circuit element M. It is characterized by generating SF.

In the first semiconductor integrated circuit device of the present invention, the test circuit 12 is based on the read data DOUT of the memory circuit element M and the operation clock signal CK as shown in FIG. 1B. A signal output circuit 12A for outputting a ternary output signal SB, and a signal generation circuit 12B for generating a control timing signal SF based on the ternary output signal SB and an expected output value DR of the storage circuit element M are characterized. And

Further, in the second semiconductor integrated circuit device of the present invention, in the first semiconductor integrated circuit device, as shown in FIG. 1B, a pulse of the control timing signal SF is provided at the subsequent stage of the signal generating circuit 12A. Signal widening circuit 12C to widen the width
Are connected.

The first aspect of the semiconductor integrated circuit device of the present invention
The test method of at least, as shown in FIG.
In the method of testing the internal integrated circuit 11 including the memory circuit element M to be the test target 13, as shown in the processing flowchart of FIG. 2B, first, at step P1, the test clock signal TCK is sent to the test target 13 as described above. And test data T
IN is supplied, and then in step P2, the control timing signal SF returned from the device under test 13 is monitored. Then, in step P3, the access time of the memory circuit element M is determined based on the control timing signal SF. TA
It is characterized in that A is measured.

The first semiconductor integrated circuit device of the present invention
In the test method of, the control timing signal SF is
It is generated based on the logical output value of the test output data TOUT of the memory circuit element M and the test clock signal TCK, and the logical output value and the expected output value DR of the memory circuit element M.

Further, in the first test method of the semiconductor integrated circuit device of the present invention, the object to be tested is measured when the access time TAA of the memory circuit element M is measured in step P3A of the processing flowchart of FIG. 2 (b). 13 based on the control timing signal SF fed back from the test clock signal TCK
It is characterized in that the pulse width is controlled.

The second aspect of the semiconductor integrated circuit device of the present invention
In the first test method, when the access time TAA of the memory circuit element M is measured, an internal clock signal CLK is supplied to the memory circuit element M to control the pulse width of the internal clock signal CLK. The above object is achieved by performing control based on the timing signal SF and measuring the pulse width of the internal clock signal CLK.

[0026]

[Operation] According to the first semiconductor integrated circuit device of the present invention, as shown in FIG. 1A, the test circuit 12 is provided, and the read data DOUT of the memory circuit element M and the operation clock signal CK are The test circuit 1 based on the logical output value and the expected output value DR of the logical output value and the memory circuit element M.
2, the control timing signal SF is generated.

Therefore, in general, the test clock signal TCK having a pulse width indicating the access time TAA of the object 13 to be tested.
Or an internal clock signal CLK or the like, an operation clock CK is generated with high precision, the test circuit 12 and an input latch circuit are combined with each other, and the control timing signal SF is detected. No matter what,
The access time T of the memory circuit element M having a small absolute value
It becomes possible to measure AA with high accuracy.

That is, in FIG. 1B, when the signal output circuit 12A of the test circuit 12 outputs the ternary output signal SB based on the read data DOUT of the memory circuit element M and the operation clock signal CK. , Its three-value output signal S
The control timing signal SF is generated from the signal generating circuit 12B based on B and the expected output value DR of the memory circuit element M.

For example, the signal generation circuit 12B generates the control timing signal SF when the pulse width of the operation clock signal CK is larger than the access time TAA. As a result, the pulse width of the clock signal CK almost represents the access time TAA of the memory circuit element M, and by detecting the generation boundary point of the control timing signal SF externally or internally, as in the conventional example. The delay times T1 and T2 of the test data TIN, the test clock signal TCK, and the test output data TOUT by the test input wiring and the test clock wiring reaching the peripheral circuit of the memory circuit element M directly intervene in the true access time TAA of the memory circuit element M. Will not do.

As a result, the speed of the memory circuit element M is further increased as the function and performance of the semiconductor integrated circuit device are improved.
The access time TAA is not affected by the influence of the delay times T1 and T2 as in the conventional example, and the true evaluation can be performed.

In particular, even in a semiconductor integrated circuit device in which the access time TAA of the built-in memory circuit element M is less than 1 [ns], the test data DIN and the test clock signal TCK as in the conventional example are supplied from the outside and the test output thereof is output. Compared to the method of measuring based on the data TOUT, the true access time T
It becomes possible to measure AA accurately.

Furthermore, according to the second semiconductor integrated circuit device of the present invention, as shown in FIG.
A signal widening circuit 12C for widening the pulse width of the control timing signal SF is connected to the subsequent stage of B.

Therefore, even in a measuring device which is not capable of detecting the control timing signal SF having a short pulse width, the timing signal SF is widened by the signal widening circuit 12C, so that the input latch and the output latch are connected. Compared with the method of measuring the true access time TAA by catching the rising and falling of the test clock signal TCK, the measuring device of low accuracy is not dependent on the measuring accuracy of the output latch sensitivity and operating speed. Therefore, the access time T
It becomes possible to measure AA.

As a result, the versatility of the test device for the semiconductor integrated circuit device with built-in RAM can be achieved. Also,
According to the first test method of the semiconductor integrated circuit device of the present invention, as shown in the processing flowchart of FIG. 2B, the test clock signal TCK and the test data TIN are supplied to the device under test 13 in step P1. Then, in step P2, the control timing signal SF returned from the device under test 13 is monitored, and then in step P3, the access time T of the memory circuit element M is based on the control timing signal SF.
AA is measured.

For example, when the pulse width of the test clock signal TCK is larger than the access time TAA in step P2, the test output data TOUT of the memory circuit element M and the logic output value of the test clock signal TCK, the logic output value and the storage The control timing signal SF generated based on the expected output value DR of the circuit element M is detected. At this time, the pulse width of the test clock signal TCK is controlled based on the control timing signal SF returned from the device under test 13 in step P3A.

Therefore, the control timing signal for the access time TAA of the memory circuit element M which inputs and latches the test data TIN in synchronization with the trailing edge of the test clock signal TCK and outputs the read data DOUT in synchronization with its leading edge. By properly calibrating the ternary output signal SB of the signal output circuit 12A based on SF, it becomes possible to measure it accurately.

As a result, the test clock signal T having a pulse width that roughly indicates the access time TAA of the device under test 13 is obtained.
By supplying the CK and configuring the test circuit 12 that generates the control timing signal SF based on the pulse width,
By observing the pulse width of the test clock signal TCK,
True access time TA regardless of the influence of its peripheral circuits
It becomes possible to measure A accurately.

The second aspect of the semiconductor integrated circuit device of the present invention
According to this test method, when measuring the access time TAA of the memory circuit element M, the internal clock signal CLK is supplied to the memory circuit element M in step P3A, and the pulse width of the internal clock signal CLK is the control timing signal SF. The pulse width of the internal clock signal CLK is measured based on this control.

Therefore, roughly, the internal clock signal CLK having a pulse width indicating the access time TAA of the device under test 13 is obtained.
And a control timing signal S based on the pulse width.
By observing the pulse width of the internal clock signal CLK by configuring the test circuit 12 that generates F, the true access time TAA can be obtained regardless of the influence of the peripheral circuits.
Can be accurately measured.

Thus, as in the first test method, R
The detailed evaluation of the access time TAA of the memory circuit element M such as the gate array with built-in AM can be performed in a measurement system with low accuracy, and the ability of the access time TAA, which is an important parameter in the evaluation of the memory circuit element M, can be improved. It is possible to recognize with high accuracy.

[0041]

Embodiments of the present invention will now be described with reference to the drawings. 3 to 8 are views for explaining a semiconductor integrated circuit device and a test method thereof according to an embodiment of the present invention.

(1) Description of the First Embodiment FIG. 3 is an overall block diagram of a RAM built-in gate array according to the first embodiment of the present invention, and FIG. 4 is a block diagram of its pass flag detection circuit. , FIG. 5 is a diagram for explaining the operation.

For example, RA which is an example of the test object 13
3, the M built-in gate array 23 includes a gate array 21, a path flag detection circuit 22, a RAM 21A, an input side peripheral circuit 21B, an output side peripheral circuit 21D, various input / output terminals and the like.

That is, the gate array 21 is one embodiment of the internal integrated circuit 11, and is composed of a logical gate circuit such as a logical product and a logical sum, and is a normal input buffer, a normal output buffer, and a normal input port and a normal output port of the RAM 21A. Connected to.

The pass flag detection circuit 22 is the test circuit 12
Which is one example of the RA connected to the gate array 21.
It assists the M21A test. For example, the pass flag detection circuit 22 uses the test output data TIN and the operation clock signal CK as an example of the read data DOUT of the RAM 21A.
A path flag, which is an example of the control timing signal SF, is generated based on the logic output value of the test clock signal TCK, which is an example, and the comparison data, which is an example of the logic output value and the expected output value DR of the RAM 21A. The internal configuration of the pass flag detection circuit 22 will be described in detail with reference to FIG.

Further, the RAM 21A is an example of the memory circuit element M, and temporarily stores data which is variously logically processed by the gate array 21 and its result data. The input side peripheral circuit 21B disconnects the gate array 21 and the RAM 21A based on the test mode T / A and supplies the test data TIN and the test clock signal TCK to the RAM 21A. The input latch circuit 21C provided in the input side peripheral circuit 21B latches the test data TIN based on the test clock signal TCK.

Further, the output side peripheral circuit 21D disconnects the gate array 21 from the RAM 21A based on the test mode T / A and outputs the test output data TOUT read from the RAM 21A to the outside. When the test mode T / A is set to the non-test mode (during normal use), the normal input data din input to the gate array 21 is input.
The normal output data dout can be output based on

FIG. 4 is a block diagram of a path flag detection circuit according to the first embodiment of the present invention. For example, the path flag detection circuit 22 for assisting the test of the RAM 21A is composed of an input circuit 22A, a ternary output circuit 22B and a pulse detection circuit 22C in FIG.

That is, the input circuit 22A and the three-value output circuit 22
B constitutes an embodiment of the signal output circuit 12A, and includes a RAM 21A
The ternary output signal SB is output based on the read data DOUT and the test clock signal TCK. For example,
The input circuit 22A is composed of npn-type bipolar transistors (hereinafter referred to as first and second transistors) Q1 and Q2 and resistance elements R1 and R2. The current value according to the above description is detected and the voltage drop is output to the ternary output circuit 22B.

The three-value output circuit 22B is an npn-type bipolar transistor (hereinafter referred to as third to ninth transistors).
It is composed of Q3 to Q9 and resistance elements R3 to R5. For example, two sets of differential pair transistor circuits composed of third to sixth transistors Q3 to Q6 and resistance element R3, and a first constant circuit composed of eighth and ninth transistors Q8 and Q9 and resistance elements R4 and R5. 8-bit read data D by the current source Io1
Based on OUT and the test clock signal TCK supplied to the circle C point, the ternary output signal SB is generated at the circle X point, and the pulse detector circuit 22C is output from the output circuit including the seventh transistor Q7 and the resistance element R6. It is output (see circle B).

The ternary output level is set as shown in Table 1 by adjusting, for example, the third to ninth transistors Q3 to Q9 and the resistance elements R3 to R5 of the ternary output circuit.

[0052]

[Table 1]

In the embodiment of the present invention, only the ternary output signal SB generated at the round X point is "0 defective"("0") in the read data DOUT of the RAM 21A. Can not be detected separately from the "1 failure" and the "1 failure" (the logic that causes a failure when "1" is read), but by reading out the output of the circle Y point, "0 failure" and "1 failure" of data DOUT
And can be detected separately. The ternary output signal SB is output from the output circuit including the seventh transistor Q7 and the resistance element R6 to the pulse detection circuit 22C (circle B).
See point).

Further, the pulse detection circuit 22C is an embodiment of the signal generation circuit 12B, and is a ternary output signal SB and RAM 21.
The pass flag SF is generated based on the comparison data DR of A. For example, the pulse detection circuit 22C is npn
Type bipolar transistors (hereinafter referred to as tenth to seventeenth transistors) Q10 to Q17, resistance elements R6 to R9, and a diode D.

For example, tenth to thirteenth transistors Q10 to
A differential pair transistor circuit composed of Q13 and a resistance element R7, and fourteenth and fifteenth transistors Q14, Q15 and a resistance element R
By the second constant current source Io2 composed of 8, the ternary output signal SB input to the circle B point and the RAM supplied to the circle D point
The pass flag SF is generated based on the comparison data DR of 21A, and the pass flag SF is output to the outside from the output circuit including the seventeenth transistor Q17 and the resistance element R9 (see a circle F point). In the embodiment of the present invention, the test clock signal TCK
When the pulse width of is larger than the access time TAA, the pass flag SF is generated, and it has an extremely short pulse width.

Thus, R according to the embodiment of the present invention
According to the AM built-in gate array, as shown in FIGS. 3 and 4, the pass flag detection circuit 22 is provided, and the logical output value of the test data TOUT and the test clock signal TCK of the RAM 21A and the logical output value and the comparison data of the RAM 21A. The pass flag S from the pass flag detection circuit 22 based on DR
F is generated.

Therefore, roughly, the test clock signal TCK having a pulse width indicating the access time TAA of the RAM 21A of the RAM built-in gate array 13 is accurately generated, and the pass flag detection circuit 22 and the input latch circuit 21C are further generated.
By combining with and detecting the pass flag SF, the access time TAA having a small absolute value in the RAM 21A can be accurately measured regardless of the peripheral circuit of the RAM 21A.

That is, in FIG. 5, the 3-value output circuit 22B of the path flag detection circuit 22 causes the 8-bit RAM to operate.
When the ternary output signal SB is output based on the read data DOUT of 21A and the test clock signal TCK, a pass flag SF is generated from the pulse detection circuit 22B based on the ternary output signal SB and the comparison data DR of the RAM 21A. To be done.

For example, when the pulse width of the test clock signal TCK is larger than the access time TAA, the pass flag SF is generated from the ternary output circuit 22B so that the pulse width of the clock signal TCK is almost the access time TAA of the RAM 21A. And the pass flag SF
By detecting the generation boundary point of the test signal externally or internally, the delay time T1 of the test data DIN, the test clock signal TCK and the test output data TOUT by the test input wiring and the test clock wiring reaching the peripheral circuit of the RAM 21A as in the conventional example. ，
T2 will not directly intervene in the true access time TAA of RAM 21A.

As a result, the influence of the delay times T1 and T2 as in the conventional example is affected by the access time TAA of the RAM 21A, which is becoming faster due to the higher functionality and higher performance of the semiconductor integrated circuit device. It will not be done and it will be possible to make a true evaluation of it.

In particular, the access time T of the internal RAM 21A
Even in a semiconductor integrated circuit device in which AA is less than 1 [ns], it is more true than the method in which the test data DIN and the test clock signal TCK are externally supplied and the measurement is performed based on the test output data TOUT as in the conventional example. Access time TA
It becomes possible to measure A accurately.

Next, a method of testing the semiconductor integrated circuit device according to the embodiment of the present invention will be described while supplementing the operation of the path flag detection circuit of the RAM built-in gate array 23.

FIG. 6 is a test flowchart for the RAM built-in gate array according to each embodiment of the present invention, and FIG. 8 is a supplementary explanatory view of the test flowchart. For example, as shown in FIG. 3, the RAM 21A of the RAM built-in gate array (hereinafter referred to as the gate array under test) 23.
In order to measure the access time TAA of the gate array 23 in FIG.
Connect with SI tester 24. At this time, as shown in FIG. 7, the test input terminal T1, the test clock input terminal T2, the test mode terminal T3, and the comparison data input terminal T4 of the gate array under test 23 are the test signal output parts out1 to out4 of the LSI tester 24. And the pass flag detection terminal T5 and the test output terminal T6 of the gate array 23 under test.
Are connected to the test signal input units in1 and in2 of the LSI tester 24.

Next, at step P2, the gate array 23 to be tested is supplied with the test mode signal T / A and the test clock signal TC.
K and test data TIN are supplied and the mode signal T / A is selected. At this time, each of the signals T / A, from the test signal output parts out1 to out4 of the LSI tester 24 to the input side peripheral circuit 21A of the gate array under test 23 and the path flag detection circuit 22.
TCK and TIN are output. For example, the test mode signal T
/ A is set to "H" level to put the RAM 21A in the test mode. As a result, the RAM 21A is separated from the gate array 21.

Then, in step P3, the monitoring process of the path flag SF returned from the path flag detection circuit 22 is started. At this time, the pass flag detection circuit 22 uses the RAM 21A.
Test output data TOUT and the test clock signal TCK logic output value and the logic output value and the comparison data D of the RAM 21A.
The pass flag SF is generated based on R and.

Then, in step P4, the pulse width of the test clock signal TCK is varied. At this time, the LSI tester 2
The pulse width of the test clock signal TCK of 4 is automatically adjusted. Next, in step P5, the boundary point is confirmed depending on whether or not the pass flag SF is detected. At this time, if the pass flag SF is detected (YES), step P4
Then, for example, the pulse width of the test clock signal TCK is reduced. When the pass flag SF reaches the boundary point where it is no longer detected (NO), the process proceeds to step P6.

If the pass flag SF reaches the boundary point where it is no longer detected (NO), the process of reducing the pulse width of the test clock signal TCK is stopped and step P6 is performed.
Then, the access time TAA of the RAM 21A is measured. Here, the true access time TAA means the time from when the test clock signal TCK is input to the RAM 21A until the read data (test output data DOUT) is output to the normal output port.

Thus, by measuring the pulse width of the test clock signal TCK reaching the boundary point where the pass flag SF is no longer detected, the test data TIN is input and latched in synchronization with the trailing edge of the test clock signal TCK. , It is possible to measure the access time TAA of the RAM 21A which outputs the read data DOUT in synchronization with its rising.

As described above, according to the method of testing a gate array with built-in RAM according to each of the embodiments of the present invention, the RAM is processed in step P2 as shown in the processing flowchart of FIG.
When the test clock signal TCK and the test data TIN are supplied to the built-in gate array 23, the pass flag SF returned from the pass flag detection circuit 22 is monitored in step P3, and then the RAM 21A is accessed based on the pass flag SF in step P6. The time TAA is measured.

For example, when the pulse width of the test clock signal TCK is larger than the access time TAA in step P3, the test output data TOUT of the RAM 21A and the logic output value of the test clock signal TCK, and the logic output value and the RAM 21.
The path flag SF generated based on the comparison data DR of A is detected. At this time, in step P4, the pulse width of the test clock signal TCK is controlled to be reduced based on the pass flag SF returned from the RAM built-in gate array 23.

For this reason, the RA which inputs and latches the test data TIN in synchronization with the falling of the test clock signal TCK and outputs the read data DOUT in synchronization with the rising thereof.
Pass flag SF for M21A access time TAA
By properly calibrating the ternary output signal SB of the ternary output circuit 22B based on the above, it becomes possible to measure it accurately.

In this way, the pass flag detection circuit 22 which supplies the test clock signal TCK having a pulse width indicating the access time TAA of the RAM built-in gate array 23 and generates the pass flag SF based on the pulse width is constructed. By observing the pulse width of the test clock signal TCK, the true access time TAA can be accurately measured regardless of the influence of the peripheral circuits.

(2) Description of Second Embodiment FIG. 8A is a block diagram of a path flag detection circuit of a RAM built-in gate array according to a second embodiment of the present invention. FIG. The respective operation explanatory diagrams of the pass flag detection circuit are shown.

The difference from the first embodiment is that in the second embodiment, a pulse width expansion circuit 22D is connected after the pulse detection circuit 22A, and the access time TAA of the RAM 21A is changed.
For, the pulse width of the internal clock signal CLK is measured.

That is, the pulse width expansion circuit 22D is an example of the signal widening circuit 12C, and widens the pulse width of the pass flag SF. For example, the pulse width expansion circuit 22D shown in FIG. 8A has the first to third delay gates DL1.
~ DL3 and a 4-input OR circuit OR, and a pass flag S
F is widened and the pass flag SFw having a long pulse width is output.

The input circuit 22A and the ternary output circuit 22B output the ternary output signal SB based on the read data DOUT output from the RAM 21A and the internal clock signal CLK controlled accurately. In addition, pulse detection circuit
22C generates a pass flag SF based on the ternary output signal SB and the comparison data DR, as in the first embodiment.

In this way, according to the pass flag detection circuit of the RAM built-in gate array of the second embodiment of the present invention, as shown in FIG. 8A, the pass flag SF of the pass flag SF is provided after the pulse detection circuit 22C. A pulse width expansion circuit 22D for expanding the pulse width is connected, the internal clock signal CLK is supplied to the RAM 21A, and the pulse width of the internal clock signal CLK is controlled based on the pass flag SF.

For example, roughly, the gate array 2 with built-in RAM
The internal clock signal CLK having a pulse width indicating the access time TAA of 3 is supplied, and based on this, the pass flag SF
By observing the pulse width of the internal clock signal CLK based on the path flag SF whose pulse width has been widened, the true access time can be obtained regardless of the influence of the peripheral circuits. It becomes possible to measure TAA accurately.

Therefore, the pass flag S having a short pulse width is
Even if the LSI tester does not have the ability to detect F, its pass flag SF is widened by the pulse width expansion circuit 22D, so that the test clock signal TCK rises between the input latch and the output latch as in the conventional example. Compared to the method of measuring the true access time TAA by catching the falling edge, the access time TAA can be accurately measured by a low-precision LSI tester without depending on the measurement accuracy of the output latch sensitivity and operation speed. It becomes possible to measure.

Thus, as in the first embodiment, RA
Access time T of RAM 21A such as M built-in gate array
The detailed evaluation of AA can be performed in a measurement system with low accuracy, and the ability of the access time TAA, which is an important parameter in RAM21A evaluation, can be accurately recognized. Further, it is possible to improve the versatility of the test device for the semiconductor integrated circuit device with a built-in RAM.

[0081]

As described above, according to the semiconductor integrated circuit device of the present invention, the read data of the memory circuit element and the logical output value of the operation clock signal, and the logical output value and the expected output value of the memory circuit element. Based on the above, a control timing signal is generated from the test circuit.

Therefore, roughly, an operation clock such as a test clock signal or an internal clock signal having a pulse width indicating the access time of the test object is accurately generated, and further, the test circuit and the input latch circuit are combined, By detecting the control timing signal, it is possible to accurately measure the access time having a small absolute value of the memory circuit element, regardless of the peripheral circuit of the memory circuit element.

Further, according to another semiconductor integrated circuit device of the present invention, a signal widening circuit for widening the pulse width of the control timing signal is connected to the subsequent stage of the signal generating circuit. For this reason, the control timing signal having a short pulse width is widened by the signal widening circuit, so that the measurement accuracy of the output latch sensitivity, operating speed, etc. does not depend on the measurement accuracy of the conventional method. , With a low-precision measuring device,
It is possible to measure the access time.

According to the semiconductor integrated circuit device testing method of the present invention, when the test clock signal and the test data are supplied to the test object, the control timing signal returned from the test object is monitored and processed. Then, the access time of the memory circuit element is measured based on the control timing signal.

Therefore, the access timing of the memory circuit element that inputs and latches the test data in synchronization with the falling edge of the test clock signal or the internal clock signal and outputs the read data in synchronization with the rising edge thereof is used as the control timing signal. By observing the pulse width of the operation clock signal based on this, the true access time can be accurately measured regardless of the influence of the peripheral circuits.

Further, the detailed evaluation can be carried out even in a measurement system having low accuracy, and the ability of access time, which is an important parameter in the evaluation of the memory circuit element, can be accurately recognized. In particular, even in the semiconductor integrated circuit device in which the access time of the built-in memory circuit element is less than 1 [ns], the true access time can be measured more accurately than the conventional measuring method.

As a result, it becomes possible to improve the reliability of the performance evaluation of the gate array, the standard cell, etc. having the built-in semiconductor memory circuit, the provision of a highly reliable semiconductor integrated circuit device, and the versatility of the test device. It greatly contributes to.

[Brief description of drawings]

FIG. 1 is a principle diagram of a semiconductor integrated circuit device according to the present invention.

FIG. 2 is a principle diagram of a method for testing a semiconductor integrated circuit device according to the present invention.

FIG. 3 is an overall configuration diagram of a RAM built-in gate array according to a first embodiment of the present invention.

FIG. 4 is a configuration diagram of a path flag detection circuit according to the first embodiment of the present invention.

FIG. 5 is an operation explanatory diagram of the path flag detection circuit according to the first embodiment of the present invention.

FIG. 6 is a test flowchart of a RAM-embedded gate array according to each embodiment of the present invention.

FIG. 7 is a supplementary explanatory diagram of a test flowchart according to each embodiment of the present invention.

FIG. 8 is a configuration diagram of a path flag detection circuit according to a second embodiment of the present invention.

FIG. 9 is an explanatory diagram of a method for testing a RAM-embedded gate array according to a conventional example.

[Explanation of symbols]

 11 ... Internal integrated circuit, 12 ... Pass flag detection circuit, 12A ... Signal output circuit, 12B ... Signal generation circuit, 12C ... Signal widening circuit, M ... Memory circuit element, TCK ... Test clock signal, CLK ... Internal clock signal, CK ... Operation clock signal, TIN ... Test data, TOUT ... Test output data, DOUT ... Read data, T / A ... Test mode signal, TAA ... True access time, SB ... Tri-level output signal, DR ... Expected output value (comparative data) ), SF ... Control timing signal (path flag).

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 21/82 27/04 T 8427-4M

Claims (7)

[Claims] 1. A semiconductor integrated circuit device incorporating a test circuit (12) for assisting a test of an internal integrated circuit (11) including a memory circuit element (M), wherein the test circuit (12) is a memory circuit. Read data of element (M) (DOUT
) And the logical output value of the operation clock signal (CK) and the expected output value (D) of the logical output value and the memory circuit element (M).
R) is used to generate a control timing signal (SF). 2. The semiconductor integrated circuit device according to claim 1, wherein the test circuit (12) outputs a ternary value based on read data (DOUT) of the memory circuit element (M) and an operation clock signal (CK). A signal output circuit (12A) that outputs a signal (SB), a control timing signal (SF) is generated based on the ternary output signal (SB) and the expected output value (DR) of the memory circuit element (M). A semiconductor integrated circuit device comprising a signal generating circuit (12B). 3. The semiconductor integrated circuit device according to claim 2, wherein a signal widening circuit (12C) for widening the pulse width of the control timing signal (SF) is connected after the signal generating circuit (12A). A semiconductor integrated circuit device. 4. A method for testing an internal integrated circuit (11) including at least a memory circuit element (M) to be tested (13), wherein a test clock signal (TCK) and a test clock signal (TCK) are applied to the tested (13). The test data (TIN) is supplied, the control timing signal (SF) returned from the device under test (13) is monitored, and the storage circuit element (M) is monitored based on the control timing signal (SF). A method for testing a semiconductor integrated circuit device, which comprises measuring an access time (TAA). 5. The method for testing a semiconductor integrated circuit device according to claim 4, wherein the control timing signal (SF) is
Generated based on the logical output value of the test output data (TOUT) of the memory circuit element (M) and the test clock signal (TCK), and the logical output value and the expected output value (DR) of the memory circuit element (M). A method for testing a semiconductor integrated circuit device, comprising: 6. The method for testing a semiconductor integrated circuit device according to claim 4, wherein a control timing signal fed back from the device under test (13) at the time of measuring the access time (TAA) of the memory circuit element (M). A test method for a semiconductor integrated circuit device, comprising controlling a pulse width of a test clock signal (TCK) based on (SF). 7. The method of testing a semiconductor integrated circuit device according to claim 4, wherein the memory circuit element (M) is used when measuring an access time (TAA) of the memory circuit element (M).
To the control timing signal (S) by supplying the internal clock signal (CLK) to the pulse width of the internal clock signal (CLK).
F) to control the internal clock signal (CL
A method for testing a semiconductor integrated circuit device, which comprises measuring the pulse width of K).