CN107068198A - A kind of SET annealing optimization circuit and method for phase-change memory cell testing current - Google Patents
A kind of SET annealing optimization circuit and method for phase-change memory cell testing current Download PDFInfo
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- CN107068198A CN107068198A CN201710256187.5A CN201710256187A CN107068198A CN 107068198 A CN107068198 A CN 107068198A CN 201710256187 A CN201710256187 A CN 201710256187A CN 107068198 A CN107068198 A CN 107068198A
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Abstract
The present invention provides a kind of SET annealing optimization circuit and method for phase-change memory cell testing current, including：Produce the pulse current source generating circuit of first, second pulse current source；The electric capacity that the trailing edge of control output driving current slowly declines；Export the load phase change resistor of the output driving current；Control the switching tube of capacitor charge and discharge；And the phase inverter anti-phase to pulse driving voltage.First, second pulse current source is produced based on negative DC current and pulse driving voltage；When pulse driving voltage is high level, the first pulse current source charges for electric capacity；Second pulse current source flows through load phase change resistor, is used as the high level signal of output driving current；When pulse voltage is low level, electric capacity is powered for load phase change resistor, the trailing edge of output driving current is slowly declined.The present invention utilizes RC discharge effects, and the trailing edge of control output driving current is slowly declined, can acted under the parameter of optimal SET operation with this each memory cell.
Description
Technical field
The present invention relates to microelectronic, more particularly to a kind of SET for phase-change memory cell testing current anneals
Optimize circuit and method.
Background technology
The basic functional principle of phase transition storage is phase-change material using based on chalcogenide compound as storage medium,
Phase-change devices unit two ends apply different pulses, are converted by phase-change material between amorphous state and crystalline state and realize that data are deposited
Storage.Phase-change material shows as characteristic of semiconductor in amorphous state, and its resistance shows as high resistant；Semimetal is shown as in crystalline state special
Property, its resistance is low-resistance.Amorphous state is commonly defined as " RESET " state, and the logical value of correspondence memory cell is " 1 ", corresponding behaviour
It is used as RESET operation；Crystalline state is defined as " SET " state, and the logical value of correspondence memory cell is " 0 ", and corresponding operation is SET behaviour
Make.Resistance difference between SET and RESET state can reach 2~3 orders of magnitude.
The basic operation of phase transition storage has three kinds, respectively including RESET operation, SET operation outside and READ operation.
RESET operation pulse is short and strong pulse, and the pulse converts electrical energy into heat energy and promotes the temperature of zone of action material to rise,
When temperature is increased to more than material melt temp, by rapid quenching processes, ultimately result in the long-range order of material crystalline state by
Destruction, realizes material from crystalline state to amorphous transformation.The trailing edge steeper of general RESET pulse, the purpose so done
It is to ensure the formation of material non crystalline structure.It is different from RESET operation, SET operation pulse medium pulse of intensity to be long,
The pulse is heated by converting electric energy into heat to non-crystalline material, material temperature is increased to more than crystallization temperature, melting temperature
Hereinafter, material crystalline is finally promoted.SET pulse width is necessarily more than the crystallization sensitive time, so just can ensure that material enough
Sufficient crystallising in time.
In the conceptual phase of phase transition storage, the test of phase-change memory cell contributes to some in labor array specific
The performance of unit, and SET current source pulse optimization circuit is to the change of research SET process voltages, phase-change mechanism in unit testing
It is most important with lifting speed.At present, SET annealing optimization circuit is widely used that the one of a kind of stepped reduction of trailing edge
Kind of programming pulse, circuit in this way optimizes SET annealing operations to a certain extent, but because its steps is led
Cause, which can not meet each memory cell, can act under its optimal SET operation parameter, therefore possess smooth trailing edge
SET annealing optimization circuits are significant.
The content of the invention
The shortcoming of prior art, is used for phase-change memory cell electricity it is an object of the invention to provide one kind in view of the above
The SET annealing optimization circuits and method of current test, for solving its output current of SET annealing optimization circuit because in the prior art
It is steps to cause that the problem of each memory cell is acted under optimal SET operation parameter is met.
In order to achieve the above objects and other related objects, the present invention provides a kind of for phase-change memory cell testing current
SET annealing optimization circuits, the SET annealing optimization circuit at least includes：
Pulse current source generating circuit, receives negative DC current and pulse driving voltage, for producing two identicals
Pulse current source, respectively the first pulse current source and the second pulse current source；
Electric capacity, one end connects first pulse current source, other end ground connection, the decline for controlling output driving current
Along slow decline；
Phase change resistor is loaded, one end connects second pulse current source, other end ground connection, is driven for exporting the output
Streaming current；
Between switching tube, the output end for being connected to first pulse current source and second pulse current source, control
The inverted signal of the end connection pulse driving voltage, the discharge and recharge for controlling the electric capacity.
Phase inverter, is connected between the pulse driving voltage and the control end of the switching tube, for anti-phase described
Pulse driving voltage controls the turn-on and turn-off of the switching tube.
Preferably, the load phase change resistor is the cell resistance in phase transition storage.
Preferably, the switching tube is N-type MOS device, and its source is connected to second pulse current source and born with described
Between load phase change resistor, drain terminal is connected between first pulse current source and the electric capacity, grid end connects the pulse and driven
The inverted signal of dynamic voltage；When the pulse driving voltage is high level, the electric capacity is in charged state, when the simple venation
The electric capacity is in discharge condition when rushing driving voltage for low level, is that the load phase change resistor is powered.
In order to achieve the above objects and other related objects, the present invention provides a kind of for phase-change memory cell testing current
SET annealing optimization methods, the SET annealing optimization method at least includes：
Two identical pulse current sources are produced based on negative DC current and pulse driving voltage, the first pulse electricity is designated as
The pulse width of stream source and the second pulse current source, first pulse current source and second pulse current source and the list
The pulse width of pulsed driving voltage is identical；
When the pulse driving voltage is high level, first pulse current source charges for electric capacity；Described second
Pulse current source flows through load phase change resistor, is used as the high level signal of output driving current；
When the pulse driving voltage is low level, the electric capacity is powered for the load phase change resistor, is made described
The trailing edge of output driving current slowly declines.
Preferably, in order to ensure output pulse current source stability, pass through two independent identicals bear direct current
Stream produces two independent identical pulse current sources in the presence of the pulse driving voltage；In pulse driving
First pulse current source described in during voltage high level and second pulse current source are high level, and electricity is driven in the pulse
The first pulse current source and second pulse current source are low level described in when forcing down level.
Preferably, the output driving current output is determined by setting the pulse width of the pulse driving voltage
The time of high level and the charging interval of the electric capacity.
Preferably, the output driving current is determined by setting the parameter of the load phase change resistor and the electric capacity
Trailing edge decrease speed.
It is highly preferred that in slow decline, the output driving current meets following relational expression：
Wherein, U is electric capacity both end voltage, and R is the resistance of the load phase change resistor, and C is the capacity of the electric capacity, and t is
Institute
The time of output driving current decline is stated, e is natural constant.
As described above, the SET annealing optimization circuit and method for phase-change memory cell testing current of the present invention, has
Following beneficial effect：
The SET annealing optimization circuit and method for phase-change memory cell testing current of the present invention utilizes RC electric discharge effects
Should, the pulse width and trailing edge decrease speed of output driving current are controlled by the setting of device parameters, phase transformation is ensured with this
Material sufficient crystallising in enough time in memory SET operation, and with a process slowly annealed, make each storage single
Member can be acted under the parameter of optimal SET operation.
Brief description of the drawings
Fig. 1 is shown as the SET annealing optimization circuit diagrams for phase-change memory cell testing current of the present invention.
The SET annealing optimization circuits for phase-change memory cell testing current that Fig. 2 is shown as the present invention work in electric capacity
Equivalent schematic under charged state.
Fig. 3 is shown as the principle schematic that the electric capacity of the present invention is worked under charged state.
The SET annealing optimization circuits for phase-change memory cell testing current that Fig. 4 is shown as the present invention work in electric capacity
Equivalent schematic under discharge condition.
Fig. 5 is shown as the voltage-time curve schematic diagram during electric capacity charging of the present invention.
Fig. 6 is shown as the current versus time curve schematic diagram during electric capacity electric discharge of the present invention.
Fig. 7 is shown as the waveform diagram of the output driving current of the present invention.
Component label instructions
1 pulse current source generating circuit
2 phase inverters
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through specific realities different in addition
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
Refer to Fig. 1~Fig. 7.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, then in schema only display with relevant component in the present invention rather than according to package count during actual implement
Mesh, shape and size are drawn, and kenel, quantity and the ratio of each component can be a kind of random change during its actual implementation, and its
Assembly layout kenel may also be increasingly complex.
As shown in figure 1, the present invention provides a kind of SET annealing optimization circuits for phase-change memory cell testing current, institute
Stating SET annealing optimization circuits at least includes：
Pulse current source generating circuit 1, electric capacity C, load phase change resistor R, switching tube Q and phase inverter 2.
As shown in figure 1, the pulse current source generating circuit 1 receives negative DC current and pulse driving voltage Vdata,
For producing two identical pulse current sources, respectively the first pulse current source Idata1 and the second pulse current source
Idata2。
Specifically, as shown in figure 1, bearing DC current there is provided two identicals in the present embodiment, respectively first is negative straight
Flow electric current Iin1 and second negative DC current Iin2, the first negative DC current Iin1 and the second negative DC current Iin2
The first pulse current source Idata1 and second pulse current source are obtained based on the pulse driving voltage Vdata
Idata2.One input current one output current of correspondence, with the stability that this ensures to export pulse current source, in actual use
In, two identical pulse current sources can be obtained by a negative DC current, be not limited with the present embodiment.The pulse drives
Dynamic voltage Vdata controls unlatching and the pass of the first pulse current source Idata1 and the second pulse current source Idata2
Close, to form pulse signal, when the pulse driving voltage Vdata is high level, first pulse current source
Idata1 and the second pulse current source Idata2 is opened；It is described when the pulse driving voltage Vdata is low level
First pulse current source Idata1 and the second pulse current source Idata2 is closed, and then determines first pulse current source
Idata1 and the second pulse current source Idata2 pulse width.The first pulse current source Idata1 and described second
Pulse current source Idata2 pulse width is identical with the pulse width of the pulse driving voltage Vdata.By setting
Pulse driving voltage Vdata pulse width is stated to obtain the pulse width of default pulse current source, in the present embodiment,
The pulse driving voltage Vdata is nanosecond voltage pulse, and it controls frequency setting to be 10MHz, and pulse width is
200ns。
Specifically, the first pulse current source Idata1 and the second pulse current source Idata2 size with it is described
First negative DC current Iin1 is relevant with the described second negative DC current Iin2 size, can be preset by the setting of ratio
Output current value, in the present embodiment, the first pulse current source Idata1 and the second pulse current source Idata2
Size and the described first negative DC current Iin1 and second negative DC current Iin2 size ratio be 4：1.
Specifically, as shown in figure 1, the pulse current source generating circuit 1 connects supply voltage Vdd, the supply voltage
Vdd is set as 2.6V~6.5V, in the present embodiment, and the supply voltage Vdd is set as 5V.The pulse current source produces electricity
Road 1, which is received, enables signal En, and in the present embodiment, the enable signal En works in high level, and high level is set as described
Supply voltage Vdd.The pulse current source generating circuit 1 is also connected with reference ground Gnd.
As shown in figure 1, one end of the electric capacity C connects the first pulse current source Idata1, other end ground connection Gnd,
For controlling the trailing edge of output driving current slowly to decline.
As shown in figure 1, one end of the load phase change resistor R connects the second pulse current source Idata2, the other end
Gnd is grounded, for exporting the output driving current.
Specifically, the load phase change resistor R is the cell resistance in phase transition storage.
As shown in figure 1, the switching tube Q is connected to the first pulse current source Idata1 and second pulse current
Between source Idata2 output end, the discharge and recharge for controlling the electric capacity C.The input of the phase inverter 2 connects the list
Pulsed driving voltage Vdata, output end connects the control end of the switching tube Q.
Specifically, in the present embodiment, the switching tube Q is N-type MOS device, and the source of the switching tube Q is connected to institute
State between the second pulse current source Idata2 and the load phase change resistor R, drain terminal is connected to first pulse current source
Between Idata1 and the electric capacity C, grid end connect the output end of the phase inverter 2.When the pulse driving voltage Vdata is
During high level, the switching tube Q shut-offs；When the pulse driving voltage Vdata is low level, the switching tube Q conductings.
The type of the switching tube Q and the polarity of control signal are not limited, and p-type MOS device may be selected, and are turned off when control end is high level
The switching tube Q, turns on the switching tube Q, other kinds of device passes through corresponding control signal when control end is low level
Realize that the open and close of switch are applied to the present invention, be not limited with the present embodiment.
As shown in Figure 1 to 4, the present invention provides a kind of SET annealing optimization side for phase-change memory cell testing current
Method, the SET annealing optimization method at least includes：
Two identical pulse current sources are produced based on negative DC current and pulse driving voltage, the first pulse electricity is designated as
The pulse width of stream source and the second pulse current source, first pulse current source and second pulse current source and the list
The pulse width of pulsed driving voltage is identical；
When the pulse driving voltage is high level, first pulse current source charges for electric capacity；Described second
Pulse current source flows through load phase change resistor, is used as the high level signal of output driving current；
When the pulse driving voltage is low level, the electric capacity is powered for the load phase change resistor, is made described
The trailing edge of output driving current slowly declines.
Specifically, as shown in figure 1, in the present embodiment, in order to ensure the stability that exports pulse current source, there is provided first
Negative DC current Iin1 and second negative DC current Iin2, the first negative DC current Iin1 and the second negative DC current
Iin2 produces the first pulse current source Idata1 and the second pulse current source Idata2, institute by pulse driving voltage Vdata
State pulse driving voltage Vdata and control the first pulse current source Idata1's and the second pulse current source Idata2
Be switched on and off, the first pulse current source Idata1 and the second pulse current source Idata2 pulse width with it is described
Pulse driving voltage Vdata pulse width is identical；The first pulse current source Idata1 and second pulse current
Source Idata2 is constant current signal, its size and the described first negative DC current Iin1 and the second negative direct current in high level
Flow Iin2 proportional, default electric current source size can be obtained according to the setting of ratio.
Specifically, as shown in Fig. 2 in the present embodiment, when the pulse driving voltage Vdata is high level, institute
The first pulse current source Idata1 and the second pulse current source Idata2 is stated for high level；The switching tube Q shut-offs.It is described
First pulse current source Idata1 and the second pulse current source Idata2 flow separately through the electricity equivalent to constant dc current stream
Hold the C and load phase change resistor R.The second pulse current source Idata2 is that the load phase change resistor R powers, and is used as institute
The high level part of output driving current is stated, the pulse width of the pulse driving voltage Vdata determines the output driving
Electric current exports the time of high level.As shown in figure 3, the first pulse current source Idata1 is equivalent to a constant-current source, it is described
Electric capacity C charges, and the pulse width of the pulse driving voltage Vdata determines the charging interval of the electric capacity C.
Specifically, as shown in figure 4, in the present embodiment, when the pulse driving voltage Vdata is low level, institute
The first pulse current source Idata1 and the second pulse current source Idata2 shut-offs are stated, low level is output as；The switching tube Q
Conducting.Powered as shown in figure 4, the electric capacity C is the load phase change resistor R so that flow through the electricity of the load phase change resistor R
Stream is slow to be declined.
The present invention can obtain being applied to PCRAM devices by the setting of device parameters and Current amplifier (or reducing) ratio
The output driving current of the test analysis of unit, size of current up to more than 10mA, the pulsewidth as little as 100ns of output.
As the example of the present invention, as shown in figure 1, as the described first negative DC current Iin1 and described second negative straight
The size of current for flowing electric current Iin2 is -0.1mA, described when the pulse driving voltage Vdata is+5V and pulsewidth is 200ns
First pulse current source Idata1 and the second pulse current source Idata2 size of current are+0.4mA and pulse width
For 200ns.Assuming that the load phase change resistor is 1K Ω.
As shown in figure 3, the first pulse current source Idata1 gives the electric capacity C charging stages.The characteristic of electric capacity can use
Expression formula Q=CU (1) represents, wherein, Q is that the electricity of the electric capacity, C are that the capacity of the electric capacity, U are the electric capacity two ends
Voltage.First pulse current source Idata1 perseverance is 0.4mA, and Δ U=Δ Q/C=(Idata1/ C) × t (2), wherein, Δ U
For the variable quantity of the electric capacity both end voltage, Δ Q is the variable quantity of the electric capacity electricity, and t is the time.
Therefore, expression formula u=U is obtained0+ Δ U=U0+(Idata1/ C) × t (3), wherein, u is the electric capacity both end voltage
Instantaneous value, U0For the initial value of the electric capacity both end voltage, the curve map of formula (3) is illustrated in figure 5.As shown in figure 1, at this
In embodiment, the output driving current exports the time t1=200ns, Idata1=0.4mA, U of high level0=0, but still
Need to know the value of both end voltage U when the electric capacity is full of, can just calculate the capacity of the electric capacity C.
As shown in figure 4, when reaching 200ns between when charging, the first pulse current source Idata1 and described
Two pulse current source Idata2 are turned off, and now switch the conducting of Q pipes, are discharged by the electric capacity C to the load phase change resistor R.Root
According to the principle of resistance capacitance first order zero input response, the expression formula of current discharge can obtainIts
In, U is the electric capacity both end voltage, and R is the resistance of the load phase change resistor, and C is the capacity of the electric capacity, and t is described defeated
Go out the time of driving current decline, e is natural constant.Because current status will reach unanimously after discharge and recharge, electric discharge electricity
Original state U/R=0.4mA, the R=1K Ω of stream, it can thus be concluded that U=0.4V.Known U=0.4V, can try to achieve C=by formula (3)
200Pf.The trailing edge of the output driving current is determined by setting the parameter of the load phase change resistor and the electric capacity
Decrease speed, design parameter set, is not limited with the present embodiment according to actual needs.
The curve map of formula (4) is illustrated in figure 6, is theoretically seen, zero can be just decayed to by infinite long-time U/R
Value, but it is generally acknowledged that it is 0 to be discharged by 3RC~5RC times in engineering, therefore, in the present embodiment, set discharge time t2 ≈
4RC=800ns.It can thus be concluded that the pulse width of the output driving current is t1+t2 ≈ 1000ns, the output driving current
Waveform it is as shown in Figure 7.
The SET annealing optimization circuit and method for phase-change memory cell testing current of the present invention utilizes RC electric discharge effects
Should, the pulse width and trailing edge decrease speed of output driving current are controlled by the setting of device parameters, phase transformation is ensured with this
Material sufficient crystallising in enough time in memory SET operation, and with a process slowly annealed, make each storage single
Member can be acted under the parameter of optimal SET operation.
In summary, the present invention provides a kind of for the SET annealing optimization circuit of phase-change memory cell testing current and side
Method, including：Negative DC current and pulse driving voltage are received, and produces two identical pulse current sources, the first pulse electricity
Stream source and the pulse current source generating circuit of the second pulse current source；The electricity that the trailing edge of control output driving current slowly declines
Hold；Export the load phase change resistor of the output driving current；Control the switching tube of the discharge and recharge of electric capacity；And pulse is driven
The phase inverter of voltage inversion.Two identical pulse current sources are produced based on negative DC current and pulse driving voltage, are designated as
First pulse current source and the second pulse current source；When pulse driving voltage is high level, the first pulse current source is electricity
Capacity charge；Second pulse current source flows through load phase change resistor, is used as the high level signal of output driving current；Driven in pulse
When dynamic voltage is low level, electric capacity is powered for load phase change resistor, the trailing edge of output driving current is slowly declined.The present invention
Using RC discharge effects, the pulse width and trailing edge decrease speed of output driving current are controlled by the setting of device parameters,
Material sufficient crystallising in enough time in phase transition storage SET operation is ensured with this, and with a process slowly annealed,
Each memory cell is set to act under the parameter of optimal SET operation.So, the present invention effectively overcomes of the prior art
Various shortcoming and have high industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (8)
1. a kind of SET annealing optimization circuits for phase-change memory cell testing current, it is characterised in that the SET annealing is excellent
Changing circuit at least includes：
Pulse current source generating circuit, receives negative DC current and pulse driving voltage, for producing two identical pulses
Current source, respectively the first pulse current source and the second pulse current source；
Electric capacity, one end connects first pulse current source, other end ground connection, for controlling the trailing edge of output driving current to delay
It is slow to decline；
Phase change resistor is loaded, one end connects second pulse current source, other end ground connection, for exporting the output driving electricity
Stream；
Between switching tube, the output end for being connected to first pulse current source and second pulse current source, control end connects
The inverted signal of the pulse driving voltage is connect, the discharge and recharge for controlling the electric capacity.
Phase inverter, is connected between the pulse driving voltage and the control end of the switching tube, for the anti-phase simple venation
Driving voltage is rushed to control the turn-on and turn-off of the switching tube.
2. SET annealing optimization circuit according to claim 1, it is characterised in that：The load phase change resistor is deposited for phase transformation
Cell resistance in reservoir.
3. SET annealing optimization circuit according to claim 1, it is characterised in that：The switching tube is N-type MOS device, its
Source is connected between second pulse current source and the load phase change resistor, drain terminal connects first pulse current source
Between the electric capacity, grid end be connected the inverted signal of the pulse driving voltage；When the pulse driving voltage is high electricity
Usually the electric capacity is in charged state, and when the pulse driving voltage is low level, the electric capacity is in discharge condition,
Powered for the load phase change resistor.
The optimization method 4. a kind of SET for phase-change memory cell testing current anneals, it is characterised in that the SET annealing is excellent
Change method at least includes：
Two identical pulse current sources are produced based on negative DC current and pulse driving voltage, the first pulse current source is designated as
With the second pulse current source, pulse width and the pulse of first pulse current source and second pulse current source
The pulse width of driving voltage is identical；
When the pulse driving voltage is high level, first pulse current source charges for electric capacity；Second pulse
Current source flows through load phase change resistor, is used as the high level signal of output driving current；
When the pulse driving voltage is low level, the electric capacity is powered for the load phase change resistor, makes the output
The trailing edge of driving current slowly declines.
The optimization method 5. SET according to claim 4 anneals, it is characterised in that：In order to ensure the pulse current source of output
Stability, by two independent identicals bear DC current is produced in the presence of the pulse driving voltage two it is only
Vertical identical pulse current source；First pulse current source and described second described in the pulse driving voltage high level
Pulse current source is high level, the first pulse current source described in the pulse driving voltage low level and second arteries and veins
Current source is rushed for low level.
The optimization method 6. SET according to claim 4 anneals, it is characterised in that：By setting the pulse driving electricity
The pulse width of pressure determines the time of output driving current output high level and the charging interval of the electric capacity.
The optimization method 7. SET according to claim 4 anneals, it is characterised in that：By setting the load phase change resistor
And the parameter of the electric capacity determines the decrease speed of the trailing edge of the output driving current.
The optimization method 8. SET according to claim 7 anneals, it is characterised in that：In slow decline, the output driving
Electric current meets following relational expression：
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<mi>R</mi>
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Wherein, U is the electric capacity both end voltage, and R is the resistance of the load phase change resistor, and C is the capacity of the electric capacity, and t is
The time that the output driving current declines, e is natural constant.
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| CN107068198B (en) | 2020-03-31 |
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