CN207816459U - Delay circuit for avalanche photodide and integrated singl e photon detection circuit - Google Patents
Delay circuit for avalanche photodide and integrated singl e photon detection circuit Download PDFInfo
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- CN207816459U CN207816459U CN201820219192.9U CN201820219192U CN207816459U CN 207816459 U CN207816459 U CN 207816459U CN 201820219192 U CN201820219192 U CN 201820219192U CN 207816459 U CN207816459 U CN 207816459U
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Abstract
The utility model discloses a kind of delay circuit for avalanche photodide and integrated singl e photon detection circuits, delay circuit includes or door chip, first delay chip, select chip, circuit is selected in control, or door chip, first delay chip, selection chip is sequentially connected electrically, or an input terminal of door chip as entire delay circuit input terminal and input photon synchronizing signal, the output end of the selection chip includes two, one of output end as delay circuit, another with or another input terminal of door chip connect, it includes selection control terminal to select chip, control selects the output end of circuit to be connect with the selection control terminal.The advantages of utility model, is：First delay chip can be reused, not need multiple delay chips, which can reduce power consumption.
Description
Technical field
The utility model is related to Technique on Quantum Communication field, more particularly, to the delay circuit of avalanche photodide and
Integrated singl e photon detection circuit.
Background technology
In quantum communications field, using light as information carrier.In order to which security performance improves, the light of transmission is quantum state,
That is single photon.Singl e photon detection function module is the necessary module of this communication equipment.Existing singl e photon detection scheme is as follows：
1, first to the signal of input into line delay.
2, avalanche photodide module detection single photon needs to be operated in state appropriate.Avalanche photodide module
Including driving circuit and diode D1, wherein the driving plate for being welded with driving circuit is located at tray interior, avalanche photodide
D1 is directly welded on avalanche photodide module drive plate.Driving plate inputs external drive signal, exports the original detected
The photon signal of beginning.Driving plate is simultaneously temperature sensor module temperature signal attached on avalanche photodide module housing
Output.
3, the photon signal that avalanche signal discriminator circuit plate is exported by cable reception to avalanche photodide module, and
This signal is screened.
4, the temperature of diode D1 is detected by being adhered to the thermistor on its surface in avalanche photodide module.
5, avalanche signal discriminator circuit plate generates the driving analog signal that avalanche photodide module needs.
6, avalanche signal discriminator circuit plate acquires avalanche photodide module temperature signal, and controls electricity by PI algorithms
Power supply of the source to refrigeration module.
Existing technology major defect：
(1) in existing delay circuit, multiple delay chips of connecting are needed, both waste Material Cost, circuit in this way
Modification and debugging are also inconvenient.
(2) the shortcomings that existing integrated singl e photon detection circuit, is：A. parts are more, and supplier is different, and technique difference is big；
B. overall power is big；C. installation and debugging are complicated, complex process；D. signaling interface is more, and signal transmission path is long, and signal kinds are more,
It is lost in transmission process big.
Utility model content
Purpose of the utility model is to solve delay circuit in the prior art is of high cost, inconvenient debugging and it is based on
The problem that the parts for integrating singl e photon detection circuit are more, power consumption is big, installation and debugging are inconvenient provides a kind of for snowslide light
The delay circuit of electric diode and integrated singl e photon detection circuit.
To achieve the goals above, the technical solution of the utility model is as follows：
A kind of delay circuit for avalanche photodide, including or door chip, the first delay chip, selection chip,
Control selects that circuit or door chip, the first delay chip, selection chip is sequentially connected electrically or an input terminal of door chip is as whole
The input terminal of a delay circuit simultaneously inputs photon synchronizing signal a, and the output end of the selection chip includes two, one of to make
For the output end of delay circuit, another with or another input terminal of door chip connect, it includes selection control terminal, control to select chip
The output end of circuit is selected to be connect with the selection control terminal.
Technical solution as an optimization, first delay chip further include time delay interval control terminal.
Technical solution as an optimization, it includes counter, comparator that circuit is selected in the control, and the counter includes resetting
End, clock signal terminal, output end, reset terminal connects with input photon synchronizing signal a's or door input terminal, clock signal terminal and
The output end of first delay chip connects, and the output end of the counter and comparator input terminal connect, comparator
Another input terminal, which is used as, passes through delay chip number control terminal, is connected through delay chip time number control device, comparator
Output end is connect with the selection control terminal.
The invention also discloses it is a kind of include as described in above-mentioned any one technical solution be used for avalanche optoelectronic two
The integrated singl e photon detection circuit of the delay circuit of pole pipe, including delay circuit, avalanche photodide module, narrow pulse signal
Generation module, avalanche signal screen module, and the output end of the delay circuit connects with the input terminal of narrow pulse signal generation module
It connects, the narrow pulse signal generation module includes the first output end of signal, signal second output terminal, and avalanche signal screens module packet
It includes and screens first input end, screen the second input terminal, screen output end, the first output end of the signal and avalanche photodide
The input terminal of module connects, and the output end of avalanche photodide module is connect with first input end is screened, and signal second exports
End is connect with the second input terminal is screened, described to screen output end of the output end as entire circuit.
Technical solution as an optimization, the narrow pulse signal generation module include the second delay chip, third delay core
Piece, the first NAND gate chip, the second NAND gate chip；The output end of delay circuit connects second delay chip and described the
Three delay chips；The output end of second delay chip is connect with an input terminal of the first NAND gate chip, the first NAND gate core
The output end output gate signal c of piece；The output end of third delay chip is connect with an input terminal of the second NAND gate chip, the
The output end output of two NAND gate chips meets gate signal d.
Technical solution as an optimization, which further includes the first driving part, the second driving portion
Part, first driving part include driving first input end, the first output end of driving and drive second output terminal, and described second
Driving part includes the 4th output end of the second input terminal of driving, driving third output end and driving；The driving first input end
It is connect respectively with the output end of delay circuit with the second input terminal of driving；The first output end of the driving and second delay chip
Input terminal connects, and the driving second output terminal and another input terminal of the first NAND gate chip are directly connected to；The driving the
Three output ends are connect with the input terminal of third delay chip, and the 4th output end of the driving is another defeated with the second NAND gate chip
Enter end to be directly connected to.
Technical solution as an optimization, the avalanche photodide module include diode D1, triode Q1, resistance
R1, resistance R2, resistance R3, capacitance C1, the first level terminal, second electrical level end, the one end the resistance R1 are avalanche photodide
The input terminal of module is connect with the output end of narrow pulse signal generation module, and the other end of the resistance R1 is with triode Q1's
Base stage connects, and the first level terminal connect by resistance R2 with the collector of triode Q1, the collector of triode Q1 also with two poles
The cathode of pipe D1 connects, and the anode of diode D1 is connect by resistance R3 with second electrical level end, the anode and capacitance of diode D1
One end of C1 connects, the output end of the other end of capacitance C1 as avalanche photodide module.
Technical solution as an optimization, which further includes temperature sensor, temperature sensor
Test side is arranged in the sides diode D1.
Technical solution as an optimization, the integrated singl e photon detection circuit are also connect with optical fiber, the light of the optical fiber input
Son is radiated on diode D1.
Technical solution as an optimization, it includes triode Q2, triode Q3, triode that the avalanche signal, which screens module,
Q4, resistance R4, resistance R5, resistance R6, resistance R7, resistance R8, capacitance C2, the first power supply VCC, discriminator input terminal Vth, electricity
Stream source, the base stage of the triode Q2 are connect with the output end of the second NAND gate chip in narrow pulse signal generation module, and first
Power supply VCC is connect by resistance R4 with the collector of triode Q2, and the output end of avalanche photodide module passes through resistance R5
It is connect with the base stage of triode Q3, discriminator input terminal Vth is also connect with the base stage of triode Q3 by resistance R6, the first electricity
Source VCC is connect by resistance R7 with the collector of triode Q3, and the collector of triode Q3 is connect with one end of capacitance C2, capacitance
The other end of C2 is connect by resistance R8 with the base stage of triode Q4 as snowslide terminal count output, discriminator input terminal Vth,
First power supply VCC is directly connect with the collector of triode Q4, the emitter of triode Q2, the emitter of triode Q3, three poles
It is connected to ground behind overcurrent source after three end of the emitter connection of pipe Q4.
The utility model has the advantage of：
(1) the delay circuit main function in the utility model is to signal into line delay.Core component is the first delay
Chip.By reducing the use number of delay chip to the multiplexing of the first delay chip, overall power is reduced, increases dynamic and prolongs
When range.
(2) the utility model proposes a kind of integrated singl e photon detection modular arrangements, after integrated, remove original only
The parasitic parameter of vertical element solution modules, improves signal quality.The circuit that signal whole flow process is passed through, in physical size
On greatly shorten, the interference of outer bound pair whole device is also reduced in the case of the interference in unit area is identical, and then improve
Overall performance.Detector device subminaturization is also promoted after integrated.
(3) the utility model screens module since gate signal c will arrive avalanche signal again by avalanche photodide module
It is interior, and meet gate signal d and directly arrive in avalanche signal examination module, when not integrated, optical cable has certain length, avalanche optoelectronic
Just need impedance matching in diode (led) module, being required to connection before two input terminals of NAND gate in narrow pulse signal generation module prolongs
When chip, but it is integrated after due to apart from short, integrated gate signal c and the relative position for meeting gate signal d, which are fixations, to be counted
It calculates, it is possible to remove the delay chip before an input terminal in two input terminal of NAND gate, to reduce the number of parts
Amount reduces power consumption, increases dynamic delay range.Diode D1 and triode after integrated in avalanche photodide module it
Between direct-coupling control, so not needing impedance matching, reduce power consumption.Since the distance of intermodule reduces, delay chip section
It saves, the efficiency and rate of such whole device work can all improve.
(4) after by integrating, signaling interface quantity is reduced so that the device connect simple and convenient with external equipment.
Description of the drawings
Fig. 1 is a kind of interior layout figure of integrated singl e photon detection device of the utility model.
Fig. 2 is a kind of internal module connection figure of integrated singl e photon detection circuit of the utility model.
Fig. 3 is circuit diagram of the utility model for the delay circuit of avalanche photodide.
Fig. 4 is the delay circuit sequence diagram that the utility model is used for avalanche photodide.
Fig. 5 is the circuit diagram of narrow pulse signal generation module in the utility model.
Fig. 6 is the sequence diagram of narrow pulse signal generation module in the utility model.
Fig. 7 is the circuit diagram of avalanche photodide module in the utility model.
Fig. 8 is the circuit diagram of snowslide signal screening module in the utility model.
Specific implementation mode
Embodiment 1
The embodiment is the description of the interior layout of integrated singl e photon detection device.
As shown in Figure 1, a kind of integrated singl e photon detection device, including refrigeration module 1, temperature sensor module 2, snowslide
Photodiode module 3, narrow pulse signal generation module 4, avalanche signal screen module 5, I/O module 6, heat sink 7, delay circuit
9, sealing heat insulation packed module 8, heat sink 7 is arranged in the top of refrigeration module 1, and the setting of avalanche photodide module 3 is being freezed
Refrigeration module 1 is simultaneously close in the lower section of module 1, and temperature sensor module 2 is arranged in the side of avalanche photodide module 3, prolongs
When circuit 9, narrow pulse signal generation module 4, avalanche signal screen module 5 or so set gradually and be located at avalanche photodide
The left and right sides that module 5 is screened in delay circuit 9 and avalanche signal is arranged in the lower section of module 3, I/O module 6.Refrigeration module 1, temperature
It spends sensor assembly 2, avalanche photodide module 3, narrow pulse signal generation module 4, avalanche signal and screens module 5, heat sink
7, delay circuit 9 is arranged in sealing heat insulation packed module 8.Sealing heat insulation packed module 8 can increase entire reception device
Anti-interference ability, and then improve overall performance.Since integrated seal is sealing off package module after each module placement in device
It is interior, so that whole device volume reduces, and can promote detector device subminaturization.
In detail, refrigeration module 1 is TEC refrigerators.
I/O module 6 includes input terminal and output end, and the input terminal includes power end, photon synchronizing signal a input terminals, discriminates
Other threshold value input, optical signal input, by delay chip number control terminal, time delay interval control terminal.Output end includes temperature
Spend sensor signal output end, snowslide terminal count output.
Temperature sensor module 2 includes temperature sensor and D/A converting circuit, and avalanche photodide module 3 includes two
The test side of pole pipe driving circuit and diode D1, temperature sensor are arranged in the sides diode D1, the signal of temperature sensor
The input terminal of output end and D/A converting circuit connects, and the output end of D/A converting circuit is as temperature sensor signal output end
And it is exported from I/O module 6.Temperature sensor signal output end exports 8 or 16 position digital signals.
The components such as refrigeration module 1 therein, avalanche photodide module 3 all select miniaturized components, and connection side
Formula and the structure of setting not only make quantum communications field single photon detection optical-electric module minimize；Also make quantum communications field single
Photon detection device miniaturization.It is modular that the job stability for enhancing device is set, increase anti-interference ability, and then improve
Overall performance.Reduce the amount of parts in whole system by encapsulation, and unifies entire integrated singl e photon detection
Device and manufacture craft.
Embodiment 2
The embodiment is the description to integrating the connection of singl e photon detection circuit internal module.
As shown in Fig. 2, the input terminal of delay circuit 9 includes photon synchronizing signal a input terminals, by delay chip time numerical control
End processed, time delay interval control terminal, the output end of delay circuit 9 is connect with the input terminal of narrow pulse signal generation module 4, described narrow
Pulse signal generation module 4 includes the first output end of signal, signal second output terminal, and it includes screening that avalanche signal, which screens module 5,
First input end screens the second input terminal, screens output end, the first output end of signal of the narrow pulse signal generation module 4
It is connect with an input terminal of avalanche photodide module 3, another input terminal of avalanche photodide module 3 is believed for light
Number input terminal, the output end of avalanche photodide module 3 are connect with first input end is screened, narrow pulse signal generation module 4
Signal second output terminal and avalanche signal screen the second input terminal of examination of module 5 and connect, avalanche signal examination module 5 also has
It is snowslide terminal count output to have discriminator input terminal, the examination output end that the avalanche signal screens module 5.
The course of work using the circuit module of above-mentioned connection type is as follows：
Externally input photon synchronizing signal a first passes through delay circuit 9 and generates delay output signal b, delay output signal b
It is input to narrow pulse signal generation module 4, narrow pulse signal generation module 4 generates the gate signal c and specific width of specific width
Meet gate signal d.Gate signal c is input in avalanche photodide module 3, is generated avalanche signal e and is input to snowslide letter
Number screen module 5 examination first input end.Meet gate signal d and is input to the input of examination second that avalanche signal screens module 5
End, avalanche signal screen module 5 and export snowslide counting pulse signal f to outside according to the discriminator of outside setting.
Embodiment 3
The embodiment is the description to the delay circuit 9 for avalanche photodide.
As shown in Figure 3-4, delay circuit 9 include or door chip 91, the first delay chip 95, selection chip 94, control choosing electricity
Road or door chip 91, the first delay chip 95, selection chip 94 is sequentially connected electrically or an input terminal conduct of door chip 91
The input terminal of entire delay circuit 9 simultaneously inputs photon synchronizing signal a, and the output end of the selection chip 94 includes two, wherein
One output end as delay circuit 9 exports delay output signal b, another with or another input terminal of door chip 91 connect
Timing circuit is formed, it includes selection control terminal to select chip 94, and control selects the output end of circuit to be connect with the selection control terminal.
First delay chip 95 further includes time delay interval control terminal, and the control selects circuit to include counter 92, compare
Device 93, the counter 92 include reset terminal, clock signal terminal, output end, and reset terminal and input photon synchronizing signal be a's or door
Input terminal connection, clock signal terminal connect with the output end of the first delay chip 95, and one of output end and comparator 93 is defeated
Enter end connection, another input terminal of comparator 93, which is used as, passes through delay chip number control terminal, is connected through delay chip
Number control device, the output end of comparator 93 are connect with the selection control terminal.
9 main function of delay circuit is to signal into line delay.Core component is the first delay chip 95.By to delay
Being multiplexed to reduce the use number of delay chip for chip, reduces overall power, increases dynamic delay range.
The signal of photon synchronizing signal a input terminals input is to need the signal that is delayed by, time of delay can pass through through
Delay chip time number control device and time delay interval control terminal are crossed to be arranged, selects chip 94 according to Rule of judgment come handoff delay
Photon synchronizing signal a afterwards is directly as delay output signal b or to be again inputted into the first delay chip 95.
Pass through the number of delay chip, the input as comparator 93 by delay chip time number control device setting signal
Parameter.When the numerical value of time delay interval control terminal input is equal to the numerical value by delay chip time number control device input, selection
The selection of chip 94 exports delay output signal from delay circuit 9.In Fig. 4, when (time delay interval control terminal inputs count value
Numerical value) with the numerical value of delay setting it is equal (by the numerical value of delay chip time number control device input) when, i.e., when being all H4, choosing
The selection of chip 94 is selected to export delay output signal b.
Embodiment 4
The embodiment is the description to narrow pulse signal generation module 4.
As seen in figs. 5-6, the narrow pulse signal generation module 4 include the first driving part 41, the second driving part 42,
Second delay chip 43, third delay chip 44, the first NAND gate chip 45, the second NAND gate chip 46.
First driving part 41 includes driving first input end, the first output end of driving and drives second output terminal,
Second driving part 42 includes the 4th output end of the second input terminal of driving, driving third output end and driving.
The driving first input end and the second input terminal of driving connect i.e. input with the output end of delay circuit 9 and prolong respectively
When output signal b.
The first output end of the driving is connect with the input terminal of the second delay chip 43, the output end of the second delay chip 43
It is connect with an input terminal of the first NAND gate chip 45, the driving second output terminal is another with the first NAND gate chip 45
Input terminal is directly connected to, the output end output gate signal c of the first NAND gate chip 45.The driving third output end prolongs with third
When chip 44 input terminal connection, the input terminal company of the output end of third delay chip 44 and the second NAND gate chip 46
It connects, another input terminal of driving the 4th output end and the second NAND gate chip 46 is directly connected to, the second NAND gate chip 46
Output end output meet gate signal d.
In the above-mentioned technical solutions, the effect of the first driving part 41 and the second driving part 42 is to prevent electricity shortage,
Waveform deforms.There are certain requirement, the second delay chip for inside modules power consumption in electronic circuit due to integrated
43 and third delay chip 44 be integrated in a binary channels delay chip, correspondingly, the first driving part 41 and second drive
Component 42 is replaced using a binary channels driving device or multichannel driving device.
In figure 6, two input terminals of 45 two input terminals of the first NAND gate chip and the second NAND gate chip 46 when
Sequential A, sequential B, sequential E, sequential D in sequence figure such as figure.
Embodiment 5
The embodiment is the description to avalanche photodide module 3.
As shown in fig. 7, the avalanche photodide module 3 include diode D1, triode Q1, resistance R1, resistance R2,
Resistance R3, capacitance C1, the first level terminal, second electrical level end, the one end the resistance R1 are the input of avalanche photodide module 3
End, connect with the output end of the first NAND gate chip 45 in narrow pulse signal generation module 4, receives narrow pulse signal generation module
The gate signal c of 4 specific widths generated, the other end of the resistance R1 are connect with the base stage of triode Q1, the first level terminal warp
It crosses resistance R2 to connect with the collector of triode Q1, the collector of triode Q1 is also connect with the cathode of diode D1, diode
The anode of D1 is connect by resistance R3 with second electrical level end, and the anode of diode D1 is connect with one end of capacitance C1, capacitance C1's
Output end of the other end as avalanche photodide module 3.First level terminal voltage value is 5V, and pressure differential range is positive and negative 2V,
Second electrical level terminal voltage value is -60V, and pressure differential range is positive and negative 10V.It is provided with optical fiber on 8 shell of sealing heat insulation packed module, institute
The photon for stating optical fiber input is radiated at as optical signal on diode D1.Since the device integrated level is high, triode Q1 and two poles
Direct-coupling controls between pipe D1, can not consider impedance matching, since impedance matching needs to use larger resistance, so integrated
After reduce loss.
Embodiment 6
The embodiment is that the description of module 5 is screened to avalanche signal.
As shown in figure 8, the avalanche signal screen module 5 include triode Q2, triode Q3, triode Q4, resistance R4,
Resistance R5, resistance R6, resistance R7, resistance R8, capacitance C2, the first power supply VCC, discriminator input terminal Vth, current source, it is described
The base stage of triode Q2 is connect with the output end of the second NAND gate chip 46 in narrow pulse signal generation module 4, receive second with
The specific width that NOT gate chip 46 exports meets gate signal d.First power supply VCC passes through the collector of resistance R4 and triode Q2
Connection.The output end of avalanche photodide module 3 is connect by resistance R5 with the base stage of triode Q3.Discriminator input terminal
Vth is also connect with the base stage of triode Q3 by resistance R6, and the first power supply VCC connects by the collector of resistance R7 and triode Q3
It connects, the collector of triode Q3 is connect with one end of capacitance C2, and the other end of capacitance C2 is as snowslide terminal count output.Discriminating threshold
Value input terminal Vth is connect by resistance R8 with the base stage of triode Q4, and the first power supply VCC directly connects with the collector of triode Q4
It connects.The emitter of triode Q2, the emitter of triode Q3, triode Q4 three end of emitter connection after behind overcurrent source with
Ground connects.The resistance value of resistance R8 in the program is less than the resistance value of resistance R6.The function that avalanche signal screens module 5 is to meet
In the gate signal d times, when avalanche signal level is higher than discriminator, snowslide counting pulse signal f is exported.
It these are only the preferred embodiment that the utility model is created, be not intended to limit the utility model creation, it is all
All any modification, equivalent and improvement etc., should be included in this made by within the spirit and principle created in the utility model
Within the protection domain that utility model is created.
Claims (10)
1. a kind of delay circuit for avalanche photodide, which is characterized in that including or door chip, the first delay chip,
Selection chip, control select circuit, and described or door chip, the first delay chip, selection chip are sequentially connected electrically, described or door chip
One input terminal as entire delay circuit input terminal and input photon synchronizing signal a, the output end packet of the selection chip
Two are included, one of output end as delay circuit, another connect with described or door chip another input terminal, described
It includes selection control terminal to select chip, and the control selects the output end of circuit to be connect with the selection control terminal.
2. the delay circuit according to claim 1 for avalanche photodide, which is characterized in that first delay
Chip further includes time delay interval control terminal.
3. the delay circuit according to claim 1 or 2 for avalanche photodide, which is characterized in that the control choosing
Circuit includes counter, comparator, and the counter includes reset terminal, clock signal terminal, output end, the reset terminal and input
A's or door the input terminal connection of photon synchronizing signal, the clock signal terminal are connect with the output end of first delay chip,
The output end of the counter is connect with an input terminal of the comparator, another input terminal of the comparator is as warp
Cross delay chip number control terminal, be connected through delay chip time number control device, the output end of the comparator with it is described
Select control terminal connection.
4. a kind of includes the integrated list of the delay circuit for avalanche photodide as described in claim 1-3 any one
Photon detection circuit, which is characterized in that including delay circuit, avalanche photodide module, narrow pulse signal generation module, snow
Signal screening module is collapsed, the output end of the delay circuit is connect with the input terminal of the narrow pulse signal generation module, described
Narrow pulse signal generation module includes the first output end of signal, signal second output terminal, and the avalanche signal screens module and includes
First input end is screened, the second input terminal is screened, screens output end, the first output end of the signal and two pole of the avalanche optoelectronic
The input terminal of tube module connects, and the output end of the avalanche photodide module is connect with the examination first input end, institute
It states signal second output terminal to connect with the second input terminal of the examination, the output end for screening output end as entire circuit.
5. integrated singl e photon detection circuit according to claim 4, which is characterized in that the narrow pulse signal generation module
Including the second delay chip, third delay chip, the first NAND gate chip, the second NAND gate chip；The output end of delay circuit
Connect second delay chip and the third delay chip；The output end of second delay chip with described first with it is non-
The input terminal connection of door chip, the output end output gate signal c of the first NAND gate chip；The third delay chip
Output end connect with an input terminal of the second NAND gate chip, the output end of the second NAND gate chip output symbol
Close gate signal d.
6. integrated singl e photon detection circuit according to claim 5, which is characterized in that further include the first driving part,
Two driving parts, first driving part include driving first input end, the first output end of driving and drive second output terminal,
Second driving part includes the 4th output end of the second input terminal of driving, driving third output end and driving；The driving the
One input terminal and the second input terminal of driving are connect with the output end of delay circuit respectively；The first output end of the driving and described the
The input terminal of two delay chips connects, and the driving second output terminal and another input terminal of the first NAND gate chip are direct
Connection；The driving third output end is connect with the input terminal of the third delay chip, the 4th output end of the driving and institute
Another input terminal for stating the second NAND gate chip is directly connected to.
7. integrated singl e photon detection circuit according to claim 4, which is characterized in that the avalanche photodide module
It is described including diode D1, triode Q1, resistance R1, resistance R2, resistance R3, capacitance C1, the first level terminal, second electrical level end
The one end resistance R1 is the input terminal of the avalanche photodide module, is connect with the output end of narrow pulse signal generation module,
The other end of the resistance R1 is connect with the base stage of the triode Q1, first level terminal by the resistance R2 with it is described
The collector of triode Q1 connects, and the collector of the triode Q1 is also connect with the cathode of the diode D1, two pole
The anode of pipe D1 is connect by the resistance R3 with the second electrical level end, and the anode of the diode D1 is with the capacitance C1's
One end connects, the output end of the other end of the capacitance C1 as the avalanche photodide module.
8. integrated singl e photon detection circuit according to claim 7, which is characterized in that further include temperature sensor, temperature
The test side of sensor is arranged in the sides the diode D1.
9. integrated singl e photon detection circuit according to claim 7, which is characterized in that also connect with optical fiber, the optical fiber
The photon irradiation of input is on the diode D1.
10. integrated singl e photon detection circuit according to claim 5 or 6, which is characterized in that the avalanche signal screens mould
Block includes triode Q2, triode Q3, triode Q4, resistance R4, resistance R5, resistance R6, resistance R7, resistance R8, capacitance C2,
One power supply VCC, discriminator input terminal Vth, current source, the base stage of the triode Q2 and the narrow pulse signal generation module
In the second NAND gate chip output end connection, the first power supply VCC pass through the resistance R4 and the triode Q2 collection
Electrode connects, and the output end of the avalanche photodide module connects by the base stage of the resistance R5 and triode Q3
It connects, the discriminator input terminal Vth is also connect with the base stage of the triode Q3 by the resistance R6, first power supply
VCC is connect by the resistance R7 with the collector of the triode Q3, the collector of the triode Q3 and the capacitance C2
One end connection, the other end of the capacitance C2 is used as snowslide terminal count output, described in the discriminator input terminal Vth processes
Resistance R8 is connect with the base stage of the triode Q4, and the first power supply VCC is directly connect with the collector of the triode Q4,
The emitter of the triode Q2, the emitter of the triode Q3, the triode Q4 three end of emitter connection after by
It is connected to ground after the current source.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820219192.9U CN207816459U (en) | 2018-02-07 | 2018-02-07 | Delay circuit for avalanche photodide and integrated singl e photon detection circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820219192.9U CN207816459U (en) | 2018-02-07 | 2018-02-07 | Delay circuit for avalanche photodide and integrated singl e photon detection circuit |
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| CN207816459U true CN207816459U (en) | 2018-09-04 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201820219192.9U Withdrawn - After Issue CN207816459U (en) | 2018-02-07 | 2018-02-07 | Delay circuit for avalanche photodide and integrated singl e photon detection circuit |
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| CN (1) | CN207816459U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110118598A (en) * | 2018-02-07 | 2019-08-13 | 科大国盾量子技术股份有限公司 | Delay circuit and integrated singl e photon detection circuit for avalanche photodide |
| CN112557883A (en) * | 2021-02-26 | 2021-03-26 | 坤元微电子(南京)有限公司 | Pulse signal parameter testing system |
-
2018
- 2018-02-07 CN CN201820219192.9U patent/CN207816459U/en not_active Withdrawn - After Issue
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110118598A (en) * | 2018-02-07 | 2019-08-13 | 科大国盾量子技术股份有限公司 | Delay circuit and integrated singl e photon detection circuit for avalanche photodide |
| CN110118598B (en) * | 2018-02-07 | 2024-07-02 | 科大国盾量子技术股份有限公司 | Delay circuit for avalanche photodiode and integrated single photon detection circuit |
| CN112557883A (en) * | 2021-02-26 | 2021-03-26 | 坤元微电子(南京)有限公司 | Pulse signal parameter testing system |
| CN112557883B (en) * | 2021-02-26 | 2021-05-25 | 坤元微电子(南京)有限公司 | Pulse signal parameter testing system |
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