CN112782550B - Nanosecond transmission delay testing device and method - Google Patents
Nanosecond transmission delay testing device and method Download PDFInfo
- Publication number
- CN112782550B CN112782550B CN201911064829.7A CN201911064829A CN112782550B CN 112782550 B CN112782550 B CN 112782550B CN 201911064829 A CN201911064829 A CN 201911064829A CN 112782550 B CN112782550 B CN 112782550B
- Authority
- CN
- China
- Prior art keywords
- waveform
- comparator
- voltage
- transmission delay
- input end
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2882—Testing timing characteristics
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/30—Structural combination of electric measuring instruments with basic electronic circuits, e.g. with amplifier
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R35/00—Testing or calibrating of apparatus covered by the other groups of this subclass
- G01R35/005—Calibrating; Standards or reference devices, e.g. voltage or resistance standards, "golden" references
Abstract
The nanosecond transmission delay test device and method can convert the transmission delay into a voltage test by constructing a combination of a rising edge pre-processing circuit, a falling edge pre-processing circuit and a synthesis post-processing circuit, so that the nanosecond transmission delay test is realized, for example, the transmission delay test carried out on SGM48000 chips and the like with the transmission delay magnitudes of 10-20ns on the rising edge and the falling edge is successfully realized.
Description
Technical Field
The invention relates to a transmission delay test technology of a chip circuit, in particular to a nanosecond transmission delay test device and a nanosecond transmission delay test method, which can convert transmission delay into voltage test by constructing a combination of a rising edge pre-processing circuit, a falling edge pre-processing circuit and a synthesis post-processing circuit, thereby realizing nanosecond transmission delay test, for example, successfully realizing transmission delay test on SGM48000 chips and the like with the transmission delay magnitudes of 10-20ns on the rising edge and the falling edge.
Background
For the transmission delay test of a chip circuit, a tester is generally used for directly measuring time. However, the inventor finds that the time measurement cannot be realized by directly adopting a tester for nanosecond transmission delay test in practical work, for example, the SGM48000 chip with the transmission delay magnitude of 10-20ns on both rising edge and falling edge cannot be tested on mass production, i.e. the test cannot be performed by the tester. The inventors believe that if the transmission delay is converted into a voltage test by constructing a combination of a rising edge pre-processing circuit and a falling edge pre-processing circuit with a synthetic post-processing circuit, the nanosecond transmission delay test is realized. In view of this, the present inventors have completed the present invention.
Disclosure of Invention
Aiming at the defects or shortcomings in the prior art, the invention provides a nanosecond transmission delay test device and a nanosecond transmission delay test method, which can convert the transmission delay into a voltage test by constructing a rising edge pre-processing circuit and a falling edge pre-processing circuit and a synthesis post-processing circuit, thereby realizing nanosecond transmission delay test, for example, successfully realizing the transmission delay test of SGM48000 chips and the like with the transmission delay magnitudes of 10-20ns on the rising edge and the falling edge.
The technical scheme of the invention is as follows:
the nanosecond transmission delay testing device is characterized by comprising a rising edge preprocessing circuit and a falling edge preprocessing circuit, wherein the rising edge preprocessing circuit and the falling edge preprocessing circuit are respectively connected with a filter circuit, and the filter circuit is connected with a testing machine through an amplifying circuit.
The rising edge pre-processing circuit comprises a first comparator and a second comparator, wherein the positive input end of the first comparator is connected with an input waveform end to be detected, the negative input end of the first comparator is connected with an input reference voltage end, the output end of the first comparator is connected with the first input end of an AND gate circuit, the positive input end of the second comparator is connected with an output waveform end to be detected, the negative input end of the second comparator is connected with an output reference voltage end, the output end of the second comparator is connected with the second input end of the AND gate circuit through a first odd number NOT gate circuit, and the output end of the AND gate circuit is connected with the first input end of the filter circuit.
The falling edge pre-processing circuit comprises a third comparator and a fourth comparator, wherein the positive input end of the third comparator is connected with an input waveform end to be detected, the negative input end of the third comparator is connected with an input reference voltage end, the output end of the third comparator is connected with the first input end of the NOR gate circuit, the positive input end of the fourth comparator is connected with an output waveform end to be detected, the negative input end of the fourth comparator is connected with an output reference voltage end, the output end of the fourth comparator is connected with the second input end of the NOR gate circuit through a second odd number of NOT gate circuits, and the output end of the NOR gate circuit is connected with the second input end of the filter circuit.
The first comparator and the third comparator adopt the same physical comparator circuit.
The second comparator and the fourth comparator adopt the same physical comparator circuit.
A nanosecond transmission delay test method is characterized by comprising the steps of converting an ascending inclined edge IN an input waveform IN to be tested into a vertical ascending edge of a waveform A, converting an ascending inclined edge IN an output waveform OUT to be tested into a vertical ascending edge of a waveform B, converting an descending inclined edge IN the input waveform IN to be tested into a vertical descending edge of the waveform A, converting an descending inclined edge IN the output waveform OUT to be tested into a vertical descending edge of the waveform B, inverting the waveform B into a waveform C, performing logical AND operation on the waveform A and the waveform C to obtain a ascending edge transmission delay pulse waveform D, performing logical NOR operation on the waveform A and the waveform C to obtain a descending edge transmission delay pulse waveform H, performing filtering processing on the pulse waveform D and the pulse waveform H to obtain a voltage E, wherein the voltage value of the voltage E is an average value of a pulse voltage IN transmission delay time, amplifying the voltage E to obtain a voltage F, and determining the transmission delay time by measuring the voltage value of the voltage F.
The method comprises the steps of inputting an input waveform IN to be detected into a positive input end of a comparator, inputting an input reference voltage Ref_IN into a negative input end of the comparator, outputting the waveform A by the comparator, inputting an output waveform OUT to be detected into the positive input end of the comparator, inputting an output reference voltage Ref_OUT into the negative input end of the comparator, outputting the waveform B by the comparator, and generating the waveform C by an odd number of NOT circuits.
The waveform A and the waveform C generate the rising-edge transmission delay pulse waveform D through an AND gate circuit, and the waveform A and the waveform C generate the falling-edge transmission delay pulse waveform H through a NOR gate circuit.
The pulse waveform D and the pulse waveform H generate the voltage E through a filter, and the voltage E generates the voltage F through amplification of an amplifier.
The voltage F is tested by a testing machine, the testing machine is calibrated before the test, the voltage value measured by the same waveform is input and output as delay error voltage G existing in the testing machine, the value=F ' -G, F ' of the voltage F is a measured value obtained directly by the testing machine after the voltage F is measured, the F ' -G is fitted with the transmission delay time measured by an oscilloscope in practice to form a proportional relation, and the voltage signal is directly tested on the testing machine according to the proportional relation to test the transmission delay.
The invention has the following technical effects: according to the nanosecond transmission delay testing device and method, the circuit structure for converting the transmission delay into the voltage test is built, so that the tester can effectively test the nanosecond transmission delay, and the problem that the SGM48000 chip cannot perform the transmission delay test in mass production is solved.
Drawings
Fig. 1 is a schematic structural diagram of a nanosecond transmission delay testing device for implementing the invention. Fig. 1 includes circuitry for pre-processing the rising and falling edges, respectively (to obtain rising edge D and falling edge H pulses), and post-processing circuitry for filtering, amplifying and entering the tester for testing. The rising edge pre-processing circuit comprises a first comparator and a second comparator, a first N NOT circuits (N NOT circuits are used for increasing transmission delay time and reversing output waveforms, and N is an odd number larger than 1), and an AND circuit. The falling edge pre-processing circuit comprises a third comparator and a fourth comparator, a second N NOT circuits (N NOT circuits are used for increasing transmission delay time and reversing output waveforms, and N is an odd number larger than 1), and a NOT circuit.
Fig. 2 is a timing diagram of the various nodes of fig. 1. The nodes involved IN FIG. 2 are Ref_IN, IN, ref_OUT, OUT, A, B, C, D, H, E, F. The abscissa of fig. 2 is time, and the ordinate is voltage. Both the rising edge propagation delay (waveform IN rising edge compared to waveform OUT rising edge) and the falling edge propagation delay (waveform IN falling edge compared to waveform OUT falling edge) are nanoseconds, e.g., 10-20ns. The waveform a of the a node is obtained by comparing the input waveform IN with the input reference voltage ref_in. The waveform B of the node B is obtained by comparing the output waveform OUT with the output reference voltage ref_out. Waveform C of node C is the inverse of waveform B. Waveform d=waveform a×waveform C (corresponding to rising edge propagation delay). Waveform H is obtained by performing NOR operation on waveform A and waveform C (corresponding to the transmission delay of the falling edge). The voltage E is obtained by filtering the pulse signal D and the pulse signal H. The voltage F is an amplification of the voltage E (for the tester to test the voltage value).
Detailed Description
The invention will be described with reference to the accompanying drawings (fig. 1-2).
Fig. 1 is a schematic structural diagram of a nanosecond transmission delay testing device for implementing the invention. Fig. 2 is a timing diagram of the various nodes of fig. 1. Referring to fig. 1 and 2, a nanosecond transmission delay testing device comprises a rising edge preprocessing circuit and a falling edge preprocessing circuit, wherein the rising edge preprocessing circuit and the falling edge preprocessing circuit are respectively connected with a filter circuit, and the filter circuit is connected with a testing machine through an amplifying circuit. The rising edge pre-processing circuit comprises a first comparator and a second comparator, wherein the positive input end (+) of the first comparator is connected with an input waveform end IN to be detected, the negative input end (-) of the first comparator is connected with an input reference voltage end Ref_IN, the output end of the first comparator is connected with the first input end of an AND gate circuit, the positive input end (+) of the second comparator is connected with an output waveform end OUT to be detected, the negative input end (-) of the second comparator is connected with an output reference voltage end Ref_OUT, the output end of the second comparator is connected with the second input end of the AND gate circuit through a first odd number of NOT gates, and the output end of the AND gate circuit is connected with the first input end of the filter circuit. The falling edge pre-processing circuit comprises a third comparator and a fourth comparator, wherein the positive input end (+) of the third comparator is connected with an input waveform end IN to be detected, the negative input end (-) of the third comparator is connected with an input reference voltage end Ref_IN, the output end (+) of the third comparator is connected with the first input end of a NOR gate circuit, the positive input end (+) of the fourth comparator is connected with an output waveform end OUT to be detected, the negative input end (-) of the fourth comparator is connected with an output reference voltage end Ref_OUT, the output end of the fourth comparator is connected with the second input end of the NOR gate circuit through a second odd number of NOR gates, and the output end of the NOR gate circuit is connected with the second input end of the filter circuit. The first comparator and the third comparator adopt the same physical comparator circuit. The second comparator and the fourth comparator adopt the same physical comparator circuit.
As shown IN fig. 1 to 2, a nanosecond transmission delay test method includes converting an upward inclined rising edge IN an input waveform IN to be tested into a vertical rising edge of a waveform a, converting an upward inclined rising edge IN an output waveform OUT to be tested into a vertical rising edge of a waveform B, converting a downward inclined falling edge IN the input waveform IN to be tested into a vertical falling edge of a waveform a, converting a downward inclined falling edge IN the output waveform OUT to be tested into a vertical falling edge of a waveform B, inverting the waveform B into a waveform C, performing logical and operation on the waveform a and the waveform C to obtain a rising edge transmission delay pulse waveform D, performing logical nor operation on the waveform a and the waveform C to obtain a falling edge transmission delay pulse waveform H, performing filtering processing on the pulse waveform D and the pulse waveform H to obtain a voltage E, wherein a voltage value of the voltage E is a pulse voltage average value IN a transmission delay time, amplifying the voltage E to obtain a voltage F, and determining the transmission delay time by measuring a voltage value of the voltage F. The method comprises the steps of inputting an input waveform IN to be detected into a positive input end of a comparator, inputting an input reference voltage Ref_IN into a negative input end of the comparator, outputting the waveform A by the comparator, inputting an output waveform OUT to be detected into the positive input end of the comparator, inputting an output reference voltage Ref_OUT into the negative input end of the comparator, outputting the waveform B by the comparator, and generating the waveform C by an odd number of NOT circuits. The waveform A and the waveform C generate the rising-edge transmission delay pulse waveform D through an AND gate circuit, and the waveform A and the waveform C generate the falling-edge transmission delay pulse waveform H through a NOR gate circuit. The pulse waveform D and the pulse waveform H generate the voltage E through a filter, and the voltage E generates the voltage F through amplification of an amplifier. The voltage F is tested by a testing machine, the testing machine is calibrated before the test, the voltage value measured by the same waveform is input and output as delay error voltage G existing in the testing machine, the value=F ' -G, F ' of the voltage F is a measured value obtained directly by the testing machine after the voltage F is measured, the F ' -G is fitted with the transmission delay time measured by an oscilloscope in practice to form a proportional relation, and the voltage signal is directly tested on the testing machine according to the proportional relation to test the transmission delay.
The working principle of converting transmission delay into voltage test by constructing a circuit is described below by combining fig. 1 and 2:
1. comparing the input waveform with Ref_IN voltage to obtain a waveform A, comparing the output waveform with Ref_OUT voltage to obtain a waveform B, wherein the Ref_IN voltage and the Ref_OUT voltage can be changed appropriately according to actual requirements (Ref_IN is 50% of IN high level and Ref_OUT is 50% of OUT high level IN a timing diagram);
2. the waveform B is passed through N NOT gates to obtain waveform C, so that the goal is to increase transmission delay time by NOT gates, and at the same time, reverse the output waveform;
3. measuring rising edge transmission delay: sending the waveform A and the waveform C into an AND gate to obtain a waveform D, and converting the rising edge transmission delay from IN to OUT into a pulse signal D with the same time;
4. measuring the transmission delay of the falling edge: sending the waveform A and the waveform C into a NOR gate to obtain a waveform D, and converting the transmission delay of the falling edge from IN to OUT into a pulse signal H with the same time;
5. the pulse signal D is sent to the RC filter by testing rising edge transmission delay, the pulse signal H is sent to the RC filter by testing falling edge transmission delay, and the pulse signals are respectively converted into voltage E;
6. after the voltage E is amplified, a testing machine is used for directly testing the voltage signal, and then a pulse voltage average value F in the corresponding transmission delay time can be obtained;
7. calibration equipment is required before testing: the input and the output adopt the same waveform, and the voltage value measured by the testing machine is the delay error G existing in the equipment;
8. after the delay error of the equipment is removed, the average voltage of the pulse signal in the rising edge transmission delay time is F-G;
9. and fitting the obtained average voltage F-G with the rising edge transmission delay time actually measured by an oscilloscope to obtain a proportional relation, and directly testing a voltage signal on a testing machine to test the transmission delay.
It is noted that the above description is helpful for a person skilled in the art to understand the present invention, but does not limit the scope of the present invention. Any and all such equivalent substitutions, modifications and/or deletions as may be made without departing from the spirit and scope of the invention.
Claims (2)
1. The nanosecond transmission delay testing device is characterized by comprising a rising edge preprocessing circuit and a falling edge preprocessing circuit, wherein the rising edge preprocessing circuit and the falling edge preprocessing circuit are respectively connected with a filter circuit, and the filter circuit is connected with a testing machine through an amplifying circuit;
the rising edge pre-processing circuit comprises a first comparator and a second comparator, wherein the positive input end of the first comparator is connected with an input waveform end to be detected, the negative input end of the first comparator is connected with an input reference voltage end, the output end of the first comparator is connected with the first input end of an AND gate circuit, the positive input end of the second comparator is connected with an output waveform end to be detected, the negative input end of the second comparator is connected with an output reference voltage end, the output end of the second comparator is connected with the second input end of the AND gate circuit through a first odd number NOT gate circuit, and the output end of the AND gate circuit is connected with the first input end of the filter circuit;
the falling edge pre-processing circuit comprises a third comparator and a fourth comparator, wherein the positive input end of the third comparator is connected with an input waveform end to be detected, the negative input end of the third comparator is connected with an input reference voltage end, the output end of the third comparator is connected with the first input end of the NOR gate circuit, the positive input end of the fourth comparator is connected with an output waveform end to be detected, the negative input end of the fourth comparator is connected with an output reference voltage end, the output end of the fourth comparator is connected with the second input end of the NOR gate circuit through a second odd number of NOT gate circuits, and the output end of the NOR gate circuit is connected with the second input end of the filter circuit.
2. A nanosecond transmission delay test method is characterized by comprising the steps of converting an ascending inclined edge IN an input waveform IN to be tested into a vertical ascending edge of a waveform A, converting an ascending inclined edge IN an output waveform OUT to be tested into a vertical ascending edge of a waveform B, converting an descending inclined edge IN the input waveform IN to be tested into a vertical descending edge of the waveform A, converting an descending inclined edge IN the output waveform OUT to be tested into a vertical descending edge of the waveform B, reversing the waveform B into a waveform C, performing logical AND operation on the waveform A and the waveform C to obtain a ascending edge transmission delay pulse waveform D, performing logical NOR operation on the waveform A and the waveform C to obtain a descending edge transmission delay pulse waveform H, performing filtering processing on the pulse waveform D and the pulse waveform H to obtain a voltage E, wherein the voltage value of the voltage E is an average value of a pulse voltage IN transmission delay time, amplifying the voltage E to obtain a voltage F, and determining the transmission delay time by measuring the voltage value of the voltage F;
inputting an input waveform IN to be tested into a positive input end of a comparator, inputting an input reference voltage Ref_IN into a negative input end of the comparator, outputting the waveform A by the comparator, inputting an output waveform OUT to be tested into the positive input end of the comparator, inputting an output reference voltage Ref_OUT into the negative input end of the comparator, outputting the waveform B by the comparator, and generating the waveform C by an odd number of NOT circuits;
the waveform A and the waveform C generate the rising-edge transmission delay pulse waveform D through an AND gate circuit, and the waveform A and the waveform C generate the falling-edge transmission delay pulse waveform H through a NOR gate circuit;
the pulse waveform D and the pulse waveform H generate the voltage E through a filter, and the voltage E generates the voltage F through amplification of an amplifier;
the voltage F is tested by a testing machine, the testing machine is calibrated before the test, the voltage value measured by the same waveform is input and output as delay error voltage G existing in the testing machine, the value=F ' -G, F ' of the voltage F is a measured value obtained directly by the testing machine after the voltage F is measured, the F ' -G is fitted with the transmission delay time measured by an oscilloscope in practice to form a proportional relation, and the voltage signal is directly tested on the testing machine according to the proportional relation to test the transmission delay.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911064829.7A CN112782550B (en) | 2019-11-04 | 2019-11-04 | Nanosecond transmission delay testing device and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911064829.7A CN112782550B (en) | 2019-11-04 | 2019-11-04 | Nanosecond transmission delay testing device and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112782550A CN112782550A (en) | 2021-05-11 |
| CN112782550B true CN112782550B (en) | 2023-05-26 |
Family
ID=75747250
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911064829.7A Active CN112782550B (en) | 2019-11-04 | 2019-11-04 | Nanosecond transmission delay testing device and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112782550B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6349267B1 (en) * | 1998-09-11 | 2002-02-19 | Agere Systems Inc. | Rise and fall time measurement circuit |
| CN202421440U (en) * | 2011-12-21 | 2012-09-05 | 上海晨兴希姆通电子科技有限公司 | Circuit delay time measurement device |
| CN106771990A (en) * | 2016-12-07 | 2017-05-31 | 武汉新芯集成电路制造有限公司 | The measuring circuit and measuring method of d type flip flop setup time |
| CN106782669A (en) * | 2016-11-23 | 2017-05-31 | 上海华力微电子有限公司 | A kind of self calibration scalability SRAM delay test circuits |
| CN108120919A (en) * | 2017-12-27 | 2018-06-05 | 北京华峰测控技术股份有限公司 | A kind of integrated circuit time parameter test circuit and method |
| CN110007162A (en) * | 2017-11-29 | 2019-07-12 | 台湾积体电路制造股份有限公司 | For monitoring the circuit of the transient time in simulation system and digital display circuit |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100843207B1 (en) * | 2006-11-01 | 2008-07-02 | 삼성전자주식회사 | Apparatus for measuring transmission delay |
| KR102626858B1 (en) * | 2016-11-02 | 2024-01-19 | 삼성전자주식회사 | Test system for measuring propagation time of transmission line |
-
2019
- 2019-11-04 CN CN201911064829.7A patent/CN112782550B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6349267B1 (en) * | 1998-09-11 | 2002-02-19 | Agere Systems Inc. | Rise and fall time measurement circuit |
| CN202421440U (en) * | 2011-12-21 | 2012-09-05 | 上海晨兴希姆通电子科技有限公司 | Circuit delay time measurement device |
| CN106782669A (en) * | 2016-11-23 | 2017-05-31 | 上海华力微电子有限公司 | A kind of self calibration scalability SRAM delay test circuits |
| CN106771990A (en) * | 2016-12-07 | 2017-05-31 | 武汉新芯集成电路制造有限公司 | The measuring circuit and measuring method of d type flip flop setup time |
| CN110007162A (en) * | 2017-11-29 | 2019-07-12 | 台湾积体电路制造股份有限公司 | For monitoring the circuit of the transient time in simulation system and digital display circuit |
| CN108120919A (en) * | 2017-12-27 | 2018-06-05 | 北京华峰测控技术股份有限公司 | A kind of integrated circuit time parameter test circuit and method |
Non-Patent Citations (2)
| Title |
|---|
| 利用延时负反馈进行延时差测量的方法;李强;《无线电工程》;20180625;第48卷(第7期);550-555 * |
| 脉冲雷达测距时间-电压转换方法;袁其平 等;《现代雷达》;20120615;第34卷(第06期);69-73 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112782550A (en) | 2021-05-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1248003C (en) | Calibrating single ended channels for differential performance | |
| CN100446208C (en) | Test system with differential signal measurement | |
| CN103926471B (en) | Eye-open monitor device for high-speed serializer/deserializer and testing method | |
| CN105301627B (en) | A kind of energy spectrum analysis method, energy spectrum analysis system and gamma-ray detection system | |
| CN110708047A (en) | Structure and method for measuring precision of high-speed comparator based on TDC chip | |
| CN101865946A (en) | Alternating current parameter testing system and method of programmable digital integrated circuit | |
| CN202033420U (en) | Special circuit for time parameter tests of analog integrated circuit test system | |
| CN112782550B (en) | Nanosecond transmission delay testing device and method | |
| TWI451108B (en) | Device and method for performing timing analysis | |
| CN201796119U (en) | Programmable digital integrated circuit alternating-current parameter testing system | |
| CN106685377B (en) | Narrow pulse generating circuit and adjustable width single pulse generator | |
| CN105548641A (en) | Waveform triggering device and method and oscilloscope for waveform triggering | |
| CN206193088U (en) | Detection circuitry of trackable peak value | |
| US20160146883A1 (en) | Device and method of detecting signal delay | |
| CN109583029B (en) | Method and device for eliminating slope value of signal edge influenced by edge | |
| JP5608023B2 (en) | Semiconductor integrated circuit and noise tolerance test method | |
| CN111273726B (en) | Duty ratio deviation compensation circuit, method and chip | |
| JP2014130095A (en) | Testing device and testing method | |
| CN112557883B (en) | Pulse signal parameter testing system | |
| CN116298831A (en) | Built-in self-test method and system for internal delay parameters of FPGA (field programmable gate array) | |
| US11269085B2 (en) | Radiation measurement device | |
| CN201184907Y (en) | Circuit test apparatus | |
| Jaya et al. | Frequency-response-associated delay-dispersion issue in time-delay measuring sensors | |
| CN117289116A (en) | Test method of Schmitt trigger | |
| Lee et al. | Low-cost Technique for Measuring Clock Duty Cycle on FPGAs |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |