CN103926471B - Eye-open monitor device for high-speed serializer/deserializer and testing method - Google Patents
Eye-open monitor device for high-speed serializer/deserializer and testing method Download PDFInfo
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Abstract
The invention provides an eye-open monitor device. According to the eye-open monitor device, when signal eye pattern testing is achieved, two eye-open measuring clocks with identical frequency with signals are utilized to test opening sizes of an eye patterns on arranged phase points; threshold value sizes are set and the phases of the measuring clocks are set in half period; whether the set threshold value sizes are located inside the eye patterns at the positions of the measuring clocks is judged, and the largest threshold value inside the eye patterns is the open size of the eye patterns at a clock phase point; the open size results of the eye patterns at all the phase points are stored into registers, the values of the registers are arranged in sequence after all the phase points are tested, and the horizontal open size and the vertical open size of the signal eye patterns are obtained. Compared with the prior art, the eye-open monitor device has the advantages that synchronous operation of an initial clock and data is not needed, setting of a testing process and recording of testing results are completed automatically through a digital control module, and the information of open sizes of the signal eye patterns in one period can be obtained.
Description
Technical field
The present invention relates to the eye pattern test circuit design field of high-speed serializer/deserializer system high speed signal, specifically
Open monitor apparatus and method of testing for a kind of eye for high-speed serializer/deserializer.
Background technology
When serial data is transmitted in a link, because system transfers total characteristic (including the characteristic of equalizer and channel) is paid no attention to
Think, lead to wave distortion, the broadening of before and after's code element, and make above waveform that very long hangover to occur, have influence on taking out of current symbol
The sample moment, thus the judgement to current symbol interferes, here it is so-called intersymbol interference phenomenon.Carrying with data rate
Rise, intersymbol interference phenomenon is also more significantly.Typically using data eye, intersymbol interference amount is weighed.Serial chain in high speed
In the Transmission system of road, transmitting terminal adopts the Pseudo-random bit generator on piece to produce cycle testss.In receiving terminal, believe for receiving
The acquisition of number eye pattern is driven monitor by the eye on piece and is obtained.What on piece, eye opened that monitor can provide eye pattern opens size information,
Even complete eye shape.
At present on piece, eye is driven monitor and can be divided into one-dimensional eye and drives monitor, and two-dimentional eye drives monitor, based on number of edges
According to eye drive monitor, and many sampling eyes drive monitor.
One-dimensional eye is driven monitor and the vertical opening degree of eye pattern is measured, and one-dimensional eye opens the hardware spending of monitor
Little, but one-dimensional eye is driven monitor and can only be monitored the vertical direction of eye pattern it is impossible to know the horizontal opening size of eye pattern.
Two-dimentional eye is driven monitor and in the vertical and horizontal direction eye pattern is monitored simultaneously.It is basic that two-dimentional eye drives monitor
Thought is to be compared with data by being shaped as the template of rectangle, if test data have passed through template, thinks corresponding mould
Plate is disabled, all templates not passing through data is overlapped, just obtains final data eye.But this circuit
During test, the starting clock position of template needs to align with data center, and its alignment operation is by allowing test data through prolonging
Line is realized late.
Driving monitor based on the eye of MARG is to be realized by checking data edge to the monitoring that eye pattern opens, edge
Monitoring typically require intensive sampling, obtained result is indicated using rectangular histogram, and rectangular histogram is narrower, and eye pattern is opened and must be got over
Greatly, but when data rate is too high, limited by sample clock frequency, opened monitor measurement using based on the eye of MARG
Eye pattern will become difficult.
Many sampling eyes drive monitor within each cycle, by multiple phase places in a cycle sampled to data in a large number
Size of vertically opening on point is sampled, and needs to design exactly accurate phase rotation device, and eye of sampling opens the prison of monitor more
Survey is the most comprehensive, but its hardware design complexity is maximum.
Drive monitor due to one-dimensional eye the size of vertically opening of eye pattern can only be measured, and the eye based on MARG
Open the raising that monitor is limited to sample frequency for high data rate, eye of sampling drives monitor more needs exactly accurate phase place
Rotator and leggy point sampling, and two-dimentional eye opens the selection that monitor depends on template to the test of eye pattern, it can only be to setting
Fixed template is tested, and its test result can only illustrate whether given template can use, and final eye pattern needs to carry out in a large number
Template-setup and test job, waste time and energy.
Content of the invention
The technical problem to be solved in the present invention is that two-dimentional eye is opened the how obstructed oversampling clock of monitor and obtained with the synchronization of data
Take signal eye diagram, then can obtain optimum sampling moment, the information such as decision threshold level from eye pattern, these information are mainly
Embodied by the horizontal opening degree of eye pattern and vertical opening degree.Increased by noisiness with signal, level with
Vertical opening degree can reduce therewith.The invention reside in the level how measuring eye pattern opens size with vertical, i.e. eye pattern
Opening degree.The present invention, by comparing two methods with reference to clock cycle traversal and threshold line, simplifies method of testing and prison
View apparatus, its concrete scheme is as follows:
A kind of signal eye diagram testing method being applied to high-speed serializer/deserializer, comprises the steps:
S10, opens measurement clock using two with signal frequency identical eye and the eye pattern on set phase point is opened
Size is tested, and described two measurement clock adjustable phases are covered each by half period；
S20, is arranged threshold size and is distinguished with two orthogonal full-speed clock of frequency with signal by phase rotation device pair
Carry out phase shift operation in half period, realize the setting to measurement clock phase；
S30, judge set threshold size at measurement clock whether inside eye pattern, meet within eye pattern
Big threshold value is that the eye pattern at this clock phase point opens size；
S40, the eye pattern on each phase point is opened size result and is saved in depositor, is testing all phase points
Afterwards by the value sequential of depositor, the level having obtained signal eye diagram opens sizes values with vertical.
Another object of the present invention also resides in a kind of eye being applied to high-speed serializer/deserializer of offer and opens monitor dress
Put, comprising: threshold line test circuit, clock and threshold value setting circuit, setting depositor, finite state machine, result observation circuit
With test result depositor, wherein:
Threshold line test circuit, receives outside detected input signals and clock and arranges two threshold values of circuit output with threshold value
Signal and two eyes are opened measurement clock and to open size to the eye pattern on set phase point and test, and export corresponding
Test result；Described two eyes open measurement clock identical with frequency input signal and two measure clocks be covered each by half week
Phase；
Result observation circuit, the eye pattern receiving on each phase point of threshold line test circuit output opens size result simultaneously
Output；
Clock and threshold value arrange circuit, using phase rotation device pair and signal with frequency two orthogonal clocks respectively at half
Carry out the phase place setting that phase shift operation realizes measurement clock, and the size setting to threshold value in cycle；
Finite state machine, the phase place setting that clock and threshold value are arranged with threshold value and test clock in circuit is controlled, and
Output to result observation circuit is processed, and test result is saved in test result depositor；
Setting depositor, arranges the clock in circuit for the control signal of finite state machine is converted into clock with threshold value
Control signal with threshold value setting；
Test result depositor, opens size result for preserving the eye pattern on each phase point, and all having tested
By end value sequential after phase point, the level having obtained signal eye diagram opens sizes values with vertical.
Further, described clock and threshold value setting circuit include D/A converting circuit and phase rotation device, described setting
Depositor includes phase place setting depositor and voltage setting depositor；
Described phase rotation device is used in half period, measurement clock phase being configured and exporting；
Described D/A converting circuit is used for the size of threshold value is configured and exports；
Described phase place setting depositor connects phase rotation device, for the control signal of finite state machine is converted into measurement
The control signal of clock phase；
Described voltage setting depositor connects D/A converting circuit, for the control signal of finite state machine is converted into threshold
The control signal of value size setting.
Further, in described threshold line test circuit, the high level input of first comparator connects outside input number
According to its low-level input connects a threshold signal, and its outfan is simultaneously connected with the input of first, second d trigger, described
The outfan of the first d trigger connects an input of the first XOR gate, and the outfan of described first XOR gate connects a sr
One input of latch, the outfan of described 2nd d trigger connects an input of the second XOR gate, described second XOR
The outfan of door connects an input of the 2nd sr latch；The high level input of the second comparator connects outside input number
According to its low-level input connects another threshold signal, and its outfan is simultaneously connected with the input of the three, the 4th d triggers, institute
The outfan stating the 3rd d trigger connects another input of the first XOR gate, and the outfan of described 4th d trigger connects the
Another input of two XOR gates, the outfan of described first, second sr latch is connected to the input of limit state machine.
Further, described first and second comparator is made up of a Gilbert cell and two-stage prime amplifier.
Compared with prior art, the present invention is by the survey to eye pattern opening degree at each phase point in eye pattern a cycle
Examination, the superposition of each test result is obtained signal eye diagram.Compared with driving monitor with traditional two-dimentional eye, eye proposed by the present invention opens prison
Visual organ circuit arrangement has the simultaneously operating that need not carry out initial clock and data, test process setting and test result record by
Digital control module is automatically performed, and can obtain the feature that signal eye diagram in a cycle opens size information.
Brief description
Below in conjunction with the accompanying drawings the specific embodiment of the present invention is described in further detail.
Fig. 1 is that the eye of the embodiment of the present invention opens the structure chart of monitor.
Fig. 2 is that the eye of the embodiment of the present invention opens the circuit structure diagram of monitor.
Fig. 3 is the circuit structure diagram of the phase rotation device of the embodiment of the present invention.
Fig. 4 is the D/A converting circuit figure of the embodiment of the present invention.
Fig. 5 is the comparator circuit figure of the embodiment of the present invention.
Fig. 6 is the flow chart of the signal eye diagram testing method of the embodiment of the present invention.
Specific embodiment
In order that the objects, technical solutions and advantages of the present invention become more apparent, below in conjunction with drawings and Examples, right
The present invention is further elaborated.It should be appreciated that specific embodiment described herein is only in order to explain the present invention, and
It is not used in the restriction present invention.
Accompanying drawing 6 is the flow chart of the signal eye diagram testing method of the embodiment of the present invention: comprises the steps:
S10, opens measurement clock using two with signal frequency identical eye and the eye pattern on set phase point is opened
Size is tested, and described two measurement clocks are covered each by half period；
S20, arranges threshold size and in half period, measurement clock phase is configured；
S30, judge set threshold size at measurement clock whether inside eye pattern, meet within eye pattern
Big threshold value is that the eye pattern at this clock phase point opens size；
S40, the eye pattern on each phase point is opened size result and is saved in depositor, is testing all phase points
Afterwards by the value sequential of depositor, the level having obtained signal eye diagram opens sizes values with vertical.
When realizing signal eye diagram test, open measurement clock to set phase using two with signal frequency identical eye
Eye pattern on site is opened size and is tested, and two clocks are covered each by half period, are existed by four-quadrant phase rotation device
In half period, measurement clock phase is configured；Test circuit judges that set threshold size is at measurement clock
The no eye pattern that inside eye pattern, to meet max-thresholds within eye pattern be at this clock phase point opens size；By each
Eye pattern on phase point is opened size result and is saved in depositor by control circuit, will post after having tested all phase points
The value sequential of storage, the level just having obtained signal eye diagram opens sizes values with vertical.The present invention passes through finite state machine
Complete threshold line setting, test result preserves in a register, just can obtain test signal by reading the value in depositor
Eye pattern.
Accompanying drawing 1 is the structural representation that eye opens monitor one embodiment.As shown in figure 1, this eye opens monitor circuit by threshold
Value line test circuit 110 and control module 120 two large divisions composition.The output to control module 120 for the threshold line test circuit 110
Threshold signal vh and vl tests to input signal vin at given test clock signal clk_right and clk_left,
And export corresponding test result signal errorl and errorr.
The core of control module 120 is finite state machine 124.The phase place to threshold value and test clock for the finite state machine 124
Setting is controlled, and the output to result observation circuit is processed, and test result is saved in test result depositor 122
In.
The control signal of finite state machine 124 is converted into clock and threshold value in analog circuit 121 by setting depositor 123
The control signal of setting circuit.In order to complete the setting to test clock, in addition it is also necessary to external clock in addition to needing control signal
Input as reference clock, as shown in figure 1, signal i is the clock signal with input signal with frequency, but both phase places are not
There is the relation of determination, signal q is that signal i ' and signal q ' is signal i respectively with frequency and 90 degree of orthogonal clock signals with signal i
Inversion signal with signal q.After control module 120 completes all of threshold value setting and tests, test result depositor 122
In just save signal eye diagram in a cycle open information, now signal finish puts high level, represents that test completes.As
Fruit needs again the eye pattern of input signal to be tested, and makes signal reset set low level.
As shown in Fig. 2 giving specific circuit structure to the full custom module in Fig. 2.In Fig. 1 analog circuit 121
Clock is realized by two phase rotation devices 231 and D/A converting circuit 232 respectively with threshold value setting circuit.Phase rotation device 231
Four reference clock signals i, i ', q, q ' pairwise orthogonal, and with input signal vin with frequency.Phase place arranges depositor 222 basis
The value output quadrant selection signal 225 of the phase counter 227 that finite state machine 223 gives, selects in four reference clocks
Two as reference clock, by the phase place that weight control signal 226 makes output clock be located at two reference clocks selected it
Between.When the value of phase counter 227 is " 0 ", signal clk_left and signal clk_right and signal i has identical phase
Position；When the value of enumerator is maximum, signal clk_left and clk_right and i ' has identical phase place.The value of enumerator is every
Plus when " 1 ", the phase place of clk_left and clk_right moves left and right corresponding size respectively.
The phase place of clk_left and clk_right respectively takies half period, i.e. 180 degree, by phase rotation device by data
During center is moved to both sides, phase rotation device 231 will carry out reselecting of a reference clock, clock and quadrant
As shown in table 1, phase rotation device 231 quadrant is controlled corresponding relation by quadrant selection signal 225.
Table 1 clock and quadrant corresponding relation
| 0-90 degree | 90-180 degree | |
| clk_left | Fourth quadrant (iq ') | Third quadrant (i ' q ') |
| clk_right | First quartile (iq) | Second quadrant (i ' q) |
Because phase rotation device 231 is by the phase shift operation carrying out a cycle with signal with the full-speed clock of frequency, therefore,
Sampling clock original position signal i does not need to align with eye pattern center, is traveled through by clock is carried out with the phase shift of a cycle,
Can get the full detail of the eye pattern in a cycle.
Input data vin is relatively completed by two comparators 233 and 234 respectively with two threshold voltages.Data is continuous
Ground is compared with threshold signal vh and vl, and comparative result obtains at sampling clock threshold signal clk_left and clk_right
?.Comparator 233 is compared to vin and vh, when vin be more than vh when, comparator is output as high level, less than when, output low
Level；Comparator 234 is compared to vin and vl, and when vin is more than vl, comparator is output as high level, less than vl, exports
Low level.
D trigger 201 and d trigger 202 sampling vin and vh at clk_left and clk_right time point respectively
Comparative result；D trigger 203 and d trigger 204 sampling input data at clk_left and clk_right time point respectively
Comparative result with vl.Output signal sl_left of output signal sh_left of d trigger 201 and d trigger 203 is carried out
XOR, for increasing driving force, XOR result be have passed through and has just obtained in time point clk_ after two-stage phase inverter 209 and 210
Rub-out signal errorl at left, similar, can get rub-out signal errorr at time point clk_right.
Errorl or errorr is high level, illustrates that signal have passed through the threshold line being made up of vh and vl, otherwise signal is outside threshold line.
For high speed signal, the minimum pulse width of the errorl or errorr signal obtaining through oversampling circuit is picosecond magnitude, if
The sr latch 217,218 of two full custom of meter, during upon receipt of errorl or errorr for high level, corresponding sr latches
Device will export high level, until output is reset by finite state machine 223 when carrying out threshold line setting.
Finite state machine 223 is opened size to the eye at each phase point in a cycle successively and is measured, and will measure
Consequential signal is sequentially saved in test result depositor, all of measurement result is arranged in a cycle, just may be used
To obtain the level of signal eye diagram and the vertical information opening size.
Accompanying drawing 3 is phase rotation device 231 circuit structure diagram, and interpolation weight and quadrant control signal come from phase place setting and post
Storage 222.By suitably adjusting difference control line, tail currents are controlled, and to arrange the phase weights of input with this and to obtain
Obtain required interpolated phase.In order to produce uniform phase step, thus equably scanning the horizontal stretching degree of eye pattern, phase place is revolved
Turn the transmission characteristic of device, i.e. the relation between output phase place and input weight, should be linear.
In output rising edge clock position from initial clock to the left and right sides moving process, phase rotation device 231 need to enter
Quadrant adjustment of row, quadrant adjustment is controlled by the nmos being numbered n2_1 n2_4 in Fig. 3, the entitled pol of control line, its
Middle pol_i1 and pol_i0 controls the quadrant of i；Pol_q1 and pol_q0 controls the quadrant of q.Work as pol_i1=1, pol_i0=0
When, i road signal is just；Work as pol_i1=0, during pol_i0=1, i road signal is negative；Q road signal is similar with i road signal.Quadrant
As shown in table 2 with the corresponding relation of quadrant control bit, in table, control bit order is pol_i1-pol_i0-pol_q1-pol_q0:
Table 2 quadrant and control bit relation
| Quadrant | First quartile | Second quadrant | Third quadrant | Fourth quadrant |
| Control bit | 1010 | 0110 | 0101 | 1001 |
When input weight is 0, the rising edge of output clock is located at initial clock, with progressively adding of input weight
Greatly, output rising edge clock moves to the direction setting respectively.The size of step-length is by being that control weight number by inputting is determined
Fixed, if step-length setting is excessive, certainty of measurement is not high, and step-length setting is too small, then because of d trigger setup time
Limiting, needing multiple adjustment just can adopt required data, thus affecting measurement efficiency.The size of step-length, that is, input
The number of control weight should be determined according to the parameter of side circuit.
Accompanying drawing 4 is the circuit theory diagrams of D/A converting circuit 232, and it is that voltage is arranged the control that depositor 224 is given
Signal is converted to analogue signal, and in the present invention, output vh and vl of original state D/A converting circuit is common mode value, controls
Signal often adds " 1 ", and vh increases one step larger, vl one step-length of reduction.Voltage arrange depositor 224 be functionally similar to one volume
Code device, its input for control threshold value Counter Value, be output as some to difference control signal.When Counter Value is for complete zero,
The half of difference control signal is " 1 ", and half is " 0 ", and output vh and vl of D/A converting circuit is common mode value.With enumerator
Value often increase 1, in difference control signal, the number of " 1 " can increase one, and the number of " 0 " can reduce one.
The operation principle of D/A converting circuit is realized by control signal control electric current distribution.Circuit as shown in Figure 4
In, the size of vl in odd number mos management and control, and the size of vh in the management and control of even number mos.When in control signal, half is " 1 ",
When half is " 0 ", the electric current flowing through two resistance is identical, and now vh with vl value is identical, by the design of r value and tail current, makes
This value is common mode value；With the change of " 1 " " 0 " number, current value will be redistributed between two resistance, and its total value keeps not
Become.
Accompanying drawing 5 is the circuit diagram of the comparator of the present embodiment, and comparator 233,234 circuit are as shown in figure 5, by a gill
Bert unit and two-stage prime amplifier are constituted.Gilbert cell be output as the differential signal and the differential reference level that input it
Between difference, because this signal amplitude is too small, the input of rear class d trigger can not be directly used in it is therefore desirable to two-stage is pre-
Amplifier is amplified, to ensure that rear class d trigger can adopt correct signal amplitude.Every first stage amplifier employs identical
Active feedback structure, the band of this amplifier is wider than traditional difference amplifier bandwidth.
The present invention proposes and opens monitor circuit device for the eye measuring High Speed Eye Diagram, by one week of eye pattern
The test of eye pattern opening degree at each phase point in phase, the superposition of each test result is obtained signal eye diagram.With traditional two-dimentional eye
Drive monitor to compare, eye proposed by the present invention is opened monitor circuit device and had the synchronization behaviour that need not carry out initial clock and data
Make, test process setting is automatically performed by digital control module with test result record, can obtain signal eye diagram in a cycle
Open the feature of size information.
Last in addition it is also necessary to it is noted that listed above be only the present invention a specific embodiment.Obviously, the present invention
It is not limited to above example, can also have many deformation.Those of ordinary skill in the art can be straight from present disclosure
Connect all deformation derived or associate, be all considered as protection scope of the present invention.
Claims (5)
1. a kind of signal eye diagram testing method being applied to high-speed serializer/deserializer is it is characterised in that comprise the steps:
S10, opens measurement clock using two with signal frequency identical eye and opens size to the eye pattern on set phase point
Tested, described two measurement clock adjustable phases are covered each by half period；
S20, setting threshold size and by phase rotation device pair and signal with frequency two orthogonal full-speed clock respectively partly
Carry out phase shift operation in the individual cycle, realize the setting to measurement clock phase；
S30, judges that set threshold size is measuring at clock whether inside eye pattern, meets the maximum threshold within eye pattern
Value is that the eye pattern at this clock phase point opens size；
S40, the eye pattern on each phase point is opened size result and is saved in depositor, will after having tested all phase points
The value sequential of depositor, the level having obtained signal eye diagram opens sizes values with vertical.
2. a kind of eye being applied to high-speed serializer/deserializer opens monitor apparatus it is characterised in that including: threshold line test
Circuit, clock and threshold value setting circuit, setting depositor, finite state machine, result observation circuit and test result depositor, its
In:
Threshold line test circuit, receives outside detected input signals and clock and arranges two threshold signals of circuit output with threshold value
Open measurement clock with two eyes and to open size to the eye pattern on set phase point and test, and export corresponding test
Result；Described two eyes open measurement clock identical with frequency input signal and two measure clock adjustable phases be covered each by half
Cycle；
Result observation circuit, receives the eye pattern on each phase point of threshold line test circuit output and opens size result defeated
Go out；
Clock and threshold value arrange circuit, using phase rotation device pair and signal with frequency two orthogonal clocks respectively in half period
Inside carry out the phase place setting that phase shift operation realizes measurement clock, and the size setting to threshold value；
Finite state machine, the phase place setting that clock and threshold value are arranged with threshold value and test clock in circuit is controlled, and to knot
The output of fruit observation circuit is processed, and test result is saved in test result depositor；
Setting depositor, arranges clock and threshold in circuit for the control signal of finite state machine is converted into clock with threshold value
The control signal of value setting；
Test result depositor, opens size result for preserving the eye pattern on each phase point, and is testing all phase places
After point, end value sequential, the level having obtained signal eye diagram are opened sizes values with vertical.
3. eye according to claim 2 opens monitor apparatus it is characterised in that described clock is included with threshold value setting circuit
D/A converting circuit and phase rotation device, described setting depositor includes phase place setting depositor and voltage setting depositor；
Described phase rotation device is used in half period, measurement clock phase being configured and exporting；
Described D/A converting circuit is used for the size of threshold value is configured and exports；
Described phase place setting depositor connects phase rotation device, for the control signal of finite state machine is converted into measurement clock
The control signal of phase place；
Described voltage setting depositor connects D/A converting circuit, big for the control signal of finite state machine is converted into threshold value
The control signal of little setting.
4. eye according to claim 3 opens monitor apparatus it is characterised in that in described threshold line test circuit, and first
The high level input of comparator (233) connects outer input data, and its low-level input connects a threshold signal, its output
End is simultaneously connected with the input of first, second d trigger (201,202), and the outfan of a described d trigger (201) connects
One input of the first XOR gate (208), the outfan of described first XOR gate (208) connects a sr latch (217)
One input, the outfan of described 2nd d trigger (202) connects an input of the second XOR gate (205), and described second is different
The outfan of OR gate (205) connects an input of the 2nd sr latch (218)；The high level input of the second comparator (234)
End connects outer input data, and its low-level input connects another threshold signal, and its outfan is simultaneously connected with the three, the 4th d
The input of trigger (203,204), the outfan of described 3rd d trigger (203) connects the another of the first XOR gate (208)
Input, another input of outfan connection the second XOR gate (205) of described 4th d trigger (204), described first,
The outfan of the 2nd sr latch (217,218) is connected to the input of limit state machine.
5. eye according to claim 4 opens monitor apparatus it is characterised in that described first and second comparator (233,234)
It is made up of a Gilbert cell and two-stage prime amplifier.
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| CN107769806B (en) * | 2017-10-17 | 2019-11-22 | 清华大学 | On piece eye figure observation circuit based on the asymmetric variable formwork of two dimension in high-speed serial communication |
| CN111371491A (en) * | 2018-12-25 | 2020-07-03 | 苏州超锐微电子有限公司 | Method for detecting ten-gigabit Ethernet SerDes signal eye diagram |
| CN112748325A (en) * | 2020-12-29 | 2021-05-04 | 海光信息技术股份有限公司 | Eye pattern testing method, device and equipment |
| CN114325196A (en) * | 2021-12-31 | 2022-04-12 | 龙迅半导体（合肥）股份有限公司 | Signal test system |
| CN115065429B (en) * | 2022-06-10 | 2023-06-13 | 电子科技大学(深圳)高等研究院 | Eye pattern-based high-speed signal frequency testing method |
| CN117352034A (en) * | 2022-06-29 | 2024-01-05 | 长鑫存储技术有限公司 | Data input verification method and data input verification structure |
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