CN103926471A - Eye-open monitor device for high-speed serializer/deserializer and testing method - Google Patents
Eye-open monitor device for high-speed serializer/deserializer and testing method Download PDFInfo
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Abstract
The invention provides an eye-open monitor device. According to the eye-open monitor device, when signal eye pattern testing is achieved, two eye-open measuring clocks with identical frequency with signals are utilized to test opening sizes of an eye patterns on arranged phase points; threshold value sizes are set and the phases of the measuring clocks are set in half period; whether the set threshold value sizes are located inside the eye patterns at the positions of the measuring clocks is judged, and the largest threshold value inside the eye patterns is the open size of the eye patterns at a clock phase point; the open size results of the eye patterns at all the phase points are stored into registers, the values of the registers are arranged in sequence after all the phase points are tested, and the horizontal open size and the vertical open size of the signal eye patterns are obtained. Compared with the prior art, the eye-open monitor device has the advantages that synchronous operation of an initial clock and data is not needed, setting of a testing process and recording of testing results are completed automatically through a digital control module, and the information of open sizes of the signal eye patterns in one period can be obtained.
Description
Technical field
The present invention relates to the eye pattern test circuit design field of high-speed serializer/deserializer system high speed signal, be specially a kind of eye for high-speed serializer/deserializer and open monitor apparatus and method of testing.
Background technology
When serial data is transmitted in link, because system transmission total characteristic (comprising the characteristic of balanced device and channel) is undesirable, wave form distortion, the broadening of code element before and after causing, and make waveform above occur very long hangover, have influence on the sampling time of current code element, thereby the judgement to current code element causes interference, so-called intersymbol interference phenomenon that Here it is.Along with the lifting of data rate, intersymbol interference phenomenon is also more remarkable.The general data eye that adopts is weighed intersymbol interference amount.In serial link transmission system at a high speed, transmitting terminal adopts the Pseudo-random bit generator on sheet to produce cycle tests.At receiving end, open monitor acquisition for receiving obtaining by the eye on sheet of signal eye diagram.On sheet, eye is driven monitor can provide the size information of opening of eye pattern, or even complete eye pattern shape.
At present on sheet, eye is driven monitor and can be divided into one dimension eye and drive monitor, and two dimension eye is driven monitor, and the eye based on marginal date is driven monitor, and many sampling eyes are driven monitor.
One dimension eye is driven monitor the vertical opening degree of eye pattern is measured, and one dimension eye is opened the hardware spending minimum of monitor, but one dimension eye is driven monitor and can only monitor the vertical direction of eye pattern, cannot know the horizontal opening size of eye pattern.
Two dimension eye is driven monitor and in vertical and horizontal direction, eye pattern is monitored simultaneously.It is that template and data by being shaped as rectangle compare that two dimension eye is opened monitor basic thought, if test data has been passed template, think that corresponding template is disabled, do not superpose through the template of data all, just obtained final data eye.But when this circuit test, need to align with data center in the initial clock position of template, its alignment operation is by allowing test data realize through lag line.
Eye based on marginal date is opened the monitoring that monitor opens eye pattern and is realized by checking data edge, the monitoring at edge needs intensive sampling conventionally, the result obtaining is used histogram to represent, histogram is narrower, eye pattern is opened greatlyr, but in the time that data rate is too high, be subject to the restriction of sampling clock frequency, the eye of use based on marginal date opened monitor measurement eye pattern will become difficulty.
Many sampling eyes are driven monitor within each cycle, by a large amount of samplings, the size of vertically opening on multiple phase points in the one-period of data is sampled, need the very accurate phase rotation device of design, the monitoring that many sampling eyes are driven monitor is the most comprehensive, but its hardware design complexity maximum.
Because one dimension eye is driven monitor and can only be measured the size of vertically opening of eye pattern, and the raising of driving monitor and be limited to for high data rate sample frequency based on the eye of marginal date, many sampling eyes are driven monitor needs very accurate phase rotation device and leggy point sampling, and two dimension eye is opened monitor depends on template selection to the test of eye pattern, it can only be tested the template of setting, its test result can only illustrate whether given template can be used, final eye pattern need to carry out a large amount of template-setups and test job, wastes time and energy.
Summary of the invention
The technical problem to be solved in the present invention is that two dimension eye is opened the how obstructed oversampling clock of monitor and obtained signal eye diagram with synchronizeing of data, then from eye pattern, can obtain the optimum sampling moment, the information such as decision threshold level, if these information spinners embody with vertical opening degree by the horizontal opening degree of eye pattern.Along with signal is subject to the increasing of noisiness, level can reduce with vertical opening degree thereupon.The invention reside in level and the vertical size of opening, the i.e. opening degree of eye pattern how to measure eye pattern.The present invention, by conjunction with clock period traversal and relatively two kinds of methods of threshold line, has simplified method of testing and monitoring arrangement, and its concrete scheme is as follows:
A signal eye diagram testing method that is applied to high-speed serializer/deserializer, comprises the steps:
S10, uses two identical with signal frequency eyes to open to measure clock to open size to the eye pattern on set phase point and tests, and measures clocks and covers respectively half period for described two;
S20, arranges threshold size and arranges measuring clock phase in half period;
S30, judges that whether set threshold size measuring clock place in eye pattern inside, and the eye pattern that to meet at the max-thresholds of eye pattern inside be this clock phase point place is opened size;
S40, opens big or small result by the eye pattern on each phase point and is saved in register, the value of register is sequentially arranged testing after all phase points, has obtained the level and the vertical sizes values of opening of signal eye diagram.
Another object of the present invention is also to provide a kind of eye that is applied to high-speed serializer/deserializer to open monitor apparatus, comprise: threshold line test circuit, clock and threshold value setting circuit, register, finite state machine, result observation circuit and test result register are set, wherein:
Threshold line test circuit, receive two threshold signals of outside detected input signals and clock and threshold value setting circuit output and two eyes and open and measure clock signal and the eye pattern on set phase point is opened to size test, and export corresponding test result; Described two eyes open measure clock signal identical with frequency input signal and two measurement clocks cover respectively half period;
Result observation circuit, the eye pattern on each phase point of receive threshold line test circuit output is opened big or small result output;
Clock and threshold value setting circuit, in half period, to measuring, clock phase arranges and size setting to threshold value;
Finite state machine, controls the phase place setting of threshold value and test clock in clock and threshold value setting circuit, and the output of result observation circuit is processed, and test result is saved in test result register;
Register is set, for the control signal of finite state machine being converted into clock and the clock of threshold value setting circuit and the control signal of threshold value setting;
Test result register, opens big or small result for the eye pattern of preserving on each phase point, and end value is sequentially arranged testing after all phase points, has obtained the level and the vertical sizes values of opening of signal eye diagram.
Further, described clock and threshold value setting circuit comprise D/A converting circuit and phase rotation device, and the described register that arranges comprises that phase place arranges register and voltage arranges register;
Described phase rotation device for arranging and export measuring clock phase in half period;
Described D/A converting circuit is for arranging and export the size of threshold value;
Described phase place setting arranges register and connects phase rotation device, for the control signal of finite state machine being converted into the control signal of measuring clock phase;
Described voltage arranges register linking number analog conversion circuit, the control signal arranging for the control signal of finite state machine being converted into threshold size.
Further, in described threshold line test circuit, the high level input end of the first comparer connects outer input data, its low level input end connects a threshold signal, its output terminal connects the input end of first, second d type flip flop simultaneously, the output terminal of described the first d type flip flop connects an input end of the first XOR gate, the output terminal of described the first XOR gate connects an input end of a SR institute storage, the second output terminal of stating d type flip flop connect an input end of the second XOR gate, the output terminal of described the second XOR gate connects an input end of the 2nd SR institute storage; The high level input end of the second comparer connects outer input data, its low level input end connects another threshold signal, its output terminal connects the 3rd simultaneously, the input end of four d flip-flop, the output terminal of described 3d flip-flop connects another input end of the first XOR gate, the output terminal of described four d flip-flop connects another input end of the second XOR gate, and the output terminal of described first, second SR institute storage connects respectively the input end of finite state machine.
Further, described first and second comparer is made up of a Gilbert cell and two-stage prime amplifier.
Compared with prior art, the present invention, by the test to each phase point place eye pattern opening degree in eye pattern one-period, obtains signal eye diagram by each test result stack.Compared with driving monitor with traditional two dimension eye, the eye that the present invention proposes is opened monitor circuit device and is had without the synchronous operation of carrying out initial clock and data, test process setting and test result record is completed automatically by digital control module, can obtain signal eye diagram in one-period and open the feature of size information.
Brief description of the drawings
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in further detail.
Fig. 1 is the structural drawing that the eye of the embodiment of the present invention is driven monitor.
Fig. 2 is the circuit structure diagram that the eye of the embodiment of the present invention is driven monitor.
Fig. 3 is the circuit structure diagram of the phase rotation device of the embodiment of the present invention.
Fig. 4 is the D/A converting circuit figure of the embodiment of the present invention.
Fig. 5 is the comparator circuit figure of the embodiment of the present invention.
Fig. 6 is the process flow diagram of the signal eye diagram testing method of the embodiment of the present invention.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein, only in order to explain the present invention, is not intended to limit the present invention.
The process flow diagram of the signal eye diagram testing method that accompanying drawing 6 is the embodiment of the present invention: comprise the steps:
S10, uses two identical with signal frequency eyes to open to measure clock to open size to the eye pattern on set phase point and tests, and measures clocks and covers respectively half period for described two;
S20, arranges threshold size and arranges measuring clock phase in half period;
S30, judges that whether set threshold size measuring clock place in eye pattern inside, and the eye pattern that to meet at the max-thresholds of eye pattern inside be this clock phase point place is opened size;
S40, opens big or small result by the eye pattern on each phase point and is saved in register, the value of register is sequentially arranged testing after all phase points, has obtained the level and the vertical sizes values of opening of signal eye diagram.
In the time realizing signal eye diagram test, using two identical with signal frequency eyes to open to measure clock to open size to the eye pattern on set phase point tests, two clocks cover respectively half period, arrange in half period by four-quadrant phase rotation device to measuring clock phase; Test circuit is judged set threshold size and whether is being measured clock place in eye pattern inside, and the eye pattern that to meet at the max-thresholds of eye pattern inside be this clock phase point place is opened size; Eye pattern on each phase point is opened to big or small result and be saved in register by control circuit, the value of register is sequentially arranged testing after all phase points, just obtained the level and the vertical sizes values of opening of signal eye diagram.The present invention completes threshold line setting by finite state machine, and test result is kept in register, just can obtain the eye pattern of test signal by reading value in register.
Accompanying drawing 1 is the structural representation that eye is opened monitor one embodiment.As shown in Figure 1, this eye is opened monitor circuit and is made up of threshold line test circuit 110 and control module 120 two large divisions.Output threshold signal VH and the VL of threshold line test circuit 110 to control module 120 tests input signal VIN at given test clock signals CLK_RIGHT and CLK_LEFT place, and exports corresponding test result signal errorL and errorR.
The core of control module 120 is finite state machines 124.Finite state machine 124 is controlled the phase place setting of threshold value and test clock, and the output of result observation circuit is processed, and test result is saved in test result register 122.
Register 123 is set the control signal of finite state machine 124 is converted into clock in mimic channel 121 and the control signal of threshold value setting circuit.In order to complete the setting to test clock, except needs control signal, the input that also needs external clock is as with reference to clock, as shown in Figure 1, signal I is with clock signal frequently with input signal, but both phase places do not have definite relation, signal Q spends orthogonal clock signal with signal I with frequency and 90, and signal I ' and signal Q ' are respectively the inversion signals of signal I and signal Q.When control module 120 has completed after all threshold value settings and test, the information of opening of just having preserved signal eye diagram in one-period in test result register 122, now signal FINISH sets high level, represents to have tested.If need to again the eye pattern of input signal be tested, make signal RESET set low level.
As shown in Figure 2, the full customized module in Fig. 2 has been provided to concrete circuit structure.Clock in Fig. 1 mimic channel 121 and threshold value setting circuit are realized by two phase rotation devices 231 and D/A converting circuit 232 respectively.Four reference clock signal I, I ' of phase rotation device 231, Q, Q ' pairwise orthogonal, and frequently same with input signal VIN.Phase place arranges register 222 and selects signal 225 according to the value output quadrant of the given phase counter 227 of finite state machine 223, select two conducts in four reference clocks with reference to clock, make the phase place of output clock by weight control signal 226 between two selected reference clocks.In the time that the value of phase counter 227 is " 0 ", signal CLK_LEFT and signal CLK_RIGHT have identical phase place with signal I; In the time that the value of counter is maximum, signal CLK_LEFT and CLK_RIGHT have identical phase place with I '.When the value of counter often adds " 1 ", the phase place of CLK_LEFT and CLK_RIGHT moves left and right respectively corresponding size.
The phase place of CLK_LEFT and CLK_RIGHT respectively takies half period, i.e. 180 degree, in the process being moved to both sides by data center by phase rotation device, phase rotation device 231 will carry out reselecting of a reference clock, the corresponding relation of clock and quadrant is as shown in table 1, and phase rotation device 231 quadrants select signal 225 to control by quadrant.
Table 1 clock and quadrant corresponding relation
| ? | 0-90 degree | 90-180 degree |
| CLK_left | Fourth quadrant (IQ ') | Third quadrant (I ' Q ') |
| CLK_right | First quartile (IQ) | The second quadrant (I ' Q) |
Because phase rotation device 231 is by the phase shift operation of carrying out one-period with signal with full speed clock frequently, therefore, sampling clock reference position signal I does not need to align with eye pattern center, by clock being carried out to the phase shift traversal of one-period, can obtain the full detail of the eye pattern in one-period.
Being completed by two comparers 233 and 234 more respectively of input data VIN and two threshold voltages.Data compare with threshold signal VH and VL continuously, and comparative result obtains at sampling clock threshold signal CLK_LEFT and CLK_RIGHT place.Comparer 233 compares VIN and VH, and in the time that VIN is greater than VH, comparer is output as high level, while being less than, and output low level; Comparer 234 compares VIN and VL, and in the time that VIN is greater than VL, comparer is output as high level, is less than VL, output low level.
D type flip flop 201 and d type flip flop 202 are respectively at the comparative result of the sampling VIN of CLK_LEFT and CLK_RIGHT time point place and VH; D type flip flop 203 and d type flip flop 204 are respectively at the comparative result of CLK_LEFT and CLK_RIGHT time point place sampling input data and VL.The output signal SL_LEFT of the output signal SH_LEFT of d type flip flop 201 and d type flip flop 203 is carried out to XOR, for strengthening driving force, by XOR result through just having obtained the rub-out signal errorL at time point CLK_LEFT place after two-stage phase inverter 209 and 210, similarly, can obtain the rub-out signal errorR at time point CLK_RIGHT place.ErrorL or errorR are high level, illustrate that signal has passed the threshold line being made up of VH and VL, otherwise signal are outside threshold line.
For high speed signal, the minimum pulse width of the errorL obtaining through oversampling circuit or errorR signal is picosecond magnitude, design the SR latch 217,218 of two full customizations, be high level once receive errorL or errorR, corresponding SR latch will be exported high level, until finite state machine 223 is carrying out when threshold line arranges exporting zero clearing.
Finite state machine 223 is opened size to the eye at the each phase point place in one-period successively and is measured, and measurement signals is saved in test result register according to the order of sequence, all measurement results are arranged in one-period, and the level that just can obtain signal eye diagram is opened big or small information with vertical.
Accompanying drawing 3 is phase rotation device 231 circuit structure diagrams, and interpolation weight and quadrant control signal come from phase place register 222 is set.By suitably regulating difference control line, hangover electric current is controlled, and the phase weights of input is set and obtains required interpolation phase place with this.In order to produce uniform phase step, thereby scan equably the horizontal stretching degree of eye pattern, the transport property of phase rotation device, that is, the relation between output phase and input weight, should be linear.
In output clock rising edge position from initial clock to the left and right sides moving process, phase rotation device 231 need carry out a quadrant adjustment, the NMOS that quadrant adjustment is N2_1-N2_4 by the label in Fig. 3 controls, and control line name is called POL, and wherein POL_I1 and POL_I0 control the quadrant of I; POL_Q1 and POL_Q0 control the quadrant of Q.Work as POL_I1=1, when POL_I0=0, I road signal is for just; Work as POL_I1=0, when POL_I0=1, I road signal is for negative; Q road signal and I road class signal are seemingly.The corresponding relation of quadrant and quadrant control bit is as shown in table 2, and in table, control bit order is POL_I1-POL_I0-POL_Q1-POL_Q0:
Table 2 quadrant and control bit relation
| Quadrant | First quartile | The second quadrant | Third quadrant | Fourth quadrant |
| Control bit | 1010 | 0110 | 0101 | 1001 |
In the time that input weight is 0, the rising edge of output clock is positioned at initial clock place, and along with the progressively increasing of input weight, output clock rising edge moves to the direction of setting respectively.The size of step-length is by being to be determined by the control weight number inputted, and excessive if step-length arranges, measuring accuracy is not high, step-length arranges too small, may be due to the d type flip flop restriction of Time Created, need to repeatedly adjust and just can adopt needed data, thereby efficiency is measured in impact.The size of step-length, namely the number of the control weight of input should be determined according to the parameter of side circuit.
Accompanying drawing 4 is the circuit theory diagrams of D/A converting circuit 232, it is voltage to be arranged to the control signal that register 224 provides be converted to simulating signal, in the present invention, output VH and the VL of original state D/A converting circuit are common mode value, control signal often adds " 1 ", VH increases a step-length, and VL reduces a step-length.The function class that voltage arranges register 224 is similar to a scrambler, and it is input as the Counter Value of controlling threshold value, is output as some to difference control signal.In the time that Counter Value is complete zero, the half of difference control signal is " 1 ", and half is " 0 ", and the output VH of D/A converting circuit and VL are common mode value.Along with the every increase 1 of value of counter, in difference control signal, the number of " 1 " can increase one, and the number of " 0 " can reduce one.
The principle of work of D/A converting circuit is distributed and is realized by control signal control electric current.In circuit, the size of VL in the control of odd number metal-oxide-semiconductor as shown in Figure 4, and the size of VH in the control of even number metal-oxide-semiconductor.When half in control signal is " 1 ", when half is " 0 ", the electric current that flows through two resistance is identical, and now VH is identical with VL value, and by the design of R value and tail current, making this value is common mode value; Along with the variation of " 1 " " 0 " number, current value will be redistributed between two resistance, and its total value remains unchanged.
The circuit diagram of the comparer that accompanying drawing 5 is the present embodiment, comparer 233,234 circuit as shown in Figure 5, are made up of a Gilbert cell and two-stage prime amplifier.Gilbert cell is output as the difference between differential signal and the difference datum of input, because this signal amplitude is too small, can not be directly used in the input of rear class d type flip flop, therefore need two-stage prime amplifier to amplify, to ensure that rear class d type flip flop can adopt correct signal amplitude.Every one-level amplifier has adopted identical active feedback structure, and the band of this amplifier is wider than traditional differential amplifier bandwidth.
The eye the present invention proposes for measuring High Speed Eye Diagram is opened monitor circuit device, by the test to each phase point place eye pattern opening degree in eye pattern one-period, each test result stack is obtained to signal eye diagram.Compared with driving monitor with traditional two dimension eye, the eye that the present invention proposes is opened monitor circuit device and is had without the synchronous operation of carrying out initial clock and data, test process setting and test result record is completed automatically by digital control module, can obtain signal eye diagram in one-period and open the feature of size information.
Finally, it is also to be noted that, what more than enumerate is only a specific embodiment of the present invention.Obviously, the invention is not restricted to above embodiment, can also have many distortion.All distortion that those of ordinary skill in the art can directly derive or associate from content disclosed by the invention, all should think protection scope of the present invention.
Claims (5)
1. a signal eye diagram testing method that is applied to high-speed serializer/deserializer, is characterized in that, comprises the steps:
S10, uses two identical with signal frequency eyes to open to measure clock to open size to the eye pattern on set phase point and tests, and measures clocks and covers respectively half period for described two;
S20, arranges threshold size and arranges measuring clock phase in half period;
S30, judges that whether set threshold size measuring clock place in eye pattern inside, and the eye pattern that to meet at the max-thresholds of eye pattern inside be this clock phase point place is opened size;
S40, opens big or small result by the eye pattern on each phase point and is saved in register, the value of register is sequentially arranged testing after all phase points, has obtained the level and the vertical sizes values of opening of signal eye diagram.
2. the eye that is applied to high-speed serializer/deserializer is opened a monitor apparatus, it is characterized in that, comprising: threshold line test circuit, clock and threshold value setting circuit, register, finite state machine, result observation circuit and test result register are set, wherein:
Threshold line test circuit, receive two threshold signals of outside detected input signals and clock and threshold value setting circuit output and two eyes and open and measure clock signal and the eye pattern on set phase point is opened to size test, and export corresponding test result; Described two eyes open measure clock signal identical with frequency input signal and two measurement clocks cover respectively half period;
Result observation circuit, the eye pattern on each phase point of receive threshold line test circuit output is opened big or small result output;
Clock and threshold value setting circuit, in half period, to measuring, clock phase arranges and size setting to threshold value;
Finite state machine, controls the phase place setting of threshold value and test clock in clock and threshold value setting circuit, and the output of result observation circuit is processed, and test result is saved in test result register;
Register is set, for the control signal of finite state machine being converted into clock and the clock of threshold value setting circuit and the control signal of threshold value setting;
Test result register, opens big or small result for the eye pattern of preserving on each phase point, and end value is sequentially arranged testing after all phase points, has obtained the level and the vertical sizes values of opening of signal eye diagram.
3. eye according to claim 2 is opened monitor apparatus, it is characterized in that, described clock and threshold value setting circuit comprise D/A converting circuit and phase rotation device, and the described register that arranges comprises that phase place arranges register and voltage arranges register;
Described phase rotation device for arranging and export measuring clock phase in half period;
Described D/A converting circuit is for arranging and export the size of threshold value;
Described phase place setting arranges register and connects phase rotation device, for the control signal of finite state machine being converted into the control signal of measuring clock phase;
Described voltage arranges register linking number analog conversion circuit, the control signal arranging for the control signal of finite state machine being converted into threshold size.
4. eye according to claim 3 is opened monitor apparatus, it is characterized in that, in described threshold line test circuit, the high level input end of the first comparer (233) connects outer input data, its low level input end connects a threshold signal, its output terminal connects first simultaneously, the second d type flip flop (201, 202) input end, the output terminal of described the first d type flip flop (201) connects an input end of the first XOR gate (208), the output terminal of described the first XOR gate (208) connects an input end of a SR institute storage (217), the second output terminal of stating d type flip flop (202) connect an input end of the second XOR gate (205), the output terminal of described the second XOR gate (205) connects an input end of the 2nd SR institute storage (218), the high level input end of the second comparer (234) connects outer input data, its low level input end connects another threshold signal, its output terminal connects the 3rd simultaneously, the input end of four d flip-flop (203,204), the output terminal of described 3d flip-flop (203) connects another input end of the first XOR gate (208), the output terminal of described four d flip-flop (204) connects another input end of the second XOR gate (205), and the output terminal of described first, second SR institute storage (217,218) connects respectively the input end of finite state machine.
5. eye according to claim 4 is opened monitor apparatus, it is characterized in that, described first and second comparer (233,234) is made up of a Gilbert cell and two-stage prime amplifier.
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| CN108414822A (en) * | 2016-12-21 | 2018-08-17 | 联发科技股份有限公司 | A kind of signal quality detection circuit and method |
| CN107769806A (en) * | 2017-10-17 | 2018-03-06 | 清华大学 | Eye pattern observation circuit on piece based on the asymmetric variable formwork of two dimension in high-speed serial communication |
| CN107769806B (en) * | 2017-10-17 | 2019-11-22 | 清华大学 | On piece eye figure observation circuit based on the asymmetric variable formwork of two dimension in high-speed serial communication |
| CN111371491A (en) * | 2018-12-25 | 2020-07-03 | 苏州超锐微电子有限公司 | Method for detecting ten-gigabit Ethernet SerDes signal eye diagram |
| CN112748325A (en) * | 2020-12-29 | 2021-05-04 | 海光信息技术股份有限公司 | Eye pattern testing method, device and equipment |
| CN114325196A (en) * | 2021-12-31 | 2022-04-12 | 龙迅半导体（合肥）股份有限公司 | Signal test system |
| CN115065429A (en) * | 2022-06-10 | 2022-09-16 | 电子科技大学(深圳)高等研究院 | High-speed signal frequency testing method based on eye pattern |
| CN115065429B (en) * | 2022-06-10 | 2023-06-13 | 电子科技大学(深圳)高等研究院 | Eye pattern-based high-speed signal frequency testing method |
| WO2024000910A1 (en) * | 2022-06-29 | 2024-01-04 | 长鑫存储技术有限公司 | Data input verification method and data input verification structure |
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