CN111371491A

CN111371491A - Method for detecting ten-gigabit Ethernet SerDes signal eye diagram

Info

Publication number: CN111371491A
Application number: CN201811587632.7A
Authority: CN
Inventors: 濮国亮; 沈寒冰; 吴俊辉
Original assignee: Suzhou Supereal Microelectronics Co ltd
Current assignee: Suzhou Supereal Microelectronics Co ltd
Priority date: 2018-12-25
Filing date: 2018-12-25
Publication date: 2020-07-03

Abstract

The invention provides a method for detecting an eye pattern of a gigabit Ethernet SerDes signal, which is a detection method for detecting jitter of transmitted differential data by using a plurality of 3.125G frequency clocks with different phases, detecting the amplitude range of the differential data, and comparing the detected value with the jitter and the amplitude range of a preset eye pattern to judge whether the eye pattern of the 10G SerDes signal meets the standard or not.

Description

Method for detecting ten-gigabit Ethernet SerDes signal eye diagram

Technical Field

A method for ten-gigabit Ethernet SerDes signal eye diagram detection.

Background

In recent years, as the CMOS process continues to evolve along moore's law, the feature size is reduced to below 10nm, so the CPU processing capability of PCs and handheld devices is greatly improved, and in addition, the common application of optical fiber networks makes the requirement for data transmission rate between system chips continuously increase, so that the serializer/deserializer (SerDes) technology gets more and more attention, the transmission rate of SerDes is also higher and higher, from 1Gbps to 2.5Gbps to 5Gbps, and the transmission rate of the latest commercial optical fiber transmission chip is up to 10 Gbps. However, with the continuous improvement of the transmission rate, the corresponding chip testing cost is higher and higher, the ordinary gigabit SerDes chip needs a special testing instrument to test indexes such as signal eye diagrams, and for the gigabit Ethernet SerDes chip, an ultra-high-speed ultra-precise instrument is needed to test various performances, which greatly increases the development cost for chip development.

Based on the above, the method for detecting the eye diagram of the ten-gigabit Ethernet SerDes signal is provided, the method is embedded in an analog circuit, the eye diagram range of the high-speed signal is tested while the signal is sent, whether the eye diagram of the signal meets the requirement or not is calculated through a digital special algorithm, and the method can be carried out without a special testing instrument, so that the testing and system development cost of a 10G Ethernet SerDes chip is greatly reduced.

Disclosure of Invention

A method for gigabit ethernet SerDes signal eye detection, the method comprising the steps of:

1. selecting 16 clock signals with similar phases by using 64 different phase clocks with the frequency of 3.125G and a data transmission clock, wherein the 16 clock signals are similar in phase to the data transmission clock, and sampling the transmitted data signal value in each clock period through the 16 clock signals;

2. detecting the amplitude of the differential sending data, and judging whether the signal amplitude is greater than a preset value;

3. data eye detection state machine samples each cycle through 40960 clock cycles

The 16-bit data is processed by special algorithm to detect 40960 clock cycles

And whether the eye pattern of the data meets the requirement of a preset value or not.

Drawings

The subject matter regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the patent application. The invention, however, both as to organization and method of operation, together with objects, features, and advantages thereof, may best be understood by reference to the following detailed description when read with the accompanying drawings.

FIG. 1 is a block diagram of a method for ten-gigabit Ethernet SerDes signal eye diagram detection;

fig. 2 is a state transition diagram of the data eye detection state machine.

Detailed Description

In the following detailed description, specific details are set forth in order to provide a thorough understanding of the invention. However, one skilled in the art will recognize that the invention may be practiced with other similar details.

A method for detecting an eye diagram of a gigabit Ethernet SerDes signal mainly comprises the following implementation steps as shown in FIG. 1, starting from step 101, generating 64 3.125G different phase clocks by a PLL, each phase difference being 5ps, performing phase fitting with a SerDes differential data transmission clock, finding 16 clock signals with the phase closest to the data transmission clock from the 64 phase clocks CKI 1-CK 164, sampling data by using the 16 clock signals, going to step 102, converting the differential transmission data into single-ended signals through an analog circuit, converting the single-ended signals into digital level signals through a level conversion circuit, going to step 103, performing data jitter detection according to the 16-bit sampling data and actual transmission data generated in step 101, going to step 104, judging whether the amplitude of the transmission signal is larger than a preset threshold value according to the amplitude detection of the transmission data signal, going to step 105, and judging whether the current signal eye diagram meets the standard or not according to the jitter range and the amplitude range.

Combining the working state of the state machine shown in fig. 2, the state machine starts to be in 201 initial state, presetting each eye diagram threshold value, entering 202 state, comparing the signal jitter range of the current clock period with the preset threshold value, then entering 203 state, judging whether the signal jitter range is larger than the preset threshold value, if the signal jitter range is larger than the preset threshold value, entering 208 state, considering that the eye diagram is not in accordance with the requirement, completing detection, if the signal jitter range is smaller than the preset threshold value, then entering 205 state, judging whether the signal jitter range is larger than the preset threshold value, if the signal jitter range is larger than the preset threshold value, then entering 208 state, considering that the eye diagram is not in accordance with the requirement, completing detection, if the signal jitter range is smaller than the preset threshold value, entering 206 state, judging whether the current detection period counter reaches 40960 period values, if the required period number is not reached, entering 202 state, continuing detection, if the current detection has reached, and (4) considering that the current signal eye pattern meets the required standard, and finishing the detection.

While the description herein describes certain features of the invention and one implementation, many modifications, substitutions, changes, and equivalents will now occur to those skilled in the art. Therefore, the protection scope of the present invention is subject to the scope of the appended claims.

Claims

1. A method for gigabit ethernet SerDes signal eye detection, the method comprising the steps of:

(1) selecting 16 clock signals with similar phases by using 64 different phase clocks with the frequency of 3.125G and a data transmission clock, wherein the 16 clock signals are similar in phase to the data transmission clock, and sampling the transmitted data signal value in each clock period through the 16 clock signals;

(2) detecting the amplitude of the differential sending data, and judging whether the signal amplitude is greater than a preset value;

(3) and the data eye pattern detection state machine carries out special algorithm processing on the 16-bit data sampled in each period through 40960 clock periods to detect whether the eye pattern of the data meets the requirement of a preset value in 40960 clock periods.