TWI668970B - Measurement system and data transmission interface - Google Patents

Abstract

A measurement system for a data transmission interface includes a signal generator, a signal receiver, and a data transmission interface. The signal generator transmits the input data to the data transmission interface. The signal receiver receives the output data from the data transmission interface. The signal receiver measures the anti-jitter capability of the data transmission interface based on the error report data in the output data. The data transmission interface includes a receiving circuit, a synchronization circuit, and a transmitting circuit. The receiving circuit is configured to receive the input data and generate a bit error signal when the data error occurs. The synchronization circuit receives the error signal to generate a bit error indication signal. The transmitting circuit is configured to send the output data to the signal receiver, and receive the error indication signal when the data error occurs, and generate an error return data according to the error indication signal.

Description

Measurement system and data transmission interface

The present disclosure relates to a measurement system and a data transmission interface, and more particularly to a measurement system and a data transmission interface for anti-jitter capability.

In the Data Transmission Interface, jitter refers to the deviation of the expected value of the periodic signal from time. Since some jitter is unavoidable, there is a need for a modern data transmission interface to exhibit some jitter tolerance and still meet performance requirements. In fact, many industry standards require that the data transfer interface have a minimum jitter tolerance (Jitter Tolerance) measured against different metrics. Therefore, manufacturers, researchers, engineers, and end users are very concerned about the anti-jitter capability of the data transfer interface or wafer and its measurement methods. Traditionally, there has been a measurement method for the anti-jitter capability of the data transmission interface, that is, the measurement device is used to transmit the jitter and output data to the data transmission interface, and then the output of the data transmission interface is analyzed to determine the minimum jitter of the data transmission interface. Tolerance, as an assessment of its anti-jitter capability.

However, traditionally lower-order measurement devices are mostly unable to measure the data transmission interface during clock domain crossing operations. Anti-jitter capability, especially anti-jitter capability at high frequency operation. In addition, although the high-order measurement equipment can measure the anti-jitter capability of the data transmission interface in the operation of the clock domain crossing, the price is relatively expensive, which is not affordable for the general measurement unit.

Therefore, how to reduce the cost of the measuring device, and at the same time, can effectively measure the anti-jitter capability of the data transmission interface during clock domain crossing operation, especially the anti-jitter capability at high frequency, which is One of the problems of improvement.

An embodiment of the present disclosure provides a measurement system for a data transmission interface, including a signal generator, a signal receiver, and a data transmission interface. The signal generator is coupled to the data transmission interface for transmitting the input data to the data transmission interface. The signal receiver is coupled to the data transmission interface for receiving output data from the data transmission interface, wherein the signal receiver measures the anti-jitter capability of the data transmission interface according to the error report data in the output data. The data transmission interface includes a receiving circuit, a synchronization circuit, and a transmitting circuit. The receiving circuit is coupled to the signal generator. The receiving circuit operates on the first clock signal to receive the input data and generate a bit error signal when the data error occurs. The synchronization circuit is coupled to the receiving circuit. The synchronization circuit receives the error signal to generate a bit error indication signal. The transmitting circuit is coupled to the synchronization circuit, the receiving circuit, and the signal receiver. The transmitting circuit operates on the second clock signal to send the output data to the signal receiver, and receives the error indication signal when the data error occurs, and generates an error report data according to the error indication signal.

Another embodiment of the present disclosure provides a data transmission medium The surface is coupled to the signal generator and the signal receiver, and the data transmission interface includes a receiving circuit, a synchronization circuit, and a transmitting circuit. The receiving circuit is coupled to the signal generator. The receiving circuit operates on the first clock signal for receiving input data from the signal generator and generating a bit error signal when the data error occurs. The synchronization circuit is coupled to the receiving circuit. The synchronization circuit receives the error signal to generate a bit error indication signal. The transmitting circuit is coupled to the synchronization circuit, the receiving circuit, and the signal receiver. The transmitting circuit operates on the second clock signal for transmitting the output data to the signal receiver. The transmitting circuit receives the error indication signal when the data error occurs, and generates an error report data according to the error indication signal to output the data.

Therefore, the embodiment of the present invention reduces the cost of the measurement system by providing a measurement system and a data transmission interface, and particularly a measurement method and a measurement system for the jitter tolerance of the system chip. In the case of synchronization, the anti-jitter capability of the data transmission interface is effectively measured, and the anti-jitter capability of the data transmission interface is effectively measured when the output data is high frequency.

1, 1A‧‧‧ measurement system

12‧‧‧Signal Generator

14‧‧‧Signal Receiver

16, 16A‧‧‧ data transmission interface

162‧‧‧ receiving circuit

164‧‧‧Synchronous circuit

166‧‧‧Transmission circuit

168, 160‧‧‧ data conversion circuit

1680‧‧‧Series

1602‧‧‧Deserturizer

1604‧‧‧ Clock and data recovery circuit

CLK1, CLK2‧‧‧ clock signal

Do, Do(s), Do(p)‧‧‧ output data

Di, Di(s), Di(p)‧‧‧ Input data

200‧‧‧Measured waveform

SI, SI1‧‧‧ error indication signal

SE, SE1‧‧‧ error signal

FD‧‧‧Error report data

Do1, Do2, Do3, Do4‧‧‧ Information

Di1, Di2, Di3, Di4‧‧‧ data

400‧‧‧Shake Tolerance Chart

JTC-S‧‧‧ standard measuring line

JTC-T‧‧‧Best measuring line

CT‧‧‧ data comparison table

Dr1 to Dr9‧‧‧Reply information

1640‧‧‧Pre-stage circuit

1642‧‧‧Intermediate circuit

1644‧‧‧After-level circuit

T1, T2, T3, T4‧‧‧D type flip-flops

XOR1, XOR2‧‧‧ Mutual exclusion or gate

Enable1, Enable2‧‧‧Enable Signal

The above and other objects, features, advantages and embodiments of the present invention will become more <RTIgt; 2 is a schematic diagram of a measurement waveform according to some embodiments of the present disclosure; FIG. 3 is a data comparison table according to some embodiments of the present disclosure; 4 is experimental data of a jitter tolerance chart according to some embodiments of the present disclosure; FIG. 5 is a schematic diagram of another measurement system according to some embodiments of the present disclosure; Figure 6 is a schematic diagram of a synchronization circuit in accordance with some embodiments of the present disclosure.

Please refer to Figure 1. 1 is a schematic diagram of a measurement system 1 depicted in accordance with some embodiments of the present disclosure. The measurement system 1 includes a data transmission interface 16, a signal generator 12, and a signal receiver 14. The data transmission interface 16 is coupled to the signal generator 12 and the signal receiver 14 respectively. In addition, as shown, the data transmission interface 16 includes a receiving circuit 162, a synchronization circuit 164, and a transmitting circuit 166, wherein the receiving circuit 162 and the transmitting circuit 166 operate on different Non-common clocks, respectively. In the connection relationship, the receiving circuit 162 is coupled to the signal generator 12. The synchronization circuit 164 is coupled to the receiving circuit 162. The transmitting circuit 166 is coupled to the synchronization circuit 164 and the signal receiver 14. The measurement system 1 shown in FIG. 1 is only an example, and the present invention is not limited thereto.

In order to make the operation mode of the measurement system 1 shown in FIG. 1 easy to understand, FIG. 2 is a schematic diagram of a measurement waveform 200 according to some embodiments of the present disclosure. Please refer to FIG. 1 and FIG. 2 together. The operation mode of the measurement system 1 will be described in detail later in conjunction with the above two figures.

In the operational relationship, the signal generator 12 is used to transmit a load The input data Di with the dither signal is given to the data transmission interface 16. The receiving circuit 162 of the data transmission interface 16 is activated by the enable signal Enable1 for receiving the pen input data Di and determining whether the pen input data Di is correct. In addition, the transmitting circuit 166 of the data transmission interface 16 is activated by the enable signal Enable2 for sending an output data Do to the signal receiver 14. In the foregoing, when the pen input data Di received by the receiving circuit 162 is determined to be correct, the transmitting circuit 166 correspondingly generates a correct output data Do to the signal receiver 14. At this time, the signal receiver 14 can know that the data transmission interface 16 is not affected by the jitter signal.

Next, the signal generator 12 transmits the second input data Di carrying the strong jitter signal to the data transmission interface 16. If the second input data Di is determined to be correct, the transmission circuit 166 correspondingly generates the second stroke. The correct output data Do is sent to the signal receiver 14. On the other hand, if the second input data Di is determined to be incorrect, the transmitting circuit 166 generates the output data Do carrying the error report data FD to the signal receiver 14. In this way, the signal receiver 14 can measure the minimum jitter tolerance and anti-jitter capability of the data transmission interface 16 according to the received output data Do.

Further, when an error occurs in the input data Di of the pen carrying the dither signal, the receiving circuit 162 generates the error signal SE and sends the error signal SE to the synchronizing circuit 164. The synchronization circuit 164 further generates the error indication signal SI according to the error signal SE, and transmits the error indication signal SI to the transmitting circuit 166 to notify the transmitting circuit 166 that the input data Di carrying the jitter signal has an error. According to this, the transmitting circuit 166 generates the output resource carrying the error report data FD according to the notification of the error indication signal SI. The material Do is sent to the signal receiver 14 with the output data Do carrying the error report data FD.

In this way, the signal receiver 14 can measure the minimum jitter tolerance and anti-jitter capability of the data transmission interface 16 according to the output data Do of the error report data FD.

It should be noted that the receiving circuit 162 operates on the first clock signal CLK1, and the transmitting circuit 166 operates in the second clock signal CLK2. In some embodiments, synchronization circuit 164 operates based on clock domain crossing (CDC). The synchronization circuit 164 is configured to receive the error signal SE from the receiving circuit 162 according to the first clock signal CLK1, and output the error indication signal SI to the transmitting circuit 166 according to the second clock signal CLK2. As such, the synchronization circuit 164 serves as a bridge for synchronous communication between the receiving circuit 162 and the transmitting circuit 166. In some embodiments, the first clock signal CLK1 and the second clock signal CLK2 are clock signals of different phases of the same frequency or clock signals of different frequencies. It should be noted that the receiving circuit 162 and the transmitting circuit 166 perform cooperative operation according to the data comparison table, so that the anti-jitter capability of the data transmission interface 16 can be effectively measured when the operating clock is not synchronized, which will be followed. The details are described in the examples.

In some embodiments, the signal generator 12, the signal receiver 14, the receiving circuit 162, and the transmitting circuit 166 each have the same data comparison table CT (see FIG. 3). In some embodiments, the signal generator 12 generates an input data Di carrying the dithered signal based on the internal data comparison table CT. In some embodiments, the receiving circuit 162 in the data transmission interface 16 compares the internal data comparison table after receiving the pen input data Di. The CT and the input data Di are used to determine whether the received input data Di is correct, and generate a error signal SE when a data error occurs. In the foregoing, if the input data Di is determined to be correct, the transmitting circuit 166 generates a correct output data Do according to the internal data comparison table CT, and sends the correct output data Do to the signal receiver 14. The signal receiver 14 compares the internal data comparison table CT with the correct output data Do to measure the ability of the data transmission interface 16 to resist the jitter signal.

If the input data Di is determined to be incorrect, the transmitting circuit 166 receives the error indication signal SI from the synchronization circuit 164, and loads the error report data FD into the output data Do according to the notification of the error indication signal SI. It becomes an erroneous output data Do, which in turn transmits the erroneous output data Do to the signal receiver 14. Thus, the signal receiver 14 detects that the data transmission interface 16 does not have the ability to resist the jitter signal based on the erroneous output data Do, which is also referred to as the minimum jitter tolerance of the data transmission interface 16.

For example, the signal generator 12, the signal receiver 14, the receiving circuit 162, and the data comparison table CT in the transmitting circuit 166 include at least one set of data D1 to D9, wherein the data D1 to D9 are 11, 22, 33, respectively. 44...99. The signal generator 12 generates an input data Di containing the data Di1 to Di9 and carrying the jitter signal according to the data data D1 to D9 in the internal data comparison table CT, wherein the data Di1 to Di9 are 11, 22, 33, 44, respectively... 99. The receiving circuit 162 receives the pen input data Di from the signal generator 12 and performs arithmetic processing to generate a piece of reply data Dr1 to Dr9. Then, the receiving circuit 162 compares and operates the pen reply data Dr1 to Dr9. The data data D1 to D9 of the data comparison table CT are compared to determine whether the reply data Dr1 to Dr9 completely match the data data D1 to D9 of the data comparison table CT.

After comparison, if the reply data Dr1 to Dr9 completely match the data D1 to D9 of the data comparison table CT, the transmitting circuit 166 will generate a complete matching data in the CT according to the internal data comparison table CT. The output data Do to D9 is sent to the signal receiver 14. The signal receiver 14 compares the internal data comparison table CT with the pen output data Do to measure the ability of the data transmission interface 16 to resist the jitter signal.

In addition, if the response value Dr4 in the response data Dr1 to Dr9 is "45", the value "44" of the data D4 in the data comparison table CT is not matched, and the receiving circuit 162 may generate an error. The code signal SE1 transmits the error signal SE1 to the synchronization circuit 164. In some embodiments, the error signal SE1 includes a message that the reply value Dr4 in the reply data Dr1 to Dr9 is an error material.

The data data D1-D9 in the foregoing data comparison table CT may be a pseudo-random binary sequence pattern (PRBS Pattern). At this time, the receiving circuit 162 may repeatedly generate and output according to the data comparison table CT. The pseudo-random test code. In addition, the pseudo-random test code is not the only option. Any code that can be used as the high-speed stream test code can be used as the data data D1-D9 in the data comparison table CT, for example, K28.5, 1010, CJPAT, and the like.

The synchronization circuit 164 receives the error according to the first clock signal CLK1. The code signal SE1 is informed that a data error has occurred in the reply value Dr4 in the reply data Dr1 to Dr9. Then, the synchronization circuit 164 outputs the error indication signal SI1 to the transmitting circuit 166 according to the second clock signal CLK2 to notify the transmitting circuit 166 that a data error has occurred at the receiving circuit 162. It is worth mentioning that due to the circuit characteristics of the synchronization circuit 164, there may be a time delay between the error signal SE1 and the error indication signal SI1. Therefore, considering the delay in the foregoing time, the transmitting circuit 166, after knowing that the data of the reply value Dr4 has occurred, loads the error report data FD into one of the data Do4 to Do9 of the output data Do according to the internal data comparison table CT. It becomes the wrong output data Do. The transmitting circuit 166 can immediately load the error report data FD into the data Do4 of the output data Do for the best case, and only considers the delay factor in the operation, the transmitting circuit 166 loads the error report data FD into the data Do5 of the output data Do to the data. One of the Do9s can also provide the signal receiver 14 to measure the minimum jitter tolerance and anti-jitter capability of the data transmission interface 16.

In the foregoing, one of the data Do4 to Do9 carrying the error report data FD is significantly different from one of the corresponding D4 to D9 in the data comparison table CT. For example, the data Do4 containing the error report data FD is "88", which is significantly different from the "44" of the data D4, or the data Do5 containing the error report data FD is "99", and the data The "55" of the data D5 has a significant difference.

Thus, the transmitting circuit 166 loads the error report data FD into the data Do5 in the output data Do according to the error indication signal SI1, so that the data Do5 is significantly different from the data data D5 of the data comparison table CT, thereby enabling the signal receiver 14 to It is easy to judge the occurrence of data errors. for example, In the data comparison table CT of the signal generator 12, the signal receiver 14, the receiving circuit 162, and the transmitting circuit 166, the data D4 is "44", and the reply value Dr4 generated by the receiving circuit 162 is "45". The transmitting circuit 166 can send the output data Do of the data Do4 of "88" or the output data Do of the data Do5 of "99".

In this way, when the signal receiver 14 receives the output data Do, the signal receiver 14 can more easily determine that the data Do4 or the data Do5 in the output data Do has an error. That is to say, the user can easily determine whether the output data Do of the data transmission interface 16 has a data error by using the lower-level signal receiver 14, and indirectly measure the minimum jitter tolerance and anti-jitter capability of the data transmission interface 16. Thereby reducing the cost of the signal receiver 14.

Please refer to Figure 4. 4 is an experimental data plot of a jitter tolerance graph 400, depicted in accordance with some embodiments of the present disclosure. The horizontal axis of the experimental data graph represents the jitter operating frequency (Hz) of the input signal Di, and the vertical axis represents the jitter signal strength contained in the input signal Di, the unit of which is the unit interval, and the experimental data map can be received by the signal receiver 14. According to the output data Do, it is used to explain the minimum jitter tolerance and anti-jitter capability of the data transmission interface 16 under different frequency operating conditions. Moreover, the standard measurement line JTC-S in the experimental data map represents the anti-jitter capability that the data transmission interface 16 basically needs to achieve under each jitter operation frequency condition. The optimal measurement line JTC-T in the experimental data plot represents the minimum jitter tolerance that the data transmission interface 16 can achieve at each jitter operating frequency.

In detail, the signal generator 12 operates at a jitter of 90 kHz. Under the frequency condition, the jitter signal of intensity 100 (mUI) is loaded into the input data Di and transmitted to the data transmission interface 16. The signal receiver 14 receives the output data Do sent from the data transmission interface 16 according to the above manner, and determines whether the output data Do is correct. At this time, if it is correct, the experimental data map shows that the data transmission interface 16 can correctly process the input data Di having a jittering operation frequency of 90 KHz and a jitter signal strength of 100 (mUI). The shaded portion indicates the extent to which the data transfer interface 16 can properly process the input data Di. That is, in the case where the jitter frequency of the input data Di is 90 kHz, the anti-jitter capability of the data transmission interface 16 ranges from 100 mUI to 75 UI, and the minimum jitter tolerance of the data transmission interface 16 is 75 UI. The input data Di of the remaining frequencies is deduced by analogy.

Thus, by viewing the experimental data presented in the experimental data map, it is possible to determine whether the data transmission interface 16 is measured by the anti-jitter capability based on whether the optimal measurement line JTC-T is superior to the standard measurement line JTC-S.

Please refer to Figure 5. Figure 5 is a schematic illustration of another measurement system 1A, depicted in accordance with some embodiments of the present disclosure. In some embodiments, the data transfer interface 16A further includes a first data conversion circuit 160. The first data conversion circuit 160 is coupled to the signal generator 12 and the receiving circuit 162. The first data conversion circuit 160 receives the serial input data Di(s) from the signal generator 12, converts the serial input data Di(s) into parallel input data Di(p), and transmits the parallel input data Di(p). The receiving circuit 162 is provided.

In some embodiments, the data transfer interface 16A further includes a second data conversion circuit 168. The second data conversion circuit 168 is coupled to the signal receiver 14 and the transmission circuit 166. Second data conversion circuit 168 from the transmitting circuit 166 receives the parallel output data Do(p), converts the parallel output data Do(p) into the serial output data Do(s), and transmits the serial output data Do(s) to the signal receiver 14.

In some embodiments, the first data conversion circuit 160 further includes a Deserializer 1602. The deserializer 1602 is configured to convert the serial input data Di(s) into a parallel input data Di(p). In some embodiments, the second data conversion circuit 168 further includes a serializer 1680. The serializer 1680 is used to convert the parallel output data Do(p) into the serial output data Do(s).

In some embodiments, the first data conversion circuit 160 further includes a clock and data recovery circuit 1604 (CDR). The clock and data recovery circuit 1604 is configured to reply to the input data Di and to reply to the clock of the input data Di.

In some embodiments, the data transmission interface 16, 16A includes a computer bus (PCIe), a universal serial bus (USB), a serial computer bus (SATA), a mobile industry processor interface (MiPi physical), and an Ethernet (ether), high-definition multimedia interface (HDMI), digital video interface (DisplayPort) or universal bus (Thunderbolt).

Please refer to Figure 6 for the picture in Figure 6. Figure 6 is a schematic diagram of a synchronization circuit in accordance with some embodiments of the present disclosure. The synchronization circuit 164 is a pulse synchronization circuit (Pulse Synchronizer), which can synchronize the pulse signal (for example, the error signal SE) in the time domain operation of the first clock signal CLK1 to the time domain of the second clock signal CLK2 (for example). , error indication signal SI). The synchronization circuit 164 includes a pre-stage circuit 1640, a mid-level circuit 1642, and a post-stage circuit 1644. In the foregoing, the pre-stage circuit 1640 includes a D-type positive The inverter T1 and the exclusive OR gate XOR1, the intermediate circuit 1642 includes intermediate D-type flip-flops T2, T3, and the subsequent circuit 1644 includes a D-type flip-flop T4 and a mutual exclusion gate or gate XOR2. As shown in FIG. 6, the pre-stage circuit 1640 operates in the first clock signal CLK1 time domain to transmit the error signal SE to the intermediate circuit 1642. The intermediate circuit 1642 operates in the time domain of the second clock signal CLK2 to forward the error signal SE to the subsequent stage circuit 1644. The subsequent stage circuit 1644 operates in the time domain of the second clock signal CLK2 to convert the error signal SE into the error indication signal SI.

As described above, in the embodiment of the present invention, the synchronization circuit 164 used by the data transmission interface 16, 16A of the present invention is based on the clock domain crossing (CDC) operation, and receives the error signal SE according to the first clock signal CLK1. And outputting the error indication signal SI according to the second clock signal CLK2, thereby serving as a bridge for synchronous communication between the receiving circuit 162 and the transmitting circuit 166. Thus, the measurement system 1, 1A of the present invention is not affected by the asynchronous operation of the receiving circuit 162 and the transmitting circuit 166, and can still effectively measure the anti-jitter capability of the data transmission interfaces 16, 16A.

In addition, the synchronization circuit 164 used by the data transmission interface 16, 16A of the present invention can synchronously notify the transmission circuit 166 when a data error occurs in the reception circuit 162, so that the transmission circuit 166 can generate and output the output data Do carrying the error report data FD to The signal receiver 14 is operative to make it easier for the signal receiver 14 to determine that a data error has occurred in the receiving circuit 162. Relatively speaking, the measurement personnel can easily measure the anti-jitter capability of the data transmission interface 16, 16A by using the less accurate signal receiver 14, thereby reducing the cost of the signal receiver 14. Furthermore, as can be seen from Fig. 4, the measurement system 1, 1A and the data transmission interface 16, 16A of the present case are even at the output. When the data Di is high frequency, the anti-jitter capability of the data transmission interface 16, 16A can also be effectively measured.

It can be seen from the above embodiments of the present invention that the embodiment of the present invention reduces the measurement system by providing a measurement system and a data transmission interface, and particularly a measurement method and a measurement system for the jitter tolerance of the system wafer. The cost is to effectively measure the anti-jitter capability of the data transmission interface when the clock is not synchronized, and to effectively measure the anti-jitter capability of the data transmission interface when the output data is high frequency.

In addition, the above examples include exemplary steps in sequence, but the steps are not necessarily performed in the order shown. Performing these steps in a different order is within the scope of the present disclosure. Such steps may be added, substituted, altered, and/or omitted as appropriate within the spirit and scope of the embodiments of the present disclosure.

Although the present disclosure has been disclosed in the above embodiments, it is not intended to limit the disclosure, and any person skilled in the art can make various changes and refinements without departing from the spirit and scope of the disclosure. The scope of protection of the disclosure is subject to the definition of the scope of the patent application.

Claims (18)

A data transmission interface measuring system includes: a signal generator coupled to a data transmission interface for transmitting an input data to the data transmission interface; and a signal receiver coupled to the data transmission interface for The data transmission interface receives an output data, wherein the signal receiver measures the anti-jitter capability of the data transmission interface according to an error report data in the output data; wherein the data transmission interface comprises: a receiving circuit, The synchronization circuit is coupled to the first clock signal for receiving the input data, and generates an error signal when the data error occurs; a synchronization circuit coupled to the receiving circuit, the synchronization The circuit receives the error signal to generate an error indication signal; and a transmitting circuit coupled to the synchronization circuit, the receiving circuit and the signal receiver, the transmitting circuit operating on a second clock signal for The output data is sent to the signal receiver, and the error indication signal is received when the data error occurs, and the signal is indicated according to the error code. The error reporting data is generated in the data, wherein the synchronization circuit is based on a clock domain crossing (CDC), and receives the error signal according to the first clock signal, and outputs the error signal according to the second clock signal. Error indication signal. The measurement system of claim 1, wherein the first clock signal and the second clock signal are clock signals of different phases in the same frequency or clock signals of different frequencies. The measurement system of claim 1, wherein the signal generator, the signal receiver, the receiving circuit, and the transmitting circuit each have the same data comparison table. The measurement system of claim 3, wherein the signal generator generates the input data according to the data comparison table. The measurement system of claim 3, wherein the receiving circuit operates the input data to generate a reply data, and the receiving circuit compares the data comparison table with the reply data, and generates the data error Error signal. The measurement system of claim 3, wherein the transmitting circuit outputs the output data according to the data comparison table, and generates the error report data in the output data when a data error occurs. The measurement system of claim 1, wherein the data transmission interface further comprises: a first data conversion circuit coupled to the signal generator and the receiving The circuit, the first data conversion circuit receives a series of input data from the signal generator, converts the serial input data into a parallel input data, and sends the parallel input data to the receiving circuit. The measurement system of claim 7, wherein the data transmission interface further comprises: a second data conversion circuit coupled to the signal receiver and the transmitting circuit, the second data conversion circuit receiving a signal from the transmitting circuit Parallel output data, and convert the parallel output data into a series of output data, and send the serial output data to the signal receiver. The measurement system of claim 1, wherein the data transmission interface comprises a computer bus (PCIe), a universal serial bus (USB), a serial computer bus (SATA), and a mobile industry processor interface (MiPi physical ), ether, high-definition multimedia interface (HDMI), digital video interface (DisplayPort) or universal bus (Thunderbolt). A data transmission interface, coupled to a signal generator and a signal receiver, the data transmission interface includes: a receiving circuit coupled to the signal generator, the receiving circuit operating in a first clock signal for The signal generator receives an input data and generates an error signal when the data error occurs; a synchronization circuit is coupled to the receiving circuit, and the synchronization circuit receives the error a signal signal for generating an error indication signal; and a transmitting circuit coupled to the synchronization circuit, the receiving circuit and the signal receiver, the transmitting circuit operating on a second clock signal for transmitting an output data to The signal receiver receives the error indication signal when a data error occurs, and generates an error report data according to the error indication signal, wherein the synchronization circuit is based on a time domain (clock domain) The CDC is configured to receive the error signal according to the first clock signal, and output the error indication signal error signal according to the second clock signal. The data transmission interface of claim 10, wherein the first clock signal and the second clock signal are clock signals of different phases in the same frequency or clock signals of different frequencies. The data transmission interface of claim 10, wherein the signal generator, the signal receiver, the receiving circuit and the transmitting circuit each have the same data comparison table. The data transmission interface of claim 10, wherein the signal generator generates the input data according to the data comparison table. The data transmission interface of claim 10, wherein the receiving circuit operates the input data to generate a reply data, and the receiving circuit compares the data comparison table with the reply data and the data error The error signal is generated when it occurs. The data transmission interface of claim 10, wherein the transmitting circuit outputs the output data according to the data comparison table, and generates the error report data in the output data when a data error occurs. The data transmission interface of claim 10, further comprising: a first data conversion circuit coupled to the signal generator and the receiving circuit, wherein the first data conversion circuit receives a serial input from the signal generator Data, and converting the serial input data into a parallel input data, and sending the parallel input data to the receiving circuit. The data transmission interface of claim 10, further comprising: a second data conversion circuit coupled to the signal receiver and the transmitting circuit, the second data conversion circuit receiving a parallel output data from the transmitting circuit, and Converting the parallel output data into a series of output data, and sending the serial output data to the signal receiver. The data transmission interface as claimed in claim 10, comprising a computer bus (PCIe), a universal serial bus (USB), a serial computer bus (SATA), a mobile industry processor interface (MiPi physical), and an Ethernet ( Ether), high-definition multimedia interface (HDMI), digital video interface (DisplayPort) or universal bus (Thunderbolt).