TWI740564B - Cross-clock-domain signal transmitting method, circuit, and electronic apparatus thereof - Google Patents

Abstract

The present disclosure relates to a cross-clock-domain signal transmitting method, a circuit, and an electronic apparatus thereof. The method includes: receiving an initial interrupt signal in a fast clock domain; detecting an edge of the initial interrupt signal by an edge detection module and generating an event trigger signal; transforming the event trigger signal into an edge signal by a flip circuit; synchronizing the edge signals into a slow clock domain for generating an synchronizing signal; generating a trigger interrupt signals based on the synchronizing signal by a circuit, thus s several trigger interrupt signals are avoided while the interrupt signal transmits between the fast clock domain and the slow clock domain, and a system becomes more stable.

Description

Cross-clock domain signal transmission method, circuit and electronic device

The invention relates to a signal transmission method, a circuit and an electronic device across clock domains.

Circuits and systems usually have circuits that work in different clock domains. For example, the circuits of a processor usually work in the fast clock domain, while other circuits located around the processor usually work in the slow clock domain. When the interrupt signal is transferred between different clock domains, it needs to be converted by a synchronization circuit. Among them, when the interrupt signal is transmitted from the fast clock domain to the slow clock domain, multiple trigger signals are generated in the slow clock domain or the trigger signal is lost, which causes the system to repeatedly perform the reset operation or not to perform the reset operation.

The main purpose of the present invention is to provide a cross-clock domain signal transmission method, circuit and electronic device, aiming to solve the abnormal problem of the signal from the fast clock domain to the slow clock domain in the prior art.

A cross-clock domain signal transmission method. The cross-clock domain signal transmission method includes: receiving an initial interrupt signal in a fast clock domain; using an edge detection module to perform edge detection on the initial interrupt signal in the fast clock domain and combining Generating an event trigger signal; using a flip circuit to convert the event trigger signal into an edge signal in the fast clock domain; A synchronization circuit is used to synchronize the edge signal to the slow clock domain and generate a synchronization signal; and an edge fetch circuit is used to generate a trigger interrupt signal in the slow clock domain according to the synchronization signal.

In addition, in order to achieve the above objective, the present invention also proposes a cross-clock domain signal transmission circuit; the cross-clock domain signal transmission circuit includes: an edge detection module for edge detection and conversion of the initial interrupt signal in the fast clock domain Is an event trigger signal; the event trigger signal is a single pulse signal; a flip circuit is used to convert the event trigger signal into an edge signal; a synchronization circuit is used to synchronize the edge signal to the slow clock domain and Generate a synchronization signal; an edge-fetching circuit for generating a trigger interrupt signal in the slow clock domain according to the synchronization signal.

In addition, in order to achieve the above-mentioned object, the present invention also provides an electronic device in which at least one instruction is stored, and when the at least one instruction is executed by a processor, the following steps are implemented: receiving an initial interrupt signal in the fast clock domain; Use an edge detection module to perform edge detection on the initial interrupt signal in the fast clock domain and generate an event trigger signal; use a flip circuit to convert the event trigger signal into an edge signal in the fast clock domain; use a synchronization circuit The edge signal is synchronized to the slow clock domain and a synchronization signal is generated; an edge fetching circuit is used to generate a trigger interrupt signal in the slow clock domain according to the synchronization signal.

The above-mentioned cross-clock domain signal transmission method, circuit and electronic device convert the interrupt signal into a single pulse signal, synchronize the single pulse signal to the slow clock domain and generate a trigger interrupt signal, It can avoid the generation of multiple trigger interrupt signals when the interrupt signal is transmitted between the fast clock domain and the slow clock domain, so as to ensure the stability of the system.

1: Cross-clock domain signal transmission circuit

2: target circuit

10: Edge detection module

20: Pulse synchronization module

11: The first trigger

13: second trigger

15: The first logic circuit

21: Flip circuit

23: Synchronous circuit

25: Take edge circuit

210: Multiplexer

213: Third Trigger

231: Fourth Trigger

232: Fifth Trigger

251: Sixth Trigger

252: second logic circuit

CLK_A: the first clock signal

CLK_B: second clock signal

S10-S14: steps

FIG. 1 is a schematic diagram of a cross-clock domain signal transmission circuit according to a preferred embodiment of the present invention.

FIG. 2 is a timing diagram of the initial interrupt signal, the first clock signal, and the event trigger signal in FIG. 1.

FIG. 3 is a flowchart of a cross-clock domain signal transmission method according to a preferred embodiment of the present invention.

In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be described clearly and completely in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only It is a part of the embodiments of the present invention, but not all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of the present invention.

The terms "first", "second", and "third" in the description of the present invention and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific sequence. In addition, the term "including" and any variations of them are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or modules is not limited to the listed steps or modules, but optionally includes steps or modules that are not listed, or optional The ground also includes other steps or modules inherent to these processes, methods, products, or equipment.

The specific implementation manner of the present invention based on the cross-clock domain signal transmission circuit will be described below with reference to the accompanying drawings.

Please refer to FIG. 1, which is a circuit diagram of a cross-clock domain signal transmission circuit 1 according to a preferred embodiment of the present invention. The cross-clock domain signal transmission circuit 1 is applied to an electronic device with multiple clock domains. The cross-clock domain signal transmission circuit 1 can synchronize the primary interrupt signal from the fast clock domain to the slow clock domain and generate a trigger interrupt signal to the target circuit 2. The cross-clock domain signal transmission circuit 1 includes an edge detection module 10 and a pulse synchronization module 20. In at least one embodiment of the present invention, the edge detection module 10 and the pulse synchronization module 20 may be installed in the same integrated circuit, or may be installed in different integrated circuits.

Please also refer to FIG. 2, the edge detection module 10 works in the fast clock domain. The edge detection module 10 performs edge detection on the initial interrupt signal and converts it into an event trigger signal. In at least one embodiment of the present invention, the event trigger signal is a single pulse signal. The edge detection module 10 includes a first flip-flop 11, a second flip-flop 13 and a first logic circuit 15. The signal input terminal D of the first flip-flop 11 receives the initial interrupt signal, the clock signal terminal CLK of the first flip-flop 11 receives the first clock signal CLK_A, and the output terminal Q of the first flip-flop 11 respectively It is electrically connected to the second flip-flop 13 and the first logic circuit 15. The signal input terminal D of the second flip-flop 13 is electrically connected to the output terminal Q of the first flip-flop 11, and the clock signal terminal CLK of the second flip-flop 13 receives the first clock signal CLK_A. The output terminal Q of the second flip-flop 13 is electrically connected to the inverting input terminal of the first logic circuit 15. The forward input terminal of the first logic circuit 15 is electrically connected to the output terminal Q of the first flip-flop 11, and the inverting input terminal of the first logic circuit 15 is connected to the output terminal of the second flip-flop 13 The terminal Q is electrically connected, and the output terminal OUT of the first logic circuit 15 is electrically connected to the pulse synchronization module 20. In at least one embodiment of the present invention, the first logic circuit 15 is a logical AND gate (AND); the first clock signal CLK_A is a fast clock signal. FIG. 2 shows the timing of the preliminary interrupt signal L_int, the first clock signal CLK_A, and the event trigger signal E_trigger Sequence diagram. The preliminary interrupt signal L_int is active at high level, and the event trigger signal E_trigger is a single pulse signal.

The pulse synchronization module 20 is electrically connected to the edge detection module 10. The pulse synchronization module 20 is used to synchronize the event trigger signal from the fast clock domain to the slow clock domain and generate a trigger interrupt signal. The pulse synchronization module 20 includes a flip circuit 21, a synchronization circuit 23 and an edge fetching circuit 25.

The flip circuit 21 works in the fast clock domain. The flip circuit 21 is used to convert the event trigger signal into an edge signal. The flip circuit 21 includes a multiplexer 210 and a third flip-flop 213. The input terminal of the multiplexer 210 is electrically connected to the output terminal OUT of the first logic circuit 15, and the output terminal of the multiplexer 210 is electrically connected to the input terminal D of the third flip-flop 213. The clock terminal CLK of the third flip-flop 213 receives the first clock signal CLK_A, and the output terminal Q of the third flip-flop 213 is electrically connected to the synchronization circuit 23.

The synchronization circuit 23 works in the slow clock domain. The synchronization circuit 23 is used to synchronize the edge signal to the slow clock domain and generate a synchronization signal. The synchronization circuit 23 includes a fourth flip-flop 231 and a fifth flip-flop 232. The input terminal D of the fourth flip-flop 231 is electrically connected to the output terminal Q of the third flip-flop 213, the clock terminal CLK of the fourth flip-flop 231 receives the second clock signal CLK_B, and the fourth trigger The output terminal Q of the switch 231 is electrically connected to the input terminal D of the fifth trigger 232. The clock terminal CLK of the fifth flip-flop 232 receives the second clock signal CLK_B, and the output terminal of the fifth flip-flop 232 is electrically connected to the edge fetching circuit 25. In at least one embodiment of the present invention, the second clock signal CLK_B is a slow clock signal. The frequency of the first clock signal CLK_A is higher than the frequency of the second clock signal CLK_B.

The edge fetching circuit 25 works in the slow clock domain. The edge fetching circuit 25 is used to generate a trigger interrupt signal in the slow clock domain according to the synchronization signal. The edge fetching circuit 25 includes a sixth flip-flop 251 and a second logic circuit 252. The input terminal D of the sixth flip-flop 251 and the The output terminal Q of the fifth flip-flop 232 is electrically connected, the clock terminal CLK of the sixth flip-flop 251 receives the second clock signal CLK_B, and the output terminal Q of the sixth flip-flop 251 is connected to the second The second input terminal of the logic circuit 252 is electrically connected. The first input terminal of the second logic circuit 252 is electrically connected to the output terminal Q of the fifth flip-flop 232. In at least one embodiment of the present invention, the second logic circuit 252 is an exclusive OR gate.

Using the above-mentioned cross-clock domain signal transmission circuit 1, the edge detection module 10 is used to convert the interrupt signal into a single pulse signal, and the pulse synchronization module 20 is used to synchronize the single pulse signal to the slow clock domain and generate a trigger interrupt signal to avoid interruption. When the signal is transmitted between the fast clock domain and the slow clock domain, multiple trigger interrupt signals are generated to ensure the stability of the system.

Please refer to FIG. 3, which is a flowchart of a signal transmission method across clock domains, which is applied to the signal transmission circuit 1 across clock domains. The cross-clock domain signal transmission method includes the following steps: S10, receiving an initial interrupt signal in the fast clock domain.

S11. Use an edge detection module to perform edge detection on the initial interrupt signal in the fast clock domain and generate an event trigger signal.

In at least one embodiment of the present invention, the event trigger signal is a single pulse signal. The edge detection module 10 includes a first flip-flop 11, a second flip-flop 13 and a first logic circuit 15. The signal input terminal D of the first flip-flop 11 receives the initial interrupt signal, the clock signal terminal CLK of the first flip-flop 11 receives the first clock signal CLK_A, and the output terminal Q of the first flip-flop 11 respectively It is electrically connected to the second flip-flop 13 and the first logic circuit 15. The signal input terminal D of the second flip-flop 13 is electrically connected to the output terminal Q of the first flip-flop 11, the clock signal terminal CLK of the second flip-flop 13 receives the first clock signal CLK_A, and the second flip-flop 13 receives the first clock signal CLK_A. The output terminal Q of the second flip-flop 13 is electrically connected to the inverting input terminal of the first logic circuit 15. The forward input terminal of the first logic circuit 15 is electrically connected to the output terminal Q of the first flip-flop 11, and the inverting input terminal of the first logic circuit 15 is connected to the output terminal of the second flip-flop 13 end Q is electrically connected, and the output terminal OUT of the first logic circuit 15 is electrically connected to the pulse synchronization module 20. In at least one embodiment of the present invention, the first logic circuit 15 is a logic AND gate (AND); the first clock signal CLK_A is a fast clock signal. FIG. 2 is a timing diagram of the preliminary interrupt signal L_int, the first clock signal CLK_A, and the event trigger signal E_trigger. The preliminary interrupt signal L_int is active at high level, and the event trigger signal E_trigger is a single pulse signal.

S12. Use a flip circuit to convert the event trigger signal into an edge signal in the fast clock domain.

In at least one embodiment of the present invention, the flip circuit 21 includes a multiplexer 210 and a third flip-flop 213. The input terminal of the multiplexer 210 is electrically connected to the output terminal OUT of the first logic circuit 15, and the output terminal of the multiplexer 210 is electrically connected to the input terminal D of the third flip-flop 213. The clock terminal CLK of the third flip-flop 213 receives the first clock signal CLK_A, and the output terminal Q of the third flip-flop 213 is electrically connected to the synchronization circuit 23.

S13. Use a synchronization circuit to synchronize the edge signal to the slow clock domain and generate a synchronization signal.

In at least one embodiment of the present invention, the synchronization circuit 23 includes a fourth flip-flop 231 and a fifth flip-flop 232. The input terminal D of the fourth flip-flop 231 is electrically connected to the output terminal Q of the third flip-flop 213, the clock terminal CLK of the fourth flip-flop 231 receives the second clock signal CLK_B, and the fourth trigger The output terminal Q of the switch 231 is electrically connected to the input terminal D of the fifth trigger 232. The clock terminal CLK of the fifth flip-flop 232 receives the second clock signal CLK_B, and the output terminal of the fifth flip-flop 232 is electrically connected to the edge fetching circuit 25. In at least one embodiment of the present invention, the second clock signal CLK_B is a slow clock signal. The frequency of the first clock signal CLK_A is higher than the frequency of the second clock signal CLK_B.

S14. Use an edge fetching circuit to generate a trigger interrupt signal in the slow clock domain according to the synchronization signal.

In at least one embodiment of the present invention, the input terminal D of the sixth flip-flop 251 is electrically connected to the output terminal Q of the fifth flip-flop 232, and the clock terminal CLK of the sixth flip-flop 251 receives all With regard to the second clock signal CLK_B, the output terminal Q of the sixth flip-flop 251 is electrically connected to the second input terminal of the second logic circuit 252. The first input terminal of the second logic circuit 252 is electrically connected to the output terminal Q of the fifth flip-flop 232. In at least one embodiment of the present invention, the second logic circuit 252 is an exclusive OR gate.

In the above-mentioned cross-clock domain signal transmission method, the interrupt signal of the edge detection module 10 is converted into a single pulse signal, and the pulse synchronization module 20 is used to synchronize the single pulse signal to the slow clock domain and generate a trigger interrupt signal, which can avoid the interrupt signal in Multiple trigger interrupt signals are generated during the transfer between the fast clock domain and the slow clock domain to ensure the stability of the system.

It should be noted that for the foregoing method embodiments, for the sake of simple description, they are all expressed as a series of action combinations, but those skilled in the art should know that the present invention is not limited by the described sequence of actions. Because according to the present invention, certain steps can be performed in other order or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present invention.

In the several embodiments provided in this application, it should be understood that the disclosed device can be implemented in other ways. For example, the device embodiments described above are only illustrative, for example, the division of the modules is only a logical function division, and there may be other divisions in actual implementation, for example, multiple modules or elements may be combined or It can be integrated into another system, or some features can be ignored or not implemented. On the other hand, the displayed or discussed mutual coupling The combined or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or modules, and may be in electrical or other forms.

The modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical modules, that is, they may be located in one place, or they may be distributed to multiple networks. On the road module. Some or all of the modules may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.

In addition, the functional modules in the various embodiments of the present invention may be integrated into one processor, or each module may exist alone physically, or two or more modules may be integrated into one module. The above-mentioned integrated modules can be implemented either in the form of hardware or in the form of software functional modules.

If the integrated module is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on this understanding, the technical solution of the present invention essentially or the part that contributes to the existing technology or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium. It includes a number of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the method described in each embodiment of the present invention.

It should also be noted that in this article, the terms "include", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements , And also include other elements not explicitly listed, or elements inherent to the process, method, article, or device. If there are no more restrictions, the element defined by the sentence "includes a..." does not exclude the existence of other identical elements in the process, method, article, or device that includes the element.

As mentioned above, the above embodiments are only used to illustrate the technical solutions of the present invention, but not to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: The technical solutions recorded in the embodiments are modified, or some of the technical features thereof are equivalently replaced; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

In summary, the present invention meets the requirements of an invention patent, and Yan filed a patent application in accordance with the law. However, the above are only the preferred embodiments of the present invention. For those who are familiar with the technique of this case, equivalent modifications or changes made in accordance with the creative spirit of this case should be included in the scope of the following patent applications.

S10-S14: steps

Claims (10)

A cross-clock domain signal transmission method. The cross-clock domain signal transmission method includes: receiving an initial interrupt signal in a fast clock domain; using an edge detection module to perform edge detection on the initial interrupt signal in the fast clock domain and combining Generate an event trigger signal; use a flip circuit to convert the event trigger signal into an edge signal in the fast clock domain; use a synchronization circuit to synchronize the edge signal to a slow clock domain and generate a synchronization signal; use an edge fetching circuit in the In the slow clock domain, a trigger interrupt signal is generated according to the synchronization signal. The cross-clock domain signal transmission method according to claim 1, wherein the edge detection module includes a first flip-flop, a second flip-flop, and a first logic circuit; the signal input terminal of the first flip-flop receives all For the initial interrupt signal, the clock signal terminal of the first flip-flop receives the first clock signal, and the output terminal of the first flip-flop is electrically connected to the second flip-flop and the first logic circuit, respectively; The signal input terminal of the second flip-flop receives the output signal of the first flip-flop, the clock signal terminal of the second flip-flop receives the first clock signal, and the output terminal of the second flip-flop is connected to the first flip-flop. The inverting input terminal of the logic circuit is electrically connected; the forward input terminal of the first logic circuit is electrically connected to the output terminal of the first flip-flop, and the inverting input terminal of the first logic circuit is electrically connected to the The output terminal of the second flip-flop is electrically connected, and the output terminal of the first logic circuit is electrically connected with the flip circuit. The signal transmission method across clock domains according to claim 2, wherein the event trigger signal is a single pulse signal; and the first logic circuit is a logic AND gate. The cross-clock domain signal transmission method according to claim 2, wherein the flip circuit includes a multiplexer and a third flip-flop; the input terminal of the multiplexer and the output terminal of the first logic circuit are electrically connected Connected, the output terminal of the multiplexer and the input terminal of the third flip-flop are electrically connected Connection; the clock terminal of the third flip-flop receives the first clock signal, and the output terminal of the third flip-flop is electrically connected to the synchronization circuit. The cross-clock domain signal transmission method according to claim 4, wherein the synchronization circuit includes a fourth flip-flop and a fifth flip-flop; the input terminal of the fourth flip-flop and the output terminal of the third flip-flop Electrically connected, the clock terminal of the fourth flip-flop receives the second clock signal, the output terminal of the fourth flip-flop is electrically connected with the input terminal of the fifth flip-flop; the clock of the fifth flip-flop The terminal receives the second clock signal, and the output terminal of the fifth flip-flop is electrically connected to the edge-fetching circuit; the frequency of the first clock signal is higher than the frequency of the second clock signal. The cross-clock domain signal transmission method according to claim 5, wherein the edge-fetching circuit includes a sixth flip-flop and a second logic circuit; the input terminal of the sixth flip-flop and the output of the fifth flip-flop Terminal is electrically connected, the clock terminal of the sixth flip-flop receives the second clock signal, the output terminal of the sixth flip-flop is electrically connected with the second input terminal of the second logic circuit; the first The first input terminal of the two logic circuits is electrically connected with the output terminal of the fifth flip-flop; the second logic circuit is an "exclusive OR" gate. A cross-clock domain signal transmission circuit, the cross-clock domain signal transmission circuit includes: an edge detection module, used to perform edge detection on an initial interrupt signal in the fast clock domain and convert it into an event trigger signal; the event trigger signal is Single pulse signal; flip circuit, used to convert the event trigger signal into an edge signal; synchronization circuit, used to synchronize the edge signal to the slow clock domain and generate a synchronization signal; edge circuit, used according to the The synchronization signal generates a trigger interrupt signal in the slow clock domain. The cross-clock domain signal transmission circuit according to claim 7, wherein the edge detection module includes a first flip-flop, a second flip-flop, and a first logic circuit; the first flip-flop The signal input terminal of the first flip-flop receives the initial interrupt signal, the clock signal terminal of the first flip-flop receives the first clock signal, and the output terminal of the first flip-flop is connected to the second flip-flop and the first logic respectively. The circuit is electrically connected; the signal input terminal of the second flip-flop receives the output signal of the first flip-flop, the clock signal terminal of the second flip-flop receives the first clock signal, and the output of the second flip-flop Terminal is electrically connected to the inverting input terminal of the first logic circuit; the forward input terminal of the first logic circuit is electrically connected to the output terminal of the first flip-flop, and the inverting input terminal of the first logic circuit is electrically connected The phase input terminal is electrically connected with the output terminal of the second flip-flop, and the output terminal of the first logic circuit is electrically connected with the flip circuit. The cross-clock domain signal transmission circuit according to claim 8, wherein the first logic circuit is a logic AND gate. An electronic device, wherein at least one instruction is stored in the electronic device, and when the at least one instruction is executed by a processor, the cross-clock domain signal transmission method as described in any one of request items 1 to 6 is implemented.

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