CN116560457B - Inter-clock domain synchronization circuit and method based on IIC communication - Google Patents
Inter-clock domain synchronization circuit and method based on IIC communication Download PDFInfo
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- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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Abstract
The application provides a clock domain crossing synchronization circuit and a clock domain crossing synchronization method based on IIC communication, and relates to the technical field of electronic circuits. The inter-clock domain synchronization circuit based on IIC communication is suitable for a low-frequency system function scene, power consumption is increased without improving clock frequency of a system function domain, signal synchronization time can be reduced, subsequent read operation abnormality caused by overlong IIC domain write synchronization time is avoided, and overall reliability of the system is improved.
Description
Technical Field
The application relates to the technical field of electronic circuits, in particular to a clock domain crossing synchronization circuit and a clock domain crossing synchronization method based on IIC communication.
Background
In a clock domain crossing integrated circuit, since a source clock domain signal and a destination clock domain signal are respectively synchronized with respective corresponding clocks, the signals of the source clock domain are easy to turn over when being sampled by the destination clock, so that the destination clock domain is sampled to a metastable state signal, and in order to avoid circuit dysfunction caused by metastable state signal propagation, a signal synchronizing circuit is usually required to be arranged to solve the problem of metastable state signals, and particularly, the signals are beaten through 2-3 stages of registers of the destination clock domain.
IIC (Inter-Integrated Circuit) is a common serial communication bus protocol, mainly used for communication between a master device and a slave device, where the communication module and the functional module in the slave device belong to different clock domains, and therefore a signal synchronization circuit is required to avoid sampling a metastable signal in a destination clock domain. Compared with the read-write occurrence time and the read-synchronization beat time in the IIC domain, the clock frequency of the IIC domain is far higher than the clock frequency of the functional domain of the slave device in the normal state, so that the beat time of write synchronization in the slave device domain through the 2-3 level register is long, and further, when the IIC domain reads a certain register immediately after finishing writing, the risk of reading data which should be covered by write operation exists, and the subsequent read operation is abnormal.
Disclosure of Invention
Aiming at the defects existing in the prior art, the application provides a clock domain crossing synchronization circuit and a clock domain crossing synchronization method based on IIC communication, which solve the technical problem that the time for beating a signal synchronization circuit is too long in the prior art, so that the write synchronization time of the IIC domain is too long to cause the abnormality of subsequent read operation.
In one aspect, the present application provides a clock domain crossing synchronization circuit based on IIC communication, including: the system comprises a signal conversion module, a double-edge synchronization module and a combinational logic module;
the signal conversion module is used for receiving the pulse signal output by the IIC domain and converting the pulse signal into a level signal;
the double-edge synchronous module is connected with the signal conversion module and is used for receiving the level signal and carrying out double-edge sampling on the level signal to obtain a data signal of a system functional domain;
the combination logic module is connected with the double-edge synchronous module and is used for receiving the data signals, carrying out combination logic calculation on the data signals and outputting logic processing results.
Optionally, the double-edge synchronization module includes a first sampling unit, a second sampling unit and a third sampling unit;
the first sampling unit is connected with the signal conversion module, a first input end of the first sampling unit is used for receiving the level signal, a second input end of the first sampling unit is used for receiving a clock signal of the system functional domain, the first sampling unit is used for sampling the level signal in a rising edge mode, and an output end of the first sampling unit outputs a first data signal of the system functional domain;
the second sampling unit is connected with the first sampling unit, a first input end of the second sampling unit is used for receiving the first data signal, a second input end of the second sampling unit is used for receiving a clock signal of the system functional domain, the second sampling unit is used for performing falling edge sampling on the first data signal, and an output end of the first sampling unit outputs a second data signal of the system functional domain;
the third sampling unit is connected with the second sampling unit, a first input end of the third sampling unit is used for receiving the second data signal, a second input end of the third sampling unit is used for receiving a clock signal of the system functional domain, the third sampling unit is used for carrying out rising edge sampling on the second data signal, and an output end of the third sampling unit outputs a third data signal of the system functional domain.
Optionally, the first sampling unit and the third sampling unit are both rising edge triggers, and the second sampling unit is a falling edge trigger.
Optionally, the combinational logic module is connected with the second sampling unit and the third sampling unit respectively;
the first input end of the combination logic module is used for receiving the second data signal of the system functional domain, the second input end of the combination logic module is used for receiving the third data signal of the system functional domain, the combination logic module is used for carrying out combination logic calculation on the second data signal and the third data signal, and the output end of the combination logic module outputs a logic processing result.
Optionally, the combination logic adopted by the combination logic module is an exclusive or operator;
when the second data signal is equal to the third data signal, the logic processing result is 0;
when the second data signal is not equal to the third data signal, the logic processing result is 1.
Optionally, the signal conversion module includes a multiplexer, an inverter, and a register;
the inverter is connected to one of the input ends of the multiplexer, so that two input ends of the multiplexer respectively input opposite level signals;
the selection end of the multiplexer is used for receiving the pulse signal;
the multiplexer is connected with a first input end of the register, extracts a level signal between the two input ends based on the pulse signal, and outputs the level signal to the register;
the register is also connected with the double-edge synchronous module, a second input end of the register is used for receiving the clock signal of the IIC domain, and an output end of the register is used for transmitting the level signal to the double-edge synchronous module.
Optionally, the clock period of the system functional domain is twenty-nine times or less than the clock period of the IIC domain, and twenty-nine times or less than three times the clock period of the system functional domain.
According to the inter-clock domain synchronous circuit based on IIC communication, firstly, a signal conversion module is utilized to convert pulse signals output by an IIC domain into level signals, the accuracy of signal transmission between two clock domains is ensured, the time sequence requirement of signal processing is simplified, the influence of deviation and jitter of pulse signals on time sequences of different clock domains on subsequent circuit processing is avoided, secondly, double-edge sampling is carried out by utilizing a double-edge synchronous module, the time of signal synchronization is effectively reduced, the abnormal subsequent reading operation caused by overlong writing synchronous time of the IIC domain is avoided, the synchronous error caused by clock jitter can be reduced by adopting double-edge sampling, the sampling rate is improved on the premise of ensuring the synchronous accuracy, the system reliability is improved, meanwhile, the high-speed transmission of data is supported, and finally, the combined logic calculation is carried out on the data signals of the system functional domain by utilizing the combined logic module, and the logic processing result meeting the conditions is output. The circuit is suitable for a low-frequency system function scene, power consumption is increased without improving the clock frequency of a system function domain, signal synchronization time is reduced, subsequent read operation abnormality caused by overlong IIC domain write synchronization time is avoided, and the overall reliability of the system is improved.
In another aspect, the present application provides a clock domain crossing synchronization method based on IIC communication, which is applied to the clock domain crossing synchronization circuit based on IIC communication, and includes:
the signal conversion module receives a pulse signal output by the IIC domain, converts the pulse signal into a level signal and transmits the level signal to the double-edge synchronous module;
the double-edge synchronous module receives the level signal, carries out double-edge sampling on the level signal to obtain a data signal of a system functional domain, and transmits the data signal to the combinational logic module;
and the combination logic module receives the data signals, performs combination logic calculation on the data signals and outputs logic processing results.
Optionally, the double-edge synchronization module includes a first sampling unit, a second sampling unit and a third sampling unit; the double-edge synchronous module receives the level signal and carries out double-edge sampling on the level signal to obtain a data signal of a system functional domain, and the double-edge synchronous module comprises:
the first sampling unit respectively receives the level signal and the clock signal of the system functional domain, then carries out rising edge sampling on the level signal and outputs a first data signal of the system functional domain;
the second sampling unit respectively receives the first data signal and the clock signal of the system functional domain, then carries out falling edge sampling on the first data signal and outputs a second data signal of the system functional domain;
and the third sampling unit is used for sampling the rising edge of the second data signal after receiving the second data signal and the clock signal of the system functional domain respectively and outputting the third data signal of the system functional domain.
Optionally, the combination logic adopted by the combination logic module is an exclusive or operator; the combination logic module receives the data signals, performs combination logic calculation on the data signals, and outputs logic processing results, wherein the combination logic module comprises:
the combination logic module receives the second data signal output by the second sampling unit and the third data signal output by the third sampling unit respectively, performs combination logic calculation on the second data signal and the third data signal, and outputs a logic processing result;
when the second data signal is equal to the third data signal, the logic processing result is 0;
when the second data signal is not equal to the third data signal, the logic processing result is 1.
According to the inter-clock domain synchronization method for IIC communication, the received pulse signals output by the IIC domain are converted into the level signals through the signal conversion module, the time sequence requirement of signal processing is simplified, the influence of deviation and jitter of the pulse signals on time sequences of different clock domains on subsequent circuit processing is avoided, double-edge sampling is carried out through the double-edge synchronization module, the time for signal synchronization is effectively shortened, the abnormality of subsequent reading operation caused by overlong writing synchronization time of the IIC domain is avoided, meanwhile, the synchronization error caused by clock jitter is reduced, the sampling rate and the system reliability are improved, and finally the combination logic calculation is carried out through the combination logic module, and the logic processing result is output. The method is suitable for the functional scene of the low-frequency system, effectively shortens the signal synchronization time, avoids the abnormal subsequent reading operation caused by overlong IIC domain writing synchronization time, and improves the overall reliability of the system.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application. The objectives and other advantages of the application will be realized and attained by the structure particularly pointed out in the written description and claims thereof as well as the appended drawings.
The technical scheme of the application is further described in detail through the drawings and the embodiments.
Drawings
The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate the application and together with the embodiments of the application, serve to explain the application. In the drawings:
FIG. 1 is a schematic diagram of an overall structure of a clock domain crossing synchronization circuit based on IIC communication according to an embodiment of the present application;
FIG. 2 is a circuit diagram of a clock domain crossing synchronization circuit based on IIC communication in one embodiment provided by the present application;
FIG. 3 is a waveform diagram of a cross-clock domain synchronization circuit based on IIC communication in one embodiment provided by the present application;
FIG. 4 is a flowchart illustrating one operation of the inter-clock domain synchronization circuit based on IIC communication according to one embodiment of the present application;
fig. 5 is a flowchart of a method for synchronizing clock domains based on IIC communication in an embodiment of the present application.
In the figure:
in_vld, pulse signal; reg_vld, level signal; xosc, clock signal of system functional domain; clock signals of SCL and IIC domains; sync_vld0, the first data signal; sync_vld1, the second data signal; sync_vld2, third data signal; out_vld, logic processing result; mux, multiplexer; xor, exclusive or operator; reg, register; reg0, a first rising edge trigger; reg1, falling edge flip-flop; reg2, a second rising edge trigger.
Detailed Description
In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the present application, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art according to the specific circumstances.
The application provides a clock domain crossing synchronization circuit based on IIC communication, which comprises a signal conversion module, a double-edge synchronization module and a combination logic module, wherein the signal conversion module is used for receiving a pulse signal in_vld output by an IIC domain and converting the pulse signal in_vld into a level signal reg_vld, the double-edge synchronization module is connected with the signal conversion module and used for receiving the level signal reg_vld and carrying out double-edge sampling on the level signal reg_vld to obtain a data signal of a system functional domain, the combination logic module is connected with the double-edge synchronization module and used for receiving the data signal, carrying out combination logic calculation on the data signal and outputting a logic processing result out_vld.
According to the inter-clock domain synchronous circuit based on IIC communication, firstly, a signal conversion module is used for converting a pulse signal in_vld output by an IIC domain into a level signal reg_vld, the accuracy of signal transmission between two clock domains is ensured, the time sequence requirement of signal processing is simplified, deviation and jitter of the pulse signal in_vld on time sequences of different clock domains are avoided to influence subsequent circuit processing, secondly, double-edge sampling is carried out by using a double-edge synchronous module, the time of signal synchronization is effectively reduced, follow-up read operation abnormality caused by overlong writing synchronous time of the IIC domain is avoided, and the synchronous error caused by clock jitter can be reduced by adopting double-edge sampling, the sampling rate is improved on the premise of ensuring synchronous accuracy, the system reliability is improved, meanwhile, high-speed transmission of data is supported, and finally, the combination logic module is used for carrying out combination logic calculation on the data signals of the system functional domain obtained by double-edge sampling, and outputting a logic processing result out_vld meeting the conditions. The circuit is suitable for a low-frequency system function scene, power consumption is improved without improving the clock frequency of a system function domain, the signal synchronization time can be reduced, subsequent read operation abnormality caused by overlong IIC domain write synchronization time is avoided, and the overall reliability of the system is improved.
Specifically, in the above embodiment, as shown in fig. 1, the double-edge synchronization module includes a first sampling unit, a second sampling unit and a third sampling unit, where the first sampling unit is connected to the signal conversion module, a first input end of the first sampling unit is used to receive the level signal reg_vld, a second input end of the first sampling unit is used to receive the clock signal xosc of the system functional domain, the first sampling unit is used to perform rising edge sampling on the level signal reg_vld, and an output end of the first sampling unit outputs the first data signal sync_vld0 of the system functional domain; the second sampling unit is connected with the first sampling unit, a first input end of the second sampling unit is used for being connected with a first data signal sync_vld0, a second input end of the second sampling unit is used for receiving a clock signal xosc of a system functional domain, the second sampling unit is used for carrying out falling edge sampling on the first data signal sync_vld0, and an output end of the first sampling unit outputs a second data signal sync_vld1 of the system functional domain; the third sampling unit is connected with the second sampling unit, a first input end of the third sampling unit is used for receiving a second data signal sync_vld1, a second input end of the third sampling unit is used for receiving a clock signal xosc of a system functional domain, the third sampling unit is used for carrying out rising edge sampling on the second data signal sync_vld1, and an output end of the third sampling unit outputs a third data signal sync_vld2 of the system functional domain.
In this embodiment, the dual-edge synchronization module is specifically provided with three sampling units, the three sampling units are all arranged in a system functional domain, after the signal conversion module converts the pulse signal in_vld into the level signal reg_vld, the pulse signal in_vld is sequentially subjected to beat in turn through the three sampling units to reduce the probability of occurrence of metastable states of the data signal, unlike the traditional metastable state elimination mode, the second sampling unit in the dual-edge synchronization module provided by the application uses the falling edge of the clock signal xosc in the system functional domain to beat, and specifically referring to fig. 3, after the dual-edge synchronization module, the pulse signal in_vld output by the IIC domain is synchronized to complete effective signal synchronization after the clock cycles of the two longest system functional domains, thereby shortening the synchronization time.
Specifically, for the inter-clock domain synchronous circuit based on IIC communication provided by the application, the time for synchronizing asynchronous signals is shortened, the occurrence probability of metastable state is further explained, firstly, the metastable state is usually eliminated by adopting a two-beat method in the prior art, because the first beat of sampling cannot avoid taking the time when the input signal jumps, but the second beat of sampling takes the signal stable after the first beat passes through one clock cycle, and the time for converting the metastable state to the determined level can be considered to be less than one period, which is just the condition for eliminating the metastable state. The application has a delay of one clock period from the shortest sampling of the input signal to the shortest sampling of the output signal, meets the condition of basically eliminating metastable state, and simultaneously, because the metastable state is easier to occur in the process of synchronizing the slow clock domain to the fast clock domain, the process beats time is shorter, and therefore, on the premise of recognizing that the metastable state can be stably eliminated from the slow clock domain to the fast clock domain, the metastable state can be stably eliminated under the low-frequency clock system scene by the inter-clock domain synchronous circuit based on IIC communication.
Further, the first sampling unit and the third sampling unit are both rising edge triggers, and the second sampling unit is a falling edge trigger.
In this embodiment, as shown in fig. 2 and 3, the sampling unit specifically uses a trigger to perform a beat, where the second sampling unit uses a falling edge trigger reg1 to perform a beat on a falling edge, and the first rising edge trigger reg0 used by the first sampling unit and the second rising edge trigger reg2 used by the third sampling unit are both rising edge triggers.
Specifically, in the above embodiment, as shown in fig. 1, the combinational logic module is connected to the second sampling unit and the third sampling unit, the first input terminal of the combinational logic module is used for receiving the second data signal sync_vld1 of the system functional domain, the second input terminal of the combinational logic module is used for receiving the third data signal sync_vld2 of the system functional domain, the combinational logic module is used for performing combinational logic computation on the second data signal sync_vld1 and the third data signal sync_vld2, and the output terminal of the combinational logic module outputs the logic processing result out_vld.
In this embodiment, the combinational logic module performs preprocessing on the second data signal sync_vld1 output by the second sampling unit and the third data signal sync_vld2 output by the third sampling unit, so as to avoid an unstable time window of the input signal and further cause adverse effects, so that combinational logic calculation is performed in advance, and on the premise of ensuring the accuracy of the output result, the reliability of data transmission is improved.
Further, as shown in fig. 2, the combinational logic adopted by the combinational logic module is an exclusive-or operator xor; when the second data signal sync_vld1 is equal to the third data signal sync_vld2, the logic processing result is 0; when the second data signal sync_vld1 is not equal to the third data signal sync_vld2, the logic processing result is 1.
In this embodiment, the synchronization of the asynchronous signals can be achieved by using the xor operator xor without introducing a latch or other synchronization element in the circuit, specifically, the combinational logic module receives the second data signal sync_vld1 output by the second sampling unit and the third data signal sync_vld2 output by the third sampling unit for comparison, when the second data signal sync_vld1 and the third data signal sync_vld2 are not output at a high level, when the second data signal sync_vld1 and the third data signal sync_vld2 are the same, the output is at a low level, and when the output is at a high level, the signal is correctly synchronized into the system function clock domain.
Specifically, in the above embodiment, as shown in fig. 2, the signal conversion module includes a multiplexer mux, an inverter, and a register reg, where the inverter is connected to one of input terminals of the multiplexer mux, so that two input terminals of the multiplexer mux respectively input opposite level signals, a selection terminal of the multiplexer mux is used for receiving the pulse signal in_vld, the multiplexer mux is connected to a first input terminal of the register reg, the multiplexer mux extracts a level signal between the two input terminals based on the pulse signal in_vld, and outputs the level signal to the register reg, the register reg is further connected to the double-edge synchronization module, a second input terminal of the register reg is used for receiving the clock signal SCL of the IIC domain, and an output terminal of the register reg is used for transmitting the level signal reg_vld to the double-edge synchronization module.
In this embodiment, in the process of performing cross-clock domain synchronization, the pulse signal in_vld output by the IIC domain needs to be converted into the level signal reg_vld first, so as to ensure the accuracy of signal transmission between two clock domains, and the pulse signal in_vld may have time sequence deviation and jitter in different clock domains, so that the subsequent circuit processing process is affected. In the application, the signal conversion module is realized by adopting a mode of combining a multiplexer mux, an inverter and a register reg, specifically, a pulse signal in_vld output by an IIC is input to a selection end of the multiplexer mux, an output end of the inverter is connected to an input end of the multiplexer mux, so that the multiplexer mux selects a level signal from different input ends to output based on the pulse signal in_vld, and finally, the signal output by the multiplexer mux is input to the register reg, and the level signal reg_vld is output through an output end of the register reg. The application only gives one realization mode of the signal conversion module adopting a combination mode of a multiplexer mux, an inverter and a register reg, in particular, the number of the inverter and the multiplexer mux can be regulated according to the requirement so as to realize different level signals reg_vld output, wherein the inverter can invert the input signals, convert the high level into the low level or convert the low level into the high level, the multiplexer mux can select different input signals according to the selection signals, and the register reg can temporarily store the input signals and output the input signals when required.
Specifically, in the above embodiment, the clock period of the IIC domain is twenty-nine times or less and the clock period of the IIC domain is twenty-nine times or less.
In this embodiment, the inter-clock domain synchronization circuit based on IIC communication provided by the present application is mainly applied to a low-frequency clock system scenario, that is, the clock frequency of the IIC domain is far higher than the clock frequency of the slave device system functional domain, and the relationship satisfied between the clock frequency of the IIC domain and the clock frequency of the system functional domain needs to be determined based on a class of more limited operation flows existing in the IIC communication process, and for example, as shown in fig. 4, the specific flow is as follows: the procedure requires that the data written into the register can be correctly read out in the next read operation, specifically, assuming that the clock frequency of the IIC domain is 400KHz and the clock frequency of the system function domain is 32.768KHz, the time of the IIC STOP-IIC BUS IDLE-IIC START in the procedure is related to the clock frequency of the IIC domain based on the characteristic of the IIC domain, and in the case that the clock frequency of the IIC domain is 400kHz, the time of the procedure is 3.8us in total and is approximately one clock cycle of the IIC domain; in the process, operations of write Reg10, slave addr, reg10 addr, read Reg10 and the like are all basic modes of 8-bit data transmission and 1-bit response, each operation needs 9 clock cycles of the IIC domain, so that the whole operation process is started from the end of the IIC write Reg10 to the read Reg10, about (3×9+1) t_scl+3.8us=73.8us is required in total, the clock cycle of one more IIC domain begins to calculate the operation process time with the write Reg10 ACK response, and the clock cycle of the IIC domain t_xosc=30.5us, the clock cycle of the IIC domain t_scl=2.5us is taken as an example, the write synchronization time of the write Reg10 is twice the clock cycle of the system domain, namely 2×xosc=61.0, and the clock cycle of the write Reg10 is less than 73.8us, so that the correct time sequence requirement can be ensured. If the double-edge synchronous module provided by the application is not used for double-edge sampling, the write synchronous time of the write Reg10 is three times the clock cycle of the system functional domain, 3 x t_xosc=91.5 us, and 91.5us is greater than 73.8us, and the time sequence requirement is not met, so that the clock cycle of the system functional domain is limited to be less than or equal to twenty-nine times the clock cycle of the IIC domain, and twenty-nine times the clock cycle of the IIC domain is less than or equal to three times the clock cycle of the system functional domain, namely 2 x t_xosc is less than or equal to 29 x t_scl is less than or equal to 3 x t_xosc, and particularly preferably the clock cycle of the IIC domain, t_xosc=2.5 us, and the clock cycle of the system functional domain, t_xosc=30.5 us.
The application provides a clock domain crossing synchronization method based on IIC communication, which is applied to the clock domain crossing synchronization circuit based on IIC communication, as shown in fig. 5, and comprises the steps that firstly, a signal conversion module receives a pulse signal in_vld output by the IIC domain, converts the pulse signal in_vld into a level signal xosc and transmits the level signal to a double-edge synchronization module, then the double-edge synchronization module receives the level signal xosc, carries out double-edge sampling on the level signal to obtain a data signal of a system functional domain, transmits the data signal to a combination logic module, and finally, the combination logic module receives the data signal, carries out combination logic calculation on the data signal and outputs a logic processing result out_vld.
According to the inter-clock domain synchronization method for IIC communication, the signal conversion module is used for converting the pulse signal in_vld output by the IIC domain into the level signal reg_vld, so that the time sequence requirement of signal processing is simplified, the influence of deviation and jitter of the pulse signal in_vld on time sequences of different clock domains on subsequent circuit processing is avoided, the double-edge synchronization module is used for carrying out double-edge sampling, the time of signal synchronization is effectively reduced, the abnormal subsequent reading operation caused by overlong writing synchronization time of the IIC domain is avoided, the synchronization error caused by clock jitter is reduced, the sampling rate and the system reliability are improved, and finally the combination logic calculation is carried out through the combination logic module, so that the logic processing result is output. The method is suitable for the functional scene of the low-frequency system, effectively shortens the signal synchronization time, avoids the abnormal subsequent reading operation caused by overlong IIC domain writing synchronization time, and improves the overall reliability of the system.
Further, the double-edge synchronization module comprises a first sampling unit, a second sampling unit and a third sampling unit; the dual-edge synchronization module receives the level signal reg_vld and performs dual-edge sampling on the level signal reg_vld to obtain a data signal of the system function domain, and the dual-edge synchronization module comprises a first sampling unit, which receives the level signal reg_vld and a clock signal xosc of the system function domain respectively, performs rising-edge sampling on the level signal reg_vld and outputs a first data signal sync_vld0 of the system function domain, a second sampling unit, which receives the first data signal sync_vld0 and the clock signal xosc of the system function domain respectively, performs falling-edge sampling on the first data signal sync_vld0 and outputs a second data signal sync_vld1 of the system function domain, and finally a third sampling unit, which receives the second data signal nc_vld1 and the clock signal xosc of the system function domain respectively, performs rising-edge sampling on the second data signal sync_vld1 and outputs a third data signal sync_vld2 of the system function domain.
In this embodiment, the dual-edge synchronization module is specifically provided with three sampling units for beating, where the second sampling unit uses the clock signal falling edge of the system functional domain to beat, so as to shorten the signal synchronization time while eliminating the metastable state phenomenon, avoid the abnormal subsequent read operation caused by the overlong write synchronization time of the IIC domain, and improve the overall reliability of the system.
Further, the combination logic adopted by the combination logic module is an exclusive or operator xor; the combination logic module receives the data signals, performs combination logic calculation on the data signals and outputs a logic processing result, and comprises a combination logic module respectively receiving a second data signal sync_vld1 output by a second sampling unit and a third data signal sync_vld2 output by a third sampling unit, and performs combination logic calculation on the second data signal sync_vld1 and the third data signal sync_vld2 to output a logic processing result out_vld, wherein when the second data signal sync_vld1 is equal to the third data signal sync_vld2, the logic processing result is 0; when the second data signal sync_vld1 is not equal to the third data signal sync_vld2, the logic processing result is 1.
In this embodiment, the exclusive-or operator is used to perform the combinational logic computation on the second data signal sync_vld1 output by the second sampling unit and the third data signal sync_vld2 output by the third sampling unit, and output the logic processing result out_vld, so that the reliability of data transmission is improved on the premise of ensuring the correctness of the output result.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (8)
1. A cross-clock domain synchronization circuit based on IIC communication, comprising: the system comprises a signal conversion module, a double-edge synchronization module and a combinational logic module;
the signal conversion module is used for receiving the pulse signal output by the IIC domain and converting the pulse signal into a level signal;
the double-edge synchronous module is connected with the signal conversion module and is used for receiving the level signal and carrying out double-edge sampling on the level signal to obtain a data signal of a system functional domain;
the double-edge synchronization module comprises a first sampling unit, a second sampling unit and a third sampling unit, wherein the first sampling unit is connected with the signal conversion module, a first input end of the first sampling unit is used for receiving the level signal, a second input end of the first sampling unit is used for receiving a clock signal of the system functional domain, the first sampling unit is used for carrying out rising edge sampling on the level signal, and an output end of the first sampling unit outputs a first data signal of the system functional domain;
the second sampling unit is connected with the first sampling unit, a first input end of the second sampling unit is used for receiving the first data signal, a second input end of the second sampling unit is used for receiving a clock signal of the system functional domain, the second sampling unit is used for performing falling edge sampling on the first data signal, and an output end of the first sampling unit outputs a second data signal of the system functional domain;
the third sampling unit is connected with the second sampling unit, a first input end of the third sampling unit is used for receiving the second data signal, a second input end of the third sampling unit is used for receiving a clock signal of the system functional domain, the third sampling unit is used for carrying out rising edge sampling on the second data signal, and an output end of the third sampling unit outputs a third data signal of the system functional domain;
the combination logic module is connected with the double-edge synchronous module and is used for receiving the data signals, carrying out combination logic calculation on the data signals and outputting logic processing results.
2. The IIC communication-based cross-clock domain synchronization circuit of claim 1, wherein the first sampling unit and the third sampling unit are both rising edge flip-flops and the second sampling unit is a falling edge flip-flop.
3. The IIC communication-based cross-clock domain synchronization circuit of claim 1, wherein the combinational logic module is connected to the second sampling unit and the third sampling unit, respectively;
the first input end of the combination logic module is used for receiving the second data signal of the system functional domain, the second input end of the combination logic module is used for receiving the third data signal of the system functional domain, the combination logic module is used for carrying out combination logic calculation on the second data signal and the third data signal, and the output end of the combination logic module outputs a logic processing result.
4. The IIC communication-based cross-clock domain synchronization circuit of claim 3, wherein the combinational logic employed by the combinational logic module is an exclusive-or operator;
when the second data signal is equal to the third data signal, the logic processing result is 0;
when the second data signal is not equal to the third data signal, the logic processing result is 1.
5. The IIC communication-based cross-clock domain synchronization circuit of claim 1, wherein the signal conversion module comprises a multiplexer, an inverter, and a register;
the inverter is connected to one of the input ends of the multiplexer, so that two input ends of the multiplexer respectively input opposite level signals;
the selection end of the multiplexer is used for receiving the pulse signal;
the multiplexer is connected with a first input end of the register, extracts a level signal between the two input ends based on the pulse signal, and outputs the level signal to the register;
the register is also connected with the double-edge synchronous module, a second input end of the register is used for receiving the clock signal of the IIC domain, and an output end of the register is used for transmitting the level signal to the double-edge synchronous module.
6. The IIC communication-based cross-clock domain synchronization circuit of claim 1, wherein twice the clock period of the system functional domain is less than or equal to twenty-nine times the clock period of the IIC domain, and twenty-nine times the clock period of the IIC domain is less than or equal to three times the clock period of the system functional domain.
7. A method of synchronizing across clock domains based on IIC communication, wherein the method is applied to the IIC communication-based clock domain synchronizing circuit of any one of claims 1 to 6, the method comprising:
the signal conversion module receives a pulse signal output by the IIC domain, converts the pulse signal into a level signal and transmits the level signal to the double-edge synchronous module;
the double-edge synchronous module receives the level signal, carries out double-edge sampling on the level signal to obtain a data signal of a system functional domain, and transmits the data signal to the combinational logic module;
the double-edge synchronization module comprises a first sampling unit, a second sampling unit and a third sampling unit; the double-edge synchronous module receives the level signal and carries out double-edge sampling on the level signal to obtain a data signal of a system functional domain, and the double-edge synchronous module comprises:
the first sampling unit respectively receives the level signal and the clock signal of the system functional domain, then carries out rising edge sampling on the level signal and outputs a first data signal of the system functional domain;
the second sampling unit respectively receives the first data signal and the clock signal of the system functional domain, then carries out falling edge sampling on the first data signal and outputs a second data signal of the system functional domain;
the third sampling unit respectively receives the second data signal and the clock signal of the system functional domain, then carries out rising edge sampling on the second data signal and outputs a third data signal of the system functional domain;
and the combination logic module receives the data signals, performs combination logic calculation on the data signals and outputs logic processing results.
8. The IIC communication-based clock domain synchronization method of claim 7, wherein the combinational logic employed by the combinational logic module is an exclusive-or operator; the combination logic module receives the data signals, performs combination logic calculation on the data signals, and outputs logic processing results, wherein the combination logic module comprises:
the combination logic module receives the second data signal output by the second sampling unit and the third data signal output by the third sampling unit respectively, performs combination logic calculation on the second data signal and the third data signal, and outputs a logic processing result;
when the second data signal is equal to the third data signal, the logic processing result is 0;
when the second data signal is not equal to the third data signal, the logic processing result is 1.
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